|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
include/llvm/CodeGen/TargetSubtargetInfo.h 33 struct InstrStage;
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h 50 struct InstrStage;
References
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc17767 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc 626 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/AMDGPU/R600GenSubtargetInfo.inc 100 extern const llvm::InstrStage R600Stages[] = {
101 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
109 { 0, 0, 0, llvm::InstrStage::Required } // End stages
239 const MCReadAdvanceEntry *RA, const InstrStage *IS,
330 extern const llvm::InstrStage R600Stages[];
gen/lib/Target/ARC/ARCGenSubtargetInfo.inc 87 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc 426 extern const llvm::InstrStage ARMStages[] = {
427 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
528 { 0, 0, 0, llvm::InstrStage::Required } // End stages
19346 const MCReadAdvanceEntry *RA, const InstrStage *IS,
19592 extern const llvm::InstrStage ARMStages[];
gen/lib/Target/AVR/AVRGenSubtargetInfo.inc 435 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/BPF/BPFGenSubtargetInfo.inc 105 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/Hexagon/HexagonGenSubtargetInfo.inc 227 extern const llvm::InstrStage HexagonStages[] = {
228 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
373 { 0, 0, 0, llvm::InstrStage::Required } // End stages
4602 const MCReadAdvanceEntry *RA, const InstrStage *IS,
4704 extern const llvm::InstrStage HexagonStages[];
gen/lib/Target/Lanai/LanaiGenSubtargetInfo.inc 39 extern const llvm::InstrStage LanaiStages[] = {
40 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
44 { 0, 0, 0, llvm::InstrStage::Required } // End stages
168 const MCReadAdvanceEntry *RA, const InstrStage *IS,
237 extern const llvm::InstrStage LanaiStages[];
gen/lib/Target/MSP430/MSP430GenSubtargetInfo.inc 105 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/Mips/MipsGenSubtargetInfo.inc 3762 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc 159 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/PowerPC/PPCGenSubtargetInfo.inc 363 extern const llvm::InstrStage PPCStages[] = {
364 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
585 { 0, 0, 0, llvm::InstrStage::Required } // End stages
8084 const MCReadAdvanceEntry *RA, const InstrStage *IS,
8232 extern const llvm::InstrStage PPCStages[];
gen/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 176 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/Sparc/SparcGenSubtargetInfo.inc 97 extern const llvm::InstrStage SparcStages[] = {
98 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
108 { 0, 0, 0, llvm::InstrStage::Required } // End stages
459 const MCReadAdvanceEntry *RA, const InstrStage *IS,
549 extern const llvm::InstrStage SparcStages[];
gen/lib/Target/SystemZ/SystemZGenSubtargetInfo.inc 5088 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc 117 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/X86/X86GenSubtargetInfo.inc21314 const MCReadAdvanceEntry *RA, const InstrStage *IS,
gen/lib/Target/XCore/XCoreGenSubtargetInfo.inc 88 const MCReadAdvanceEntry *RA, const InstrStage *IS,
include/llvm/CodeGen/TargetSubtargetInfo.h 69 const MCReadAdvanceEntry *RA, const InstrStage *IS,
include/llvm/MC/MCInstrItineraries.h 110 const InstrStage *Stages = nullptr; ///< Array of stages selected
117 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S,
132 const InstrStage *beginStage(unsigned ItinClassIndx) const {
138 const InstrStage *endStage(unsigned ItinClassIndx) const {
154 for (const InstrStage *IS = beginStage(ItinClassIndx),
include/llvm/MC/MCSubtargetInfo.h 86 const InstrStage *Stages; // Instruction itinerary stages
97 const MCReadAdvanceEntry *RA, const InstrStage *IS,
lib/CodeGen/DFAPacketizer.cpp 90 for (const InstrStage *IS = InstrItins->beginStage(InsnClass),
lib/CodeGen/MachinePipeliner.cpp 920 for (const InstrStage &IS :
966 for (const InstrStage &IS :
lib/CodeGen/ScoreboardHazardRecognizer.cpp 45 const InstrStage *IS = ItinData->beginStage(idx);
46 const InstrStage *E = ItinData->endStage(idx);
128 for (const InstrStage *IS = ItinData->beginStage(idx),
147 case InstrStage::Required:
151 case InstrStage::Reserved:
187 for (const InstrStage *IS = ItinData->beginStage(idx),
198 case InstrStage::Required:
202 case InstrStage::Reserved:
215 if (IS->getReservationKind() == InstrStage::Required)
lib/CodeGen/TargetSubtargetInfo.cpp 22 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
lib/MC/MCSchedule.cpp 137 const InstrStage *I = IID.beginStage(SchedClass);
138 const InstrStage *E = IID.endStage(SchedClass);
lib/MC/MCSubtargetInfo.cpp 214 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
lib/Target/Hexagon/HexagonInstrInfo.cpp 4332 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h 68 extern const InstrStage HexagonStages[];