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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 2158 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2198 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2238 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2278 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2318 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2358 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2431 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2485 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2539 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2593 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2647 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
2701 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
70496 /*169060*/ OPC_CheckChild1Type, MVT::Untyped,
71731 /*171615*/ OPC_CheckChild1Type, MVT::Untyped,
72330 /*172780*/ OPC_CheckChild1Type, MVT::Untyped,
83475 /*193553*/ /*SwitchType*/ 32, MVT::Untyped,// ->193587
83480 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5,
83487 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5,
83931 /*194588*/ /*SwitchType*/ 12, MVT::Untyped,// ->194602
83935 MVT::Untyped, 2/*#Ops*/, 2, 3,
84021 /*194760*/ /*SwitchType*/ 12, MVT::Untyped,// ->194774
84025 MVT::Untyped, 2/*#Ops*/, 2, 3,
85122 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
85172 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
85222 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
85312 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
85359 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
85406 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
86246 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
86294 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
86342 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
86388 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
86433 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
86478 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
103724 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
103738 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
103790 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
103804 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
103892 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
103906 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
103958 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
103972 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
104250 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
104276 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
104459 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
104485 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
106645 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
106657 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
106671 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
106683 MVT::Untyped, 4/*#Ops*/, 2, 3, 4, 5, // Results = #7
106854 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
106866 MVT::Untyped, 2/*#Ops*/, 2, 3, // Results = #5
113887 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
113897 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
113955 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
113965 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114013 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114023 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114071 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114081 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114129 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114139 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114187 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
114197 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5188 /* 52 */ MVT::Untyped, MVT::Other,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3756 /* 40 */ MVT::Untyped, MVT::Other,
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2349 /* 45 */ MVT::Untyped, MVT::Other,
gen/lib/Target/Mips/MipsGenDAGISel.inc21473 MVT::Untyped, 2/*#Ops*/, 2, 1,
21480 MVT::Untyped, 2/*#Ops*/, 2, 1,
21489 MVT::Untyped, 2/*#Ops*/, 0, 1,
21495 MVT::Untyped, 2/*#Ops*/, 0, 1,
24113 MVT::Untyped, 2/*#Ops*/, 0, 1, // Results = #2
24340 MVT::Untyped, 2/*#Ops*/, 0, 1,
24346 MVT::Untyped, 2/*#Ops*/, 0, 1,
24352 MVT::Untyped, 2/*#Ops*/, 0, 1,
24358 MVT::Untyped, 2/*#Ops*/, 0, 1,
24367 MVT::Untyped, 2/*#Ops*/, 0, 1,
24379 MVT::Untyped, 2/*#Ops*/, 0, 1,
24385 MVT::Untyped, 2/*#Ops*/, 0, 1,
24391 MVT::Untyped, 2/*#Ops*/, 0, 1,
24397 MVT::Untyped, 2/*#Ops*/, 0, 1,
24406 MVT::Untyped, 2/*#Ops*/, 0, 1,
24488 MVT::Untyped, 2/*#Ops*/, 0, 1,
24494 MVT::Untyped, 2/*#Ops*/, 0, 1,
24500 MVT::Untyped, 2/*#Ops*/, 0, 1,
24509 MVT::Untyped, 2/*#Ops*/, 0, 1,
24520 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24526 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24532 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24538 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24549 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24555 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24561 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24567 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24578 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24584 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24590 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24596 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24607 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24613 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24619 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
24625 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
25924 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25931 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25944 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25951 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25964 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25971 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25984 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
25991 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26004 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26011 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26022 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26028 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26039 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26045 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26056 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26062 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26073 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26079 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26092 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26099 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26112 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26119 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26132 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26139 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26152 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26159 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26171 MVT::Untyped, 2/*#Ops*/, 1, 2,
26178 MVT::Untyped, 2/*#Ops*/, 1, 2,
26189 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26195 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26206 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26212 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26225 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26232 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26245 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26252 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26263 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26269 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26280 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26286 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26299 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26306 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26319 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26326 MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
26337 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26343 MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
26407 MVT::Untyped, 2/*#Ops*/, 0, 1,
26413 MVT::Untyped, 2/*#Ops*/, 0, 1,
26422 MVT::Untyped, 2/*#Ops*/, 0, 1,
26434 MVT::Untyped, 2/*#Ops*/, 0, 1,
26440 MVT::Untyped, 2/*#Ops*/, 0, 1,
26449 MVT::Untyped, 2/*#Ops*/, 0, 1,
gen/lib/Target/Mips/MipsGenFastISel.inc 898 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
938 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
2841 if (RetVT.SimpleTy != MVT::Untyped)
2853 if (RetVT.SimpleTy != MVT::Untyped)
2890 if (RetVT.SimpleTy != MVT::Untyped)
2902 if (RetVT.SimpleTy != MVT::Untyped)
3153 if (RetVT.SimpleTy != MVT::Untyped)
3168 if (RetVT.SimpleTy != MVT::Untyped)
3187 if (RetVT.SimpleTy != MVT::Untyped)
3205 if (RetVT.SimpleTy != MVT::Untyped)
3224 if (RetVT.SimpleTy != MVT::Untyped)
3242 if (RetVT.SimpleTy != MVT::Untyped)
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3932 /* 24 */ MVT::Untyped, MVT::Other,
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 3875 /* 7665*/ OPC_CheckChild1Type, MVT::Untyped,
18852 MVT::Untyped, 1/*#Ops*/, 0, // Results = #6
18854 MVT::Untyped, 4/*#Ops*/, 6, 3, 4, 5,
18861 MVT::Untyped, 2/*#Ops*/, 0, 1,
18883 MVT::Untyped, 1/*#Ops*/, 0, // Results = #6
18885 MVT::Untyped, 4/*#Ops*/, 6, 3, 4, 5,
18892 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
18894 MVT::Untyped, 2/*#Ops*/, 2, 1,
18916 MVT::Untyped, 1/*#Ops*/, 0, // Results = #6
18918 MVT::Untyped, 4/*#Ops*/, 6, 3, 4, 5,
18926 MVT::Untyped, 1/*#Ops*/, 0, // Results = #6
18928 MVT::Untyped, 4/*#Ops*/, 6, 3, 4, 5,
18937 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
18939 MVT::Untyped, 2/*#Ops*/, 2, 1,
18945 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
18947 MVT::Untyped, 2/*#Ops*/, 2, 1,
18971 MVT::Untyped, 1/*#Ops*/, 0, // Results = #6
18973 MVT::Untyped, 4/*#Ops*/, 6, 3, 4, 5,
18980 MVT::Untyped, 1/*#Ops*/, 0, // Results = #2
18982 MVT::Untyped, 2/*#Ops*/, 2, 1,
19008 MVT::Untyped, 1/*#Ops*/, 8, // Results = #9
19010 MVT::Untyped, 4/*#Ops*/, 9, 3, 4, 5,
19022 MVT::Untyped, 1/*#Ops*/, 4, // Results = #5
19024 MVT::Untyped, 2/*#Ops*/, 5, 1,
19254 /* 35956*/ /*SwitchType*/ 13, MVT::Untyped,// ->35971
19258 MVT::Untyped, 3/*#Ops*/, 2, 3, 4,
20388 MVT::Untyped, 3/*#Ops*/, 2, 3, 4,
20865 MVT::Untyped, MVT::i32, 4/*#Ops*/, 2, 3, 4, 5,
22065 MVT::Untyped, MVT::i32, 1/*#Ops*/, 0, // Results = #1 #2
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1854 /* 34 */ MVT::Untyped, MVT::Other,
gen/lib/Target/X86/X86GenDAGISel.inc41533 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41547 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41555 MVT::Untyped, 2/*#Ops*/, 0, 1,
41575 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41589 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41597 MVT::Untyped, 2/*#Ops*/, 0, 1,
41617 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41631 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41639 MVT::Untyped, 2/*#Ops*/, 0, 1,
41659 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41673 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41681 MVT::Untyped, 2/*#Ops*/, 0, 1,
41701 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41715 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41723 MVT::Untyped, 2/*#Ops*/, 0, 1,
41743 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41757 MVT::Untyped, 6/*#Ops*/, 0, 3, 4, 5, 6, 7,
41765 MVT::Untyped, 2/*#Ops*/, 0, 1,
gen/lib/Target/X86/X86GenFastISel.inc12617 if (RetVT.SimpleTy != MVT::Untyped)
12626 if (RetVT.SimpleTy != MVT::Untyped)
12635 if (RetVT.SimpleTy != MVT::Untyped)
12644 if (RetVT.SimpleTy != MVT::Untyped)
12653 if (RetVT.SimpleTy != MVT::Untyped)
12662 if (RetVT.SimpleTy != MVT::Untyped)
gen/lib/Target/X86/X86GenRegisterInfo.inc 4491 /* 56 */ MVT::Untyped, MVT::Other,
include/llvm/CodeGen/SelectionDAGNodes.h 2072 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 4725 if (PtrType == MVT::Untyped || PtrType.isExtended())
14334 if (PtrType == MVT::Untyped || PtrType.isExtended())
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 319 if (VT == MVT::Untyped) {
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1769 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None);
lib/CodeGen/ValueTypes.cpp 256 case MVT::Untyped: return "Untyped";
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1124 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
1252 const EVT ResTys[] = {MVT::Untyped, MVT::Other};
1280 MVT::Untyped, MVT::Other};
1392 const EVT ResTys[] = {MVT::Untyped, MVT::Other};
lib/Target/AArch64/AArch64ISelLowering.cpp11982 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0);
12024 Opcode, SDLoc(N), DAG.getVTList(MVT::Untyped, MVT::Other), Ops);
lib/Target/ARM/ARMISelDAGToDAG.cpp 3852 ResTys.push_back(MVT::Untyped);
3915 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
4720 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
4724 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
4751 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
4756 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
lib/Target/ARM/ARMISelLowering.cpp 9066 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0);
9080 DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other), Ops);
lib/Target/Mips/MipsISelLowering.cpp 1034 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
lib/Target/Mips/MipsSEISelLowering.cpp 309 if (VT == MVT::Untyped)
1270 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1291 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1346 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1350 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
lib/Target/SystemZ/SystemZISelLowering.cpp 2584 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1);
5053 MVT::Untyped, Hi, Lo);
5073 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::Other);
5102 SDVTList Tys = DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other);
6311 if (Op.getResNo() != 0 || VT == MVT::Untyped)
7805 if (VT == MVT::Untyped)
lib/Target/X86/X86ISelLowering.cpp23600 SDVTList VTs = DAG.getVTList(MVT::Untyped, MVT::Other);
utils/TableGen/CodeGenTarget.cpp 197 case MVT::Untyped: return "MVT::Untyped";