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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenCallingConv.inc 385 LocVT == MVT::v1i1) {
571 LocVT == MVT::v1i1) {
767 LocVT == MVT::v1i1) {
810 LocVT == MVT::v1i1) {
1073 LocVT == MVT::v1i1) {
1097 LocVT == MVT::v1i1) {
1390 LocVT == MVT::v1i1) {
1876 LocVT == MVT::v1i1) {
2143 LocVT == MVT::v1i1) {
2339 LocVT == MVT::v1i1) {
2658 if (LocVT == MVT::v1i1) {
3018 LocVT == MVT::v1i1 ||
3426 if (LocVT == MVT::v1i1) {
3588 LocVT == MVT::v1i1 ||
3788 LocVT == MVT::v1i1 ||
gen/lib/Target/X86/X86GenDAGISel.inc 7444 /* 15967*/ OPC_CheckChild1Type, MVT::v1i1,
7517 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
7541 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
7588 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
7611 MVT::v1i1, 2/*#Ops*/, 3, 9, // Results = #10
7633 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
7673 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
7754 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
27740 /* 56808*/ OPC_CheckType, MVT::v1i1,
27745 MVT::v1i1, 8/*#Ops*/, 0, 1, 4, 5, 6, 7, 8, 3,
27757 /* 56845*/ OPC_CheckType, MVT::v1i1,
27762 MVT::v1i1, 8/*#Ops*/, 0, 1, 4, 5, 6, 7, 8, 3,
27780 MVT::v1i1, 7/*#Ops*/, 0, 3, 4, 5, 6, 7, 2,
27795 MVT::v1i1, 7/*#Ops*/, 0, 3, 4, 5, 6, 7, 2,
27815 /* 56967*/ OPC_CheckType, MVT::v1i1,
27820 MVT::v1i1, 8/*#Ops*/, 3, 0, 4, 5, 6, 7, 8, 2,
27833 /* 57005*/ OPC_CheckType, MVT::v1i1,
27838 MVT::v1i1, 8/*#Ops*/, 3, 0, 4, 5, 6, 7, 8, 2,
27857 MVT::v1i1, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 1,
27873 MVT::v1i1, 7/*#Ops*/, 2, 3, 4, 5, 6, 7, 1,
28532 /* 58630*/ OPC_CheckType, MVT::v1i1,
28543 MVT::v1i1, 2/*#Ops*/, 6, 7,
28554 /* 58695*/ OPC_CheckType, MVT::v1i1,
28565 MVT::v1i1, 2/*#Ops*/, 6, 7,
28579 /* 58756*/ OPC_CheckType, MVT::v1i1,
28582 MVT::v1i1, 4/*#Ops*/, 0, 1, 2, 3,
28594 /* 58783*/ OPC_CheckType, MVT::v1i1,
28597 MVT::v1i1, 4/*#Ops*/, 0, 1, 2, 3,
28612 /* 58816*/ OPC_CheckType, MVT::v1i1,
28615 MVT::v1i1, 4/*#Ops*/, 0, 1, 2, 3,
28627 /* 58843*/ OPC_CheckType, MVT::v1i1,
28630 MVT::v1i1, 4/*#Ops*/, 0, 1, 2, 3,
28857 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
28870 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
28936 /* 59397*/ OPC_CheckType, MVT::v1i1,
28939 MVT::v1i1, 4/*#Ops*/, 3, 0, 1, 2,
28952 /* 59425*/ OPC_CheckType, MVT::v1i1,
28955 MVT::v1i1, 4/*#Ops*/, 3, 0, 1, 2,
28971 /* 59459*/ OPC_CheckType, MVT::v1i1,
28974 MVT::v1i1, 4/*#Ops*/, 3, 0, 1, 2,
28987 /* 59487*/ OPC_CheckType, MVT::v1i1,
28990 MVT::v1i1, 4/*#Ops*/, 3, 0, 1, 2,
29232 MVT::v1i1, 3/*#Ops*/, 2, 0, 1,
29246 MVT::v1i1, 3/*#Ops*/, 2, 0, 1,
31898 /* 66193*/ /*SwitchType*/ 41, MVT::v1i1,// ->66236
31909 MVT::v1i1, 2/*#Ops*/, 6, 7,
41880 /* 87530*/ OPC_SwitchType /*8 cases */, 13, MVT::v1i1,// ->87546
41884 MVT::v1i1, 2/*#Ops*/, 0, 1,
41974 /* 87712*/ OPC_SwitchType /*7 cases */, 31, MVT::v1i1,// ->87746
41983 MVT::v1i1, 2/*#Ops*/, 3, 4,
47410 /* 99351*/ /*SwitchType*/ 41, MVT::v1i1,// ->99394
47421 MVT::v1i1, 2/*#Ops*/, 6, 7,
48604 /*102089*/ OPC_CheckType, MVT::v1i1,
48615 MVT::v1i1, 2/*#Ops*/, 6, 7,
48622 /*102146*/ OPC_CheckType, MVT::v1i1,
48633 MVT::v1i1, 2/*#Ops*/, 6, 7,
48645 /*102210*/ OPC_CheckType, MVT::v1i1,
48656 MVT::v1i1, 2/*#Ops*/, 6, 7,
50342 /*106224*/ /*SwitchType*/ 41, MVT::v1i1,// ->106267
50353 MVT::v1i1, 2/*#Ops*/, 6, 7,
52589 /*111357*/ OPC_SwitchType /*9 cases */, 28, MVT::v1i1,// ->111388
52597 MVT::v1i1, 2/*#Ops*/, 7, 8,
55760 /*118187*/ OPC_CheckChild0Type, MVT::v1i1,
57307 /*121207*/ OPC_CheckChild0Type, MVT::v1i1,
194119 /*392336*/ OPC_CheckType, MVT::v1i1,
194144 /*392402*/ OPC_SwitchType /*6 cases */, 69, MVT::v1i1,// ->392474
194710 /*393708*/ OPC_CheckChild1Type, MVT::v1i1,
194894 /*394204*/ OPC_CheckChild1Type, MVT::v1i1,
200604 /*405880*/ OPC_CheckType, MVT::v1i1,
200609 MVT::v1i1, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
200627 /*405923*/ OPC_CheckType, MVT::v1i1,
200632 MVT::v1i1, 7/*#Ops*/, 0, 4, 5, 6, 7, 8, 3,
200652 /*405969*/ OPC_CheckType, MVT::v1i1,
200658 MVT::v1i1, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 9,
200668 /*406003*/ OPC_CheckType, MVT::v1i1,
200674 MVT::v1i1, 7/*#Ops*/, 2, 4, 5, 6, 7, 8, 9,
200687 /*406042*/ OPC_CheckType, MVT::v1i1,
200693 MVT::v1i1, 7/*#Ops*/, 0, 3, 4, 5, 6, 7, 2,
200698 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
200709 /*406088*/ OPC_CheckType, MVT::v1i1,
200715 MVT::v1i1, 7/*#Ops*/, 0, 3, 4, 5, 6, 7, 2,
200720 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
200731 /*406134*/ OPC_CheckType, MVT::v1i1,
200734 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
200744 /*406157*/ OPC_CheckType, MVT::v1i1,
200747 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
206694 MVT::v1i1, 2/*#Ops*/, 10, 11, // Results = #12
206714 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
206737 MVT::v1i1, 2/*#Ops*/, 10, 11, // Results = #12
206757 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
226970 MVT::v1i1, 6/*#Ops*/, 2, 3, 4, 5, 6, 1,
226975 MVT::v1i1, 2/*#Ops*/, 0, 1,
226990 MVT::v1i1, 6/*#Ops*/, 2, 3, 4, 5, 6, 1,
226995 MVT::v1i1, 2/*#Ops*/, 0, 1,
228483 /*466298*/ OPC_CheckType, MVT::v1i1,
228486 MVT::v1i1, 2/*#Ops*/, 0, 1,
228493 /*466318*/ OPC_SwitchType /*2 cases */, 11, MVT::v1i1,// ->466332
228496 MVT::v1i1, 2/*#Ops*/, 0, 1,
228510 /*466353*/ OPC_SwitchType /*3 cases */, 11, MVT::v1i1,// ->466367
228513 MVT::v1i1, 2/*#Ops*/, 0, 1,
228533 /*466401*/ OPC_SwitchType /*4 cases */, 11, MVT::v1i1,// ->466415
228536 MVT::v1i1, 2/*#Ops*/, 0, 1,
228562 /*466462*/ OPC_SwitchType /*5 cases */, 11, MVT::v1i1,// ->466476
228565 MVT::v1i1, 2/*#Ops*/, 0, 1,
228597 /*466536*/ OPC_SwitchType /*5 cases */, 11, MVT::v1i1,// ->466550
228600 MVT::v1i1, 2/*#Ops*/, 0, 1,
229165 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
229188 MVT::v1i1, 2/*#Ops*/, 10, 11, // Results = #12
229247 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
229270 MVT::v1i1, 2/*#Ops*/, 10, 11, // Results = #12
229313 MVT::v1i1, 2/*#Ops*/, 2, 9, // Results = #10
229331 MVT::v1i1, 2/*#Ops*/, 2, 8, // Results = #9
229373 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
229396 MVT::v1i1, 2/*#Ops*/, 10, 11, // Results = #12
229435 MVT::v1i1, 2/*#Ops*/, 11, 12, // Results = #13
229458 MVT::v1i1, 2/*#Ops*/, 10, 11, // Results = #12
231015 /*471340*/ OPC_CheckType, MVT::v1i1,
231018 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
231028 /*471363*/ OPC_CheckType, MVT::v1i1,
231031 MVT::v1i1, 3/*#Ops*/, 0, 1, 2,
231402 /*472033*/ /*SwitchType*/ 19, MVT::v1i1,// ->472054
231408 MVT::v1i1, 2/*#Ops*/, 0, 1,
231563 /*472327*/ /*SwitchType*/ 19, MVT::v1i1,// ->472348
231569 MVT::v1i1, 2/*#Ops*/, 0, 1,
233778 MVT::v1i1, 2/*#Ops*/, 1, 4, // Results = #5
234212 MVT::v1i1, 2/*#Ops*/, 1, 3, // Results = #4
240210 MVT::v1i1, 2/*#Ops*/, 1, 4, // Results = #5
240644 MVT::v1i1, 2/*#Ops*/, 1, 3, // Results = #4
gen/lib/Target/X86/X86GenRegisterInfo.inc 4480 /* 24 */ MVT::v1i1, MVT::Other,
include/llvm/Support/MachineValueType.h 116 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
147 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
207 FIRST_VECTOR_VALUETYPE = v1i1,
428 case v1i1:
652 case v1i1:
694 case v1i1:
903 if (NumElements == 1) return MVT::v1i1;
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 743 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type");
lib/CodeGen/ValueTypes.cpp 139 case MVT::v1i1: return "v1i1";
283 case MVT::v1i1: return VectorType::get(Type::getInt1Ty(Context), 1);
lib/Target/X86/X86ISelLowering.cpp 1292 addRegisterClass(MVT::v1i1, &X86::VK1RegClass);
1298 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1300 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1311 setOperationAction(ISD::LOAD, MVT::v1i1, Custom);
1316 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1350 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
2412 if (ValVT == MVT::v1i1)
2789 if (ValVT == MVT::v1i1)
2790 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3258 else if (RegVT == MVT::v1i1)
17539 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Elt);
21223 DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CondOp0, CondOp1,
21270 SDValue Cmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, Cond);
22663 SDValue IMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v1i1,
23091 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::v1i1, Src1, Imm);
23130 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::v1i1, Src1, Src2, CC, Sae);
23136 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::v1i1, Src1, Src2, CC);
23193 FCmp = DAG.getNode(X86ISD::FSETCCM, dl, MVT::v1i1, LHS, RHS,
23196 FCmp = DAG.getNode(X86ISD::FSETCCM_SAE, dl, MVT::v1i1, LHS, RHS,
38707 DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CMP00, CMP01,
40513 if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() &&
44758 if (VT == MVT::v1i1 && Src.getOpcode() == ISD::AND && Src.hasOneUse())
44761 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1,
44765 if (VT == MVT::v1i1 && Src.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
utils/TableGen/CodeGenTarget.cpp 80 case MVT::v1i1: return "MVT::v1i1";