reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

31414 /* 60880*/        OPC_CheckValueType, MVT::v2i8,
72824   return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;

include/llvm/Support/MachineValueType.h

  329       return (SimpleTy == MVT::v2i8  || SimpleTy == MVT::v1i16 ||
  446       case v2i8:
  637       case v2i8:
  708       case v2i8:
  917         if (NumElements == 2)   return MVT::v2i8;

lib/CodeGen/ValueTypes.cpp

  151   case MVT::v2i8:    return "v2i8";
  295   case MVT::v2i8:    return VectorType::get(Type::getInt8Ty(Context), 2);

lib/Target/AArch64/AArch64ISelLowering.cpp

 2623   case MVT::v2i8:

lib/Target/AArch64/AArch64TargetTransformInfo.cpp

  327     { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8,  3 },
  330     { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8,  3 },
  351     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8,  4 },
  354     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8,  4 },
  370     { ISD::FP_TO_SINT, MVT::v2i8,  MVT::v2f32, 1 },
  373     { ISD::FP_TO_UINT, MVT::v2i8,  MVT::v2f32, 1 },
  384     { ISD::FP_TO_SINT, MVT::v2i8,  MVT::v2f64, 2 },
  387     { ISD::FP_TO_UINT, MVT::v2i8,  MVT::v2f64, 2 },

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  135     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
  136     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
  137     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
  212   setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);

lib/Target/AMDGPU/R600ISelLowering.cpp

  111   setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
  189   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);

lib/Target/AMDGPU/SIISelLowering.cpp

  188   setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
  218   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
  312   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
  316   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
  669   for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {

lib/Target/ARM/ARMISelLowering.cpp

  911     for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
 8294   case MVT::v2i8:

lib/Target/ARM/ARMTargetTransformInfo.cpp

  241     { ISD::SINT_TO_FP,  MVT::v2f32, MVT::v2i8, 3 },
  242     { ISD::UINT_TO_FP,  MVT::v2f32, MVT::v2i8, 3 },
  273     { ISD::SINT_TO_FP,  MVT::v2f64, MVT::v2i8, 4 },
  274     { ISD::UINT_TO_FP,  MVT::v2f64, MVT::v2i8, 4 },
  364     { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 10 },
  365     { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 2 },

lib/Target/Hexagon/HexagonISelLowering.cpp

 1469   setLoadExtAction(ISD::EXTLOAD,  MVT::v2i16, MVT::v2i8, Legal);
 1470   setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
 1471   setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);

lib/Target/NVPTX/NVPTXISelLowering.cpp

  139   case MVT::v2i8:
 2302     case MVT::v2i8:
 4510     if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
 4793   case MVT::v2i8:

lib/Target/PowerPC/PPCISelLowering.cpp

  687     setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
  842       setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
  846       setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);

lib/Target/X86/X86ISelLowering.cpp

  846     for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
  854     setOperationAction(ISD::MUL,                MVT::v2i8,  Custom);
  938     setOperationAction(ISD::FP_TO_SINT,         MVT::v2i8,  Custom);
  943     setOperationAction(ISD::FP_TO_UINT,         MVT::v2i8,  Custom);
  990     setOperationAction(ISD::TRUNCATE,    MVT::v2i8,  Custom);
 1066       setLoadExtAction(LoadExtOp, MVT::v2i64, MVT::v2i8,  Legal);
 1733     setTruncStoreAction(MVT::v2i64, MVT::v2i8,  Legal);

lib/Target/X86/X86TargetTransformInfo.cpp

 1369     { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i8,   2 },
 1551     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i64,  1 }, // PSHUFB
 1610     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i16,  2 }, // PAND+PACKUSWB
 1614     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i32,  3 }, // PAND+3*PACKUSWB
 1622     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i64,  4 }, // PAND+3*PACKUSWB
 2546     { ISD::ADD,   MVT::v2i8,    2 },
 2571     { ISD::ADD,   MVT::v2i8,    2 },
 3544     { 3, MVT::v2i8,  10 }, //(load 6i8 and)  deinterleave into 3 x 2i8
 3551     { 4, MVT::v2i8,  12 }, //(load 8i8 and)   deinterleave into 4 x 2i8
 3564     { 3, MVT::v2i8,  7 },  //interleave 3 x 2i8  into 6i8 (and store)
 3570     { 4, MVT::v2i8,  12 }, //interleave 4 x 2i8  into 8i8 (and store)

utils/TableGen/CodeGenTarget.cpp

   91   case MVT::v2i8:     return "MVT::v2i8";