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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/TargetRegisterInfo.h 1147 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
References
lib/CodeGen/AggressiveAntiDepBreaker.cpp 144 << " " << printReg(r, TRI));
219 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
326 dbgs() << header << printReg(Reg, TRI);
342 dbgs() << header << printReg(Reg, TRI);
345 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g"
381 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
402 << printReg(AliasReg, TRI) << ")");
477 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
513 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
516 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
582 LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
591 dbgs() << " " << printReg(r, TRI);
616 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
654 LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
671 LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI));
693 << "(alias " << printReg(AliasReg, TRI) << " live)");
802 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
858 LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
961 << printReg(AntiDepReg, TRI) << ":");
969 LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
970 << printReg(NewReg, TRI) << "("
lib/CodeGen/AllocationOrder.cpp 45 dbgs() << ' ' << printReg(Hints[I], TRI);
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 798 << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
812 << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo());
897 OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo());
lib/CodeGen/CriticalAntiDepBreaker.cpp 469 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
649 << printReg(AntiDepReg, TRI) << " with "
651 << " using " << printReg(NewReg, TRI) << "!\n");
lib/CodeGen/DetectDeadLanes.cpp 527 dbgs() << printReg(Reg, nullptr)
lib/CodeGen/ExecutionDomainFix.cpp 248 LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
lib/CodeGen/GlobalISel/Localizer.cpp 161 LLVM_DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
lib/CodeGen/GlobalISel/RegBankSelect.cpp 166 LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
166 LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 464 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
466 LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
790 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
796 OS << printReg(VReg, TRI);
lib/CodeGen/InlineSpiller.cpp 963 LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
1122 << printReg(Original) << '\n');
lib/CodeGen/LiveDebugValues.cpp 339 dbgs() << printReg(Loc.RegNo, TRI);
342 dbgs() << printReg(Loc.SpillLocation.SpillBase, TRI);
964 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
971 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
978 LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
983 LLVM_DEBUG(dbgs() << "Restoring Register " << printReg(Reg, TRI) << '('
lib/CodeGen/LiveInterval.cpp 1037 OS << printReg(reg) << ' ';
lib/CodeGen/LiveIntervalUnion.cpp 89 << printReg(SI.value()->reg, TRI);
lib/CodeGen/LiveIntervals.cpp 1027 dbgs() << printReg(Reg);
lib/CodeGen/LivePhysRegs.cpp 133 OS << " " << printReg(*I, TRI);
lib/CodeGen/LiveRangeCalc.cpp 367 errs() << "Use of " << printReg(PhysReg, MRI->getTargetRegisterInfo())
378 errs() << "The register " << printReg(PhysReg, TRI)
lib/CodeGen/LiveRangeEdit.cpp 471 dbgs() << "Inflated " << printReg(LI.reg) << " to "
lib/CodeGen/LiveRegMatrix.cpp 104 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to "
105 << printReg(PhysReg, TRI) << ':');
122 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from "
123 << printReg(PhysReg, TRI) << ':');
lib/CodeGen/MIRPrinter.cpp 192 OS << printReg(Reg, TRI);
255 OS << printReg(I, TRI);
676 OS << printReg(LI.PhysReg, &TRI);
lib/CodeGen/MachineBasicBlock.cpp 399 OS << printReg(LI.PhysReg, TRI);
lib/CodeGen/MachineCopyPropagation.cpp 441 LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
442 << "\n with " << printReg(CopySrcReg, TRI)
lib/CodeGen/MachineFunction.cpp 503 OS << printReg(I->first, TRI);
505 OS << " in " << printReg(I->second, TRI);
lib/CodeGen/MachineOperand.cpp 433 OS << printReg(*Reg, TRI);
779 OS << printReg(Reg, TRI, 0, MRI);
879 OS << " " << printReg(i, TRI);
904 OS << printReg(Reg, TRI);
lib/CodeGen/MachineRegisterInfo.cpp 224 errs() << printReg(Reg, getTargetRegisterInfo())
233 errs() << printReg(Reg, getTargetRegisterInfo())
239 errs() << printReg(Reg, getTargetRegisterInfo())
245 errs() << printReg(Reg, getTargetRegisterInfo())
lib/CodeGen/MachineScheduler.cpp 1119 << printReg(Reg, TRI) << ':'
lib/CodeGen/MachineTraceMetrics.cpp 1137 LLVM_DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
lib/CodeGen/MachineVerifier.cpp 547 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
551 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
1695 errs() << printReg(Reg, TRI) << " is not a "
2287 errs() << "Virtual register " << printReg(*I)
2324 errs() << "Virtual register " << printReg(Reg)
2330 errs() << "Virtual register " << printReg(Reg)
2349 errs() << printReg(Reg, TRI) << " still has defs or uses\n";
lib/CodeGen/PHIElimination.cpp 278 LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
599 LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
lib/CodeGen/ReachingDefAnalysis.cpp 112 LLVM_DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr
lib/CodeGen/RegAllocBasic.cpp 221 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
lib/CodeGen/RegAllocFast.cpp 316 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI)
317 << " in " << printReg(AssignedReg, TRI));
344 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
345 << printReg(PhysReg, TRI) << '\n');
561 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI)
571 LLVM_DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding "
572 << printReg(PhysReg, TRI) << " is reserved already.\n");
583 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n");
612 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to "
613 << printReg(PhysReg, TRI) << '\n');
668 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg)
670 << " with hint " << printReg(Hint0, TRI) << '\n');
678 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
685 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
699 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
706 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
717 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
898 LLVM_DEBUG(dbgs() << ' ' << printReg(Reg));
966 LLVM_DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI)
980 dbgs() << " " << printReg(Reg, TRI);
988 dbgs() << '=' << printReg(PhysRegState[Reg]);
lib/CodeGen/RegAllocGreedy.cpp 780 LLVM_DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n');
799 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost "
829 << printReg(PrevReg, TRI) << " to "
830 << printReg(PhysReg, TRI) << '\n');
1057 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
1152 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
1153 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1911 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
1914 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = ";
1922 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1963 << printReg(VirtReg.reg, TRI) << " may ");
1989 LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
2344 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore]
2444 LLVM_DEBUG(dbgs() << printReg(LREdit.get(i)));
2636 << printReg(PhysReg, TRI) << '\n');
2697 << printReg(PhysReg, TRI) << '\n');
2761 << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
2928 LLVM_DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI)
2929 << '(' << printReg(PhysReg, TRI) << ")\n");
2950 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
2950 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
lib/CodeGen/RegAllocPBQP.cpp 687 LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: "
696 LLVM_DEBUG(dbgs() << printReg(LI.reg, &TRI) << " ");
726 LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> "
883 OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')';
lib/CodeGen/RegUsageInfoCollector.cpp 184 dbgs() << printReg(PReg, TRI) << " ";
lib/CodeGen/RegisterClassInfo.cpp 158 dbgs() << ' ' << printReg(RCI.Order[I], TRI);
lib/CodeGen/RegisterCoalescer.cpp 623 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI));
1829 << printReg(CP.getSrcReg(), TRI) << " with "
1830 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n');
1851 dbgs() << printReg(CP.getDstReg()) << " in "
1853 << printReg(CP.getSrcReg()) << " in "
1856 dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
1857 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1964 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
1965 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
1968 dbgs() << printReg(CP.getDstReg(), TRI);
2075 << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
2735 LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
2737 << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
2775 LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
2798 LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
2802 LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
2845 LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@'
2956 LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
2968 LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
3346 LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS
3561 LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg)
3720 LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to "
lib/CodeGen/RegisterScavenging.cpp 290 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
563 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
574 << printReg(SReg, TRI) << "\n");
597 LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
613 LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
lib/CodeGen/RegisterUsageInfo.cpp 97 OS << printReg(PReg, TRI) << " ";
lib/CodeGen/RenameIndependentSubregs.cpp 136 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses()
138 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
144 LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg));
lib/CodeGen/ScheduleDAG.cpp 87 dbgs() << " Reg=" << printReg(getReg(), TRI);
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 1472 else dbgs() << printReg(LRegs[0], TRI);
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 621 OS << ' ' << printReg(R->getReg(),
lib/CodeGen/SplitKit.cpp 1149 << printReg(Edit->get(RegIdx)) << ')');
lib/CodeGen/StackMaps.cpp 195 OS << printReg(Loc.Reg, TRI);
202 OS << printReg(Loc.Reg, TRI);
211 OS << printReg(Loc.Reg, TRI);
235 OS << printReg(LO.Reg, TRI);
lib/CodeGen/TargetRegisterInfo.cpp 73 dbgs() << "Error: Super register " << printReg(*SR, this)
74 << " of reserved register " << printReg(Reg, this)
521 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
lib/CodeGen/VirtRegMap.cpp 142 OS << '[' << printReg(Reg, TRI) << " -> "
143 << printReg(Virt2PhysMap[Reg], TRI) << "] "
151 OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 543 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
617 << printReg(DestReg, TRI) << " at " << *MI);
637 << printReg(AccumReg, TRI) << " in MI " << *MI);
663 << printReg(DestReg, TRI) << "\n");
691 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
703 << printReg(I->first, TRI) << "\n");
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 762 << printReg(ScratchReg, TRI) << '\n');
781 << printReg(ScratchReg, TRI) << '\n');
lib/Target/AArch64/AArch64FrameLowering.cpp 2029 LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
2030 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
2120 LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
2121 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
2248 << ' ' << printReg(Reg, RegInfo);
2276 LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 249 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI)
250 << " to " << printReg(Rd, TRI) << '\n';);
255 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI)
342 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at ";
lib/Target/AArch64/AArch64SpeculationHardening.cpp 310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " ";
335 << printReg(MI_Reg.second, TRI)
345 << printReg(MI_Reg.second, TRI)
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp 30 OS << "Reg " << printReg(getRegister(), TRI);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 270 dbgs() << "Dest: " << printReg(Element.DestReg, TRI)
273 dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second)
503 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
504 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
553 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
554 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
698 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI)
703 LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n");
710 << "): " << printReg(Reg, TRI) << "\n");
721 LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI)
738 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI)
743 << "): " << printReg(Reg, TRI) << "\n");
782 << "): " << printReg(PHIReg, TRI) << "\n");
851 << "): " << printReg(PHIReg, TRI) << "\n");
874 << "): In:" << printReg(getBBSelectRegIn(), TRI)
875 << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {";
877 OS << printReg(LI, TRI) << " ";
917 << printReg(Register, MRI->getTargetRegisterInfo()) << " with "
918 << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
954 << printReg(NewRegister, MRI->getTargetRegisterInfo())
959 << printReg(Register, MRI->getTargetRegisterInfo())
961 << printReg(NewRegister, MRI->getTargetRegisterInfo())
1032 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << "\n");
1037 << printReg(Reg, MRI->getTargetRegisterInfo())
1041 << printReg(Reg, MRI->getTargetRegisterInfo())
1051 << printReg(Reg, TRI) << "\n");
1459 LLVM_DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI)
1490 LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1502 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1516 LLVM_DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI)
1534 LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1544 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1572 LLVM_DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI)
1576 LLVM_DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << " = PHI(");
1583 LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1594 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1619 LLVM_DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is "
1763 << "): " << printReg(DestRegister, TRI) << " = PHI("
1764 << printReg(IfSourceRegister, TRI) << ", "
1766 << printReg(CodeSourceRegister, TRI) << ", "
1951 << printReg(Reg, MRI->getTargetRegisterInfo())
1955 << printReg(Reg, MRI->getTargetRegisterInfo())
2039 LLVM_DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI));
2065 LLVM_DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n");
2162 LLVM_DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << " = PHI(");
2188 << printReg(NewBackedgeReg, TRI) << " = PHI("
2189 << printReg(CurrentBackedgeReg, TRI) << ", "
2191 << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", "
2197 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
2206 LLVM_DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", "
2237 << printReg(NewRegister, MRI->getTargetRegisterInfo())
2245 << printReg(Register, MRI->getTargetRegisterInfo())
2247 << printReg(NewRegister, MRI->getTargetRegisterInfo())
2265 LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n");
2268 LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI)
2269 << " SourceReg: " << printReg(SourceReg, TRI) << "\n");
2456 LLVM_DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI)
2460 LLVM_DEBUG(dbgs() << printReg(PHISource, TRI) << ", "
2464 LLVM_DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", "
2688 LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
2690 LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
2712 LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
2714 LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
2819 LLVM_DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI)
lib/Target/AMDGPU/GCNNSAReassign.cpp 298 dbgs() << " " << llvm::printReg((VRM->getPhys(LI->reg)), TRI);
335 << llvm::printReg((VRM->getPhys(Intervals.front()->reg)), TRI)
337 << llvm::printReg((VRM->getPhys(Intervals.back()->reg)), TRI)
lib/Target/AMDGPU/GCNRegBankReassign.cpp 234 OS << llvm::printReg(Reg, TRI);
238 OS << "<unassigned> " << llvm::printReg(Reg, TRI);
240 OS << llvm::printReg(Reg, TRI) << '('
241 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')';
lib/Target/AMDGPU/GCNRegPressure.cpp 52 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
450 dbgs() << " " << printReg(P.first, TRI)
455 dbgs() << " " << printReg(P.first, TRI)
466 dbgs() << " " << printReg(P.first, TRI)
lib/Target/AMDGPU/SIFrameLowering.cpp 1034 dbgs() << "Spilling FP to " << printReg(Spill.VGPR, TRI)
1052 dbgs() << "FP requires fallback spill to " << printReg(Spill.VGPR, TRI)
1056 printReg(MFI->SGPRForFPSaveRestoreCopy, TRI) << '\n');
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 423 OS << printReg(Reg, &TRI);
442 OS << printReg(Arg.getRegister(), &TRI);
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 345 << printReg(CopyToExec, TRI) << '\n');
lib/Target/ARC/ARCInstrInfo.cpp 313 LLVM_DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)
340 LLVM_DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI)
lib/Target/ARC/ARCRegisterInfo.cpp 68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
69 << " for FrameReg=" << printReg(FrameReg, TRI)
lib/Target/ARM/A15SDOptimizer.cpp 275 LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n");
645 << printReg(NewReg) << "\n");
lib/Target/ARM/ARMFrameLowering.cpp 1928 << printReg(Reg, TRI)
1948 LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
1955 << printReg(Reg, TRI)
1978 LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
2008 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2060 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2071 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
lib/Target/Hexagon/BitTracker.cpp 184 dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
829 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
836 dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
859 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
865 dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "
982 dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)
lib/Target/Hexagon/HexagonBitSimplify.cpp 175 OS << ' ' << printReg(R, P.TRI);
2459 dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
3133 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
3134 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
3135 << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
3255 << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
3256 << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
lib/Target/Hexagon/HexagonBitTracker.cpp 107 dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
lib/Target/Hexagon/HexagonBlockRanges.cpp 533 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
lib/Target/Hexagon/HexagonConstExtenders.cpp 452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
469 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
lib/Target/Hexagon/HexagonConstPropagation.cpp 93 dbgs() << printReg(Reg, TRI, SubReg);
615 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
664 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC
784 LLVM_DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
2801 dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
2817 dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
lib/Target/Hexagon/HexagonExpandCondsets.cpp 1145 << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
1146 << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
lib/Target/Hexagon/HexagonFrameLowering.cpp 1421 dbgs() << ' ' << printReg(R, &TRI);
1442 LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1545 dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1558 dbgs() << printReg(R, TRI) << ' ';
2258 LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
lib/Target/Hexagon/HexagonGenInsert.cpp 189 OS << ' ' << printReg(R, P.TRI);
430 OS << printReg(*I, P.TRI);
483 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
483 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
584 dbgs() << " " << printReg(I->first, HRI) << ":\n";
797 dbgs() << __func__ << ": " << printReg(VR, HRI)
862 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
867 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
914 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
914 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
915 << ',' << printReg(InsR, HRI) << ",#" << L << ",#"
1542 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
lib/Target/Hexagon/HexagonGenPredicate.cpp 78 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
226 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n");
231 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
lib/Target/Hexagon/HexagonHardwareLoops.cpp 359 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
lib/Target/Hexagon/HexagonInstrInfo.cpp 879 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
879 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
lib/Target/Hexagon/HexagonSplitDouble.cpp 140 dbgs() << ' ' << printReg(I, &TRI);
248 LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~");
271 LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI));
1150 LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
1151 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
1151 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
lib/Target/Hexagon/RDFLiveness.cpp 63 OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
lib/Target/X86/X86DomainReassignment.cpp 359 dbgs() << printReg(Reg, MRI->getTargetRegisterInfo(), 0, MRI);