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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10504 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 16, false>());
10513 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 32, false>());
10522 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 64, false>());
10531 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, false>());
10540 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, true>());
10630 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 16, false>());
10639 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 32, false>());
10648 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 64, false>());
10657 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, false>());
10666 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::UXTW, 8, true>());
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18021 AArch64_AM::getArithExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTW
18272 || AArch64_AM::getMemExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTW
29759 AArch64_AM::getArithExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTW
30010 || AArch64_AM::getMemExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTW
lib/Target/AArch64/AArch64FastISel.cpp 744 Addr.setExtendType(AArch64_AM::UXTW);
768 Addr.setExtendType(AArch64_AM::UXTW);
828 Addr.setExtendType(AArch64_AM::UXTW);
865 Addr.setExtendType(AArch64_AM::UXTW);
887 Addr.setExtendType(AArch64_AM::UXTW);
1070 Addr.getExtendType() == AArch64_AM::UXTW )
1081 if (Addr.getExtendType() == AArch64_AM::UXTW)
1857 if (Addr.getExtendType() == AArch64_AM::UXTW ||
2148 if (Addr.getExtendType() == AArch64_AM::UXTW ||
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 477 return AArch64_AM::UXTW;
495 return AArch64_AM::UXTW;
675 if (Ext == AArch64_AM::UXTW &&
lib/Target/AArch64/AArch64InstrInfo.cpp 791 case AArch64_AM::UXTW:
825 case AArch64_AM::UXTW:
lib/Target/AArch64/AArch64InstructionSelector.cpp 4525 return AArch64_AM::UXTW;
4548 return AArch64_AM::UXTW;
4617 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) {
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 1099 if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW ||
1252 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW ||
1265 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW;
1290 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) &&
1736 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW;
2746 .Case("uxtw", AArch64_AM::UXTW)
lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h 62 case AArch64_AM::UXTW: return "uxtw";
129 case 2: return AArch64_AM::UXTW;
156 case AArch64_AM::UXTW: return 2; break;
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 993 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
999 ExtType == AArch64_AM::UXTW) ) {