|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/ADT/Hashing.h 407 get_hashable_data(*first)))
420 get_hashable_data(*first)))
include/llvm/ADT/SCCIterator.h 159 NodeRef childN = *VisitStack.back().NextChild++;
include/llvm/ADT/STLExtras.h 528 using type = std::tuple<decltype(*declval<Iters>())...>;
556 return value_type(*std::get<Ns>(iterators)...);
include/llvm/ADT/SetVector.h 172 const key_type &V = *I;
include/llvm/Support/Automaton.h 139 for (auto *Head : Heads) {
lib/Analysis/BlockFrequencyInfoImpl.cpp 696 for (const auto *P : make_range(Irr.pred_begin(), Irr.pred_end())) {
723 for (const auto *P : make_range(Irr.pred_begin(), Irr.pred_end())) {
lib/Analysis/LoopPass.cpp 86 if (*I == L.getParentLoop()) {
189 for (Loop *L : LQ) {
lib/Analysis/RegionPass.cpp 67 for (Region *R : RQ) {
lib/Bitcode/Reader/MetadataLoader.cpp 379 for (auto &PH : PHs) {
lib/CodeGen/MachinePipeliner.cpp 535 for (SUnit *SU : Schedule.getInstructions(Cycle)) {
2308 if (ST.getInstrInfo()->isZeroCost((*I)->getInstr()->getOpcode()))
2310 assert(ProcItinResources.canReserveResources(*(*I)->getInstr()) &&
2312 ProcItinResources.reserveResources(*(*I)->getInstr());
2407 for (SUnit *I : getInstructions(cycle)) {
2485 (*I)->getInstr()->readsWritesVirtualRegister(Reg);
2486 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
2490 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) {
2494 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
2495 if (cycleScheduled(*I) == cycleScheduled(SU) && !(*I)->isSucc(SU)) {
2495 if (cycleScheduled(*I) == cycleScheduled(SU) && !(*I)->isSucc(SU)) {
2503 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
2511 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
2516 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 &&
2517 isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {
2527 if (S.getSUnit() != *I)
2529 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {
2537 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) {
2544 if (P.getSUnit() != *I)
2546 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {
2763 for (SUnit *SU : Instrs) {
2875 for (SUnit *CI : cycleInstrs->second) {
lib/MC/XCOFFObjectWriter.cpp 134 for (auto *Group : Groups)
334 for (const auto *Group : Section->Groups) {
335 for (const auto &Csect : Group->Csects) {
522 for (const auto *Group : Section->Groups) {
528 for (const auto &Csect : Group->Csects) {
571 for (auto *Group : Section->Groups) {
576 for (auto &Csect : Group->Csects) {
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 1026 for (MachineLoop *ExaminedLoop : NestedLoops) {
tools/clang/lib/Analysis/PathDiagnostic.cpp 379 if (*XI != *YI)
379 if (*XI != *YI)
380 return (*XI) < (*YI);
380 return (*XI) < (*YI);
1130 ID.AddString(*I);
tools/clang/lib/Format/UnwrappedLineFormatter.cpp 1035 formatChildren(State, (*I)->NewLine, /*DryRun=*/false, Penalty);
1036 Penalty += Indenter->addTokenToState(State, (*I)->NewLine, false);
1039 printLineState((*I)->Previous->State);
1040 if ((*I)->NewLine) {
1042 << (*I)->Previous->State.NextToken->Tok.getName()
tools/clang/lib/Serialization/ASTWriter.cpp 1851 for (const auto &Entry : SortedFiles) {
4837 for (const auto &I : SemaRef.PendingInstantiations) {
tools/clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp 499 os << "<tr><td></td><td>" << html::EscapeText(*I) << "</td></tr>\n";
tools/clang/tools/extra/clangd/TUScheduler.cpp 734 Request R = std::move(*I);
751 for (const auto &R : Requests)
tools/clang/utils/TableGen/NeonEmitter.cpp 2013 for (auto &I : V) {
tools/lldb/source/Target/StackFrameRecognizer.cpp 71 for (auto entry : m_recognizers) {
105 for (auto entry : m_recognizers) {
tools/llvm-exegesis/lib/Clustering.cpp 152 const size_t Q = *ToProcess.begin();
usr/include/c++/7.4.0/bits/deque.tcc 665 *__pos = _GLIBCXX_MOVE(__x_copy);
usr/include/c++/7.4.0/bits/predefined_ops.h 43 { return *__it1 < *__it2; }
43 { return *__it1 < *__it2; }
241 { return *__it == _M_value; }
283 { return bool(_M_pred(*__it)); }
351 { return !bool(_M_pred(*__it)); }
usr/include/c++/7.4.0/bits/stl_algo.h 871 *__result = _GLIBCXX_MOVE(*__first);
871 *__result = _GLIBCXX_MOVE(*__first);
1365 _ValueType __t = _GLIBCXX_MOVE(*__p);
1367 *(__p + __n - 1) = _GLIBCXX_MOVE(__t);
1388 _ValueType __t = _GLIBCXX_MOVE(*(__p + __n - 1));
1390 *__p = _GLIBCXX_MOVE(__t);
1566 *__result2 = _GLIBCXX_MOVE(*__first);
1572 *__result1 = _GLIBCXX_MOVE(*__first);
1572 *__result1 = _GLIBCXX_MOVE(*__first);
1577 *__result2 = _GLIBCXX_MOVE(*__first);
usr/include/c++/7.4.0/bits/stl_algobase.h 148 swap(*__a, *__b);
148 swap(*__a, *__b);
324 *__result = *__first;
324 *__result = *__first;
343 *__result = std::move(*__first);
343 *__result = std::move(*__first);
548 *--__result = std::move(*--__last);
548 *--__result = std::move(*--__last);
696 *__first = __tmp;
800 if (!(*__first1 == *__first2))
800 if (!(*__first1 == *__first2))
usr/include/c++/7.4.0/bits/stl_construct.h 108 std::_Destroy(std::__addressof(*__first));
usr/include/c++/7.4.0/bits/stl_deque.h 246 { return *(*this + __n); }
1454 return *begin();
1465 return *begin();
1478 return *__tmp;
1491 return *__tmp;
usr/include/c++/7.4.0/bits/stl_iterator.h 172 return *--__tmp;
1053 { return static_cast<reference>(*_M_current); }
usr/include/c++/7.4.0/bits/stl_numeric.h 154 __init = __binary_op(__init, *__first);
usr/include/c++/7.4.0/bits/stl_tempbuf.h 195 _GLIBCXX_MOVE(*__seed));
201 *__seed = _GLIBCXX_MOVE(*__prev);
usr/include/c++/7.4.0/bits/stl_uninitialized.h 83 std::_Construct(std::__addressof(*__cur), *__first);
83 std::_Construct(std::__addressof(*__cur), *__first);
utils/TableGen/AsmMatcherEmitter.cpp 1237 for (const CodeGenRegister &CGR : Registers) {
2600 for (const CodeGenRegister &Reg : Regs) {
2625 for (const CodeGenRegister &Reg : Regs) {
utils/TableGen/AsmWriterEmitter.cpp 504 for (const auto &Reg : Registers) {
utils/TableGen/CodeGenRegisters.cpp 1110 for (auto &Idx : SubRegIndices)
1133 for (auto &Reg : Registers)
1137 for (auto &Reg : Registers)
1147 for (auto &Reg : Registers)
1152 for (CodeGenSubRegIndex &SRI : SubRegIndices) {
1161 for (auto &Reg : Registers)
1167 for (auto &Reg : Registers)
1172 for (auto &Reg : Registers) {
1328 for (const CodeGenRegister &R : Registers) {
1367 for (const CodeGenSubRegIndex &Idx : SubRegIndices)
1375 for (const auto &Reg1 : Registers) {
1429 for (auto &Idx : SubRegIndices) {
1450 for (const auto &Idx : SubRegIndices) {
1469 for (auto &Idx2 : SubRegIndices) {
1525 for (const auto &Idx : SubRegIndices) {
1536 for (const auto &SubRegIndex : SubRegIndices) {
1613 for (const auto &Reg : Registers) {
1629 for (const CodeGenRegister &Reg : Registers) {
1779 for (auto &Reg : Registers) {
2042 for (auto &Register : Registers) {
2192 for (const auto &SubIdx : SubRegIndices) {
2226 for (auto &SubIdx : SubRegIndices) {
utils/TableGen/DFAPacketizerEmitter.cpp 522 for (unsigned NewState : applyInsnClass(InsnClass, State)) {
utils/TableGen/GlobalISelEmitter.cpp 1044 for (const auto &Predicate : predicates())
1581 for (const auto &Predicate : predicates())
2183 for (auto &P : predicates())
2208 dyn_cast<LLTOperandMatcher>(&**InsnMatcher.predicates_begin()))
2282 for (auto &OP : OM->predicates())
2292 for (auto &OP : Operands[0]->predicates())
2297 for (auto &OP : OM->predicates())
5339 for (auto &OP : OM->predicates())
5360 for (auto &OP : OM->predicates())
5372 return **Matcher.predicates_begin();
5376 for (auto &OP : OM->predicates())
5394 for (auto &OP : OM->predicates())
utils/TableGen/RegisterBankEmitter.cpp 199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
utils/TableGen/RegisterInfoEmitter.cpp 126 for (const auto &Reg : Registers)
178 for (const auto &Idx : SubRegIndices)
377 for (auto &RE : Regs) {
443 for (auto &RE : Regs) {
510 for (auto &RE : Regs) {
712 for (const auto &Idx : SubRegIndices) {
771 for (const auto &Idx : SubRegIndices) {
899 const auto &Reg = *I;
987 for (const auto &Idx : SubRegIndices) {
1005 for (const auto &Reg : Regs) {
1094 for (const auto &RE : Regs) {
1249 for (const auto &Idx : SubRegIndices) {
1258 for (const auto &Idx : SubRegIndices) {
1329 for (auto &Idx : SubRegIndices) {
1439 for (const auto &Reg : Regs) {
1474 for (auto &Idx : SubRegIndices) {
1657 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
1663 for (const CodeGenRegister &R : RegBank.getRegisters()) {