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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc75325 /*166945*/ /*SwitchOpcode*/ 60|128,3/*444*/, TARGET_VAL(ISD::FCOPYSIGN),// ->167393
gen/lib/Target/AMDGPU/R600GenDAGISel.inc10699 /* 40879*/ /*SwitchOpcode*/ 68|128,4/*580*/, TARGET_VAL(ISD::FCOPYSIGN),// ->41463
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38400 /* 97344*/ /*SwitchOpcode*/ 94|128,1/*222*/, TARGET_VAL(ISD::FCOPYSIGN),// ->97570
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13148 /* 24557*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::FCOPYSIGN),// ->24633
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc24171 /* 45536*/ /*SwitchOpcode*/ 33|128,2/*289*/, TARGET_VAL(ISD::FCOPYSIGN),// ->45829
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19057 /* 36383*/ /*SwitchOpcode*/ 68, TARGET_VAL(ISD::FCOPYSIGN),// ->36454
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1905 case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1249 ISDs.push_back(ISD::FCOPYSIGN);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1569 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
11084 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
12673 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
12693 N0.getOpcode() == ISD::FCOPYSIGN)
12694 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1);
12701 if (N1.getOpcode() == ISD::FCOPYSIGN)
12702 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1));
12707 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0));
13044 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
13048 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
13267 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1564 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1566 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
3074 case ISD::FCOPYSIGN:
4370 case ISD::FCOPYSIGN:
4381 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 73 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break;
1146 case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break;
1647 case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break;
1733 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N),
1918 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
2051 case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 411 case ISD::FCOPYSIGN:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 111 case ISD::FCOPYSIGN:
855 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
1241 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
1242 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
1990 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
2813 case ISD::FCOPYSIGN:
4154 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4024 case ISD::FCOPYSIGN: {
5004 case ISD::FCOPYSIGN:
5130 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6097 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
7572 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 259 case ISD::FCOPYSIGN: return "fcopysign";
lib/CodeGen/TargetLoweringBase.cpp 689 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 239 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
355 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
358 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
360 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
443 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
453 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
665 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
838 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
3051 case ISD::FCOPYSIGN:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 429 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
2130 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2178 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2239 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
lib/Target/AMDGPU/R600ISelLowering.cpp 233 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
234 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 372 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
373 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
8770 case ISD::FCOPYSIGN:
lib/Target/ARM/ARMISelLowering.cpp 773 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
942 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1308 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1309 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1373 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
9169 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
lib/Target/Hexagon/HexagonISelLowering.cpp 1384 ISD::FPOW, ISD::FCOPYSIGN}) {
lib/Target/Mips/MipsISelLowering.cpp 359 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
360 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1231 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
lib/Target/Mips/MipsSEISelLowering.cpp 140 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 563 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand);
565 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
2159 RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A);
lib/Target/PowerPC/PPCISelLowering.cpp 304 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
305 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
307 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
308 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
855 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
856 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
935 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
986 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
lib/Target/Sparc/SparcISelLowering.cpp 1636 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1637 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1638 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 574 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 185 ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
lib/Target/X86/X86ISelLowering.cpp 537 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
572 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
593 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
631 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
679 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
734 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
817 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
870 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
1115 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
1375 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
27715 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
36231 case ISD::FCOPYSIGN: