reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/BasicTTIImpl.h

 1218       ISDs.push_back(ISD::FEXP);

include/llvm/CodeGen/TargetLowering.h

  952       case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3894   case ISD::FEXP:
 4400   case ISD::FEXP:

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

   76     case ISD::FEXP:        R = SoftenFloatRes_FEXP(N); break;
 1149   case ISD::FEXP:       ExpandFloatRes_FEXP(N, Lo, Hi); break;
 2058     case ISD::FEXP:

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  420   case ISD::FEXP:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

   83   case ISD::FEXP:
  895   case ISD::FEXP:
 2856   case ISD::FEXP:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 4010   case ISD::FEXP:
 7765   case ISD::STRICT_FEXP:       NewOpc = ISD::FEXP;       break;

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 5005   return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  211   case ISD::FEXP:                       return "fexp";

lib/CodeGen/TargetLoweringBase.cpp

  770     setOperationAction(ISD::FEXP ,      VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  380   setOperationAction(ISD::FEXP,    MVT::f16,   Promote);
  381   setOperationAction(ISD::FEXP,    MVT::v4f16, Expand);
  382   setOperationAction(ISD::FEXP,    MVT::v8f16, Expand);
  834     setOperationAction(ISD::FEXP, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  266   setOperationAction(ISD::FEXP, MVT::f32, Custom);
  411     setOperationAction(ISD::FEXP, VT, Expand);
 1149   case ISD::FEXP:

lib/Target/AMDGPU/SIISelLowering.cpp

  362     setOperationAction(ISD::FEXP, MVT::f16, Custom);
  647     setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
 8586   case ISD::FEXP:

lib/Target/ARM/ARMISelLowering.cpp

  342       setOperationAction(ISD::FEXP, VT, Expand);
  787     setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
  808     setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
  824     setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
  953     setOperationAction(ISD::FEXP,       MVT::f64, Expand);
 1379     setOperationAction(ISD::FEXP, MVT::f16, Promote);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1430     ISD::FLOG10,  ISD::FEXP,    ISD::FEXP2,   ISD::FCEIL,   ISD::FTRUNC,

lib/Target/Mips/MipsISelLowering.cpp

  447   setOperationAction(ISD::FEXP,              MVT::f32,   Expand);

lib/Target/Mips/MipsSEISelLowering.cpp

  151     setOperationAction(ISD::FEXP, MVT::f16, Promote);

lib/Target/PowerPC/PPCISelLowering.cpp

  636       setOperationAction(ISD::FEXP, VT, Expand);
  970     setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
 1015     setOperationAction(ISD::FEXP , MVT::v4f32, Expand);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  186                     ISD::FEXP, ISD::FEXP2, ISD::FRINT}) {

lib/Target/X86/X86ISelLowering.cpp

  722   setOperationAction(ISD::FEXP, MVT::f80, Expand);
  739     setOperationAction(ISD::FEXP,      VT, Expand);
 1831          {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,