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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc105852 /*236673*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FNEARBYINT),// ->236767
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4279 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenDAGISel.inc44993 /* 99554*/ /*SwitchOpcode*/ 60, TARGET_VAL(ISD::FNEARBYINT),// ->99617
gen/lib/Target/ARM/ARMGenFastISel.inc 2714 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71365 /*150486*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::FNEARBYINT),// ->150550
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38654 /* 97834*/ /*SwitchOpcode*/ 68, TARGET_VAL(ISD::FNEARBYINT),// ->97905
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1702 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc24585 /* 46434*/ /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(ISD::FNEARBYINT),// ->46599
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19182 /* 36628*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FNEARBYINT),// ->36652
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 967 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1261 ISDs.push_back(ISD::FNEARBYINT);
include/llvm/CodeGen/TargetLowering.h 960 case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp13137 case ISD::FNEARBYINT:
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3944 case ISD::FNEARBYINT:
4389 case ISD::FNEARBYINT:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 84 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
1157 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break;
2064 case ISD::FNEARBYINT:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 425 case ISD::FNEARBYINT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 89 case ISD::FNEARBYINT:
901 case ISD::FNEARBYINT:
2862 case ISD::FNEARBYINT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4017 case ISD::FNEARBYINT: {
7773 case ISD::STRICT_FNEARBYINT: NewOpc = ISD::FNEARBYINT; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6044 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
7625 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 207 case ISD::FNEARBYINT: return "fnearbyint";
lib/CodeGen/TargetLoweringBase.cpp 773 setOperationAction(ISD::FNEARBYINT, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 411 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
447 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
458 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
475 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
491 setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal);
671 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
783 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
793 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 269 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
270 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
422 setOperationAction(ISD::FNEARBYINT, VT, Expand);
528 case ISD::FNEARBYINT:
1142 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
3776 case ISD::FNEARBYINT: // XXX - Should fround be handled?
lib/Target/AMDGPU/SIISelLowering.cpp 8591 case ISD::FNEARBYINT:
lib/Target/ARM/ARMISelLowering.cpp 344 setOperationAction(ISD::FNEARBYINT, VT, Expand);
793 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
813 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
829 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
958 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1347 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1363 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
lib/Target/Hexagon/HexagonISelLowering.cpp 1431 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
lib/Target/Mips/MipsSEISelLowering.cpp 144 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 548 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
lib/Target/PowerPC/PPCISelLowering.cpp 240 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
645 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
769 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
903 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
1061 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 336 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
386 Opcode = ISD::FNEARBYINT; break;
lib/Target/SystemZ/SystemZISelLowering.cpp 424 setOperationAction(ISD::FNEARBYINT, VT, Legal);
481 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
513 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 98 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
184 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
lib/Target/X86/X86ISelDAGToDAG.cpp 874 case ISD::FNEARBYINT:
884 case ISD::FNEARBYINT: Imm = 0xC; break;
5196 case ISD::FNEARBYINT:
5210 case ISD::FNEARBYINT: Imm = 0xC; break;
lib/Target/X86/X86ISelLowering.cpp 656 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
760 setOperationAction(ISD::FNEARBYINT, VT, Expand);
1036 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
1112 setOperationAction(ISD::FNEARBYINT, VT, Legal);
1427 setOperationAction(ISD::FNEARBYINT, VT, Legal);
36245 case ISD::FNEARBYINT: