|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc102003 /*228419*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102039 /*228491*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102064 /*228544*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FNEG),// ->228618
102121 /*228646*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102142 /*228683*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102156 /*228708*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102194 /*228775*/ /*SwitchOpcode*/ 20|128,1/*148*/, TARGET_VAL(ISD::FNEG),// ->228927
102286 /*228936*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102321 /*229000*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::FNEG),// ->229054
102361 /*229079*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102413 /*229181*/ /*SwitchOpcode*/ 108, TARGET_VAL(ISD::FNEG),// ->229292
102560 /*229470*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102565 /*229477*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102589 /*229525*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102594 /*229533*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102639 /*229622*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102664 /*229671*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102718 /*229775*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102765 /*229878*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102801 /*229962*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FNEG),// ->230056
102865 /*230081*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102886 /*230123*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102925 /*230194*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102938 /*230218*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
102958 /*230253*/ /*SwitchOpcode*/ 60|128,1/*188*/, TARGET_VAL(ISD::FNEG),// ->230445
103066 /*230454*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
103093 /*230507*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
103208 /*230724*/ /*SwitchOpcode*/ 117, TARGET_VAL(ISD::FNEG),// ->230844
103267 /*230862*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
103298 /*230939*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
103316 /*230980*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
103361 /*231091*/ /*SwitchOpcode*/ 112|128,1/*240*/, TARGET_VAL(ISD::FNEG),// ->231335
103469 /*231345*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
103511 /*231453*/ /*SwitchOpcode*/ 70, TARGET_VAL(ISD::FNEG),// ->231526
103549 /*231530*/ OPC_SwitchOpcode /*2 cases */, 39, TARGET_VAL(ISD::FNEG),// ->231573
105395 /*235824*/ /*SwitchOpcode*/ 62|128,1/*190*/, TARGET_VAL(ISD::FNEG),// ->236018
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4280 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc74105 /*163861*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
74122 /*163897*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
74396 /*164585*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
74840 /*165706*/ /*SwitchOpcode*/ 62|128,3/*446*/, TARGET_VAL(ISD::FNEG),// ->166156
gen/lib/Target/AMDGPU/R600GenDAGISel.inc10692 /* 40866*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::FNEG),// ->40879
gen/lib/Target/ARM/ARMGenDAGISel.inc41481 /* 91198*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
41549 /* 91352*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
42788 /* 94250*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43548 /* 96088*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43554 /* 96097*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43598 /* 96199*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43623 /* 96254*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43674 /* 96374*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43754 /* 96563*/ /*SwitchOpcode*/ 94|128,4/*606*/, TARGET_VAL(ISD::FNEG),// ->97173
43760 /* 96579*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
43787 /* 96636*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
44006 /* 97180*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
44031 /* 97234*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
gen/lib/Target/ARM/ARMGenFastISel.inc 2715 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68278 /*132205*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
68292 /*132228*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
68422 /*132491*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FNEG),// ->132565
gen/lib/Target/Mips/MipsGenDAGISel.inc26928 /* 50972*/ /*SwitchOpcode*/ 81|128,2/*337*/, TARGET_VAL(ISD::FNEG),// ->51313
gen/lib/Target/Mips/MipsGenFastISel.inc 1201 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70924 /*149553*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FNEG),// ->149590
gen/lib/Target/PowerPC/PPCGenDAGISel.inc16216 /* 43147*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
35933 /* 92390*/ /*SwitchOpcode*/ 32|128,5/*672*/, TARGET_VAL(ISD::FNEG),// ->93066
35942 /* 92410*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
35965 /* 92450*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
36050 /* 92610*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
36155 /* 92795*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
36228 /* 92928*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37409 /* 95545*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37420 /* 95565*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37435 /* 95590*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37448 /* 95612*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37460 /* 95633*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37475 /* 95658*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37488 /* 95680*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37500 /* 95701*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37515 /* 95726*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37550 /* 95793*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37570 /* 95830*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37584 /* 95853*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37596 /* 95874*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37611 /* 95899*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37640 /* 95953*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37660 /* 95990*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37674 /* 96013*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37686 /* 96034*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37701 /* 96059*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37730 /* 96113*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37750 /* 96150*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37764 /* 96173*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37776 /* 96194*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
37791 /* 96219*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1703 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12921 /* 24084*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
12926 /* 24091*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
12980 /* 24206*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
13008 /* 24265*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
13040 /* 24328*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
13068 /* 24387*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
13152 /* 24564*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
13325 /* 24894*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::FNEG),// ->24924
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3159 /* 5833*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FNEG),// ->5870
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc22155 /* 41626*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
22195 /* 41724*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
22278 /* 41877*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
22330 /* 41971*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
22370 /* 42057*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
22443 /* 42200*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
23855 /* 44960*/ /*SwitchOpcode*/ 60|128,4/*572*/, TARGET_VAL(ISD::FNEG),// ->45536
23864 /* 44978*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
23921 /* 45084*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
24061 /* 45335*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
24104 /* 45413*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19032 /* 36337*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::FNEG),// ->36383
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 968 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc75424 /*159105*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::FNEG),// ->159145
gen/lib/Target/X86/X86GenFastISel.inc 5914 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1577 case ISD::FNEG: return visitFNEG(N);
10920 FPOpcode = ISD::FNEG;
10943 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp);
11033 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
11046 if (N0.getOpcode() == ISD::FNEG) {
11065 if (N0.getOpcode() == ISD::FNEG)
11584 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags);
11591 DAG.getNode(ISD::FNEG, SL, VT,
11597 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) &&
11602 DAG.getNode(ISD::FNEG, SL, VT, N00), N01,
11603 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags);
11619 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags);
11631 DAG.getNode(ISD::FNEG, SL, VT,
11648 if (N00.getOpcode() == ISD::FNEG) {
11652 return DAG.getNode(ISD::FNEG, SL, VT,
11669 if (N0.getOpcode() == ISD::FNEG) {
11675 return DAG.getNode(ISD::FNEG, SL, VT,
11698 DAG.getNode(ISD::FNEG, SL, VT,
11709 DAG.getNode(ISD::FNEG, SL, VT,
11713 DAG.getNode(ISD::FNEG, SL, VT, N20),
11733 DAG.getNode(ISD::FNEG, SL, VT,
11761 DAG.getNode(ISD::FNEG, SL, VT,
11777 DAG.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)),
11780 DAG.getNode(ISD::FNEG, SL, VT,
11806 DAG.getNode(ISD::FNEG, SL, VT,
11811 DAG.getNode(ISD::FNEG, SL, VT,
11872 DAG.getNode(ISD::FNEG, SL, VT, Y), Flags);
11892 DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y,
11896 DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y,
11897 DAG.getNode(ISD::FNEG, SL, VT, Y), Flags);
11902 DAG.getNode(ISD::FNEG, SL, VT, Y), Flags);
11992 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
11996 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
12144 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
12145 return DAG.getNode(ISD::FNEG, DL, VT, N1, Flags);
12154 return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(1), Flags);
12157 return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(0), Flags);
12257 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
12258 return DAG.getNode(ISD::FNEG, DL, VT, N0);
12304 TLI.isOperationLegal(ISD::FNEG, VT))
12305 return DAG.getNode(ISD::FNEG, DL, VT,
12401 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
12402 SDValue RHSNeg = DAG.getNode(ISD::FNEG, DL, VT, N0);
12409 if (N0.getOpcode() == ISD::FNEG &&
12414 DAG.getNode(ISD::FNEG, DL, VT, N1, Flags), N2);
12428 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
12683 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
12684 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
12692 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
13164 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
13207 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)),
13267 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
lib/CodeGen/SelectionDAG/FastISel.cpp 1716 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1519 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1521 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
3077 case ISD::FNEG:
3176 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3178 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
4392 case ISD::FNEG:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 85 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
1158 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1204 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1400 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1401 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
2065 case ISD::FNEG:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 403 case ISD::FNEG:
790 case ISD::FNEG:
1263 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 90 case ISD::FNEG:
902 case ISD::FNEG:
2893 case ISD::FNEG:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4023 case ISD::FNEG:
4358 case ISD::FNEG:
4428 case ISD::FNEG:
4648 case ISD::FNEG:
4658 if (OpOpcode == ISD::FNEG) // --X -> X
4662 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 2967 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 670 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 190 case ISD::FNEG: return "fneg";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3708 if (N0.getOpcode() == ISD::FNEG) {
3712 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
5346 if (Op.getOpcode() == ISD::FNEG)
5463 if (Op.getOpcode() == ISD::FNEG)
lib/CodeGen/TargetLoweringBase.cpp 1591 case FNeg: return ISD::FNEG;
lib/Target/AArch64/AArch64ISelLowering.cpp 244 setOperationAction(ISD::FNEG, MVT::f128, Expand);
406 setOperationAction(ISD::FNEG, MVT::f16, Promote);
435 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
459 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
672 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
4868 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2383 if (Src.getOpcode() == ISD::FNEG) {
2423 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
2464 if (Src.getOpcode() == ISD::FNEG) {
2475 if (Lo.getOpcode() == ISD::FNEG) {
2480 if (Hi.getOpcode() == ISD::FNEG) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 426 setOperationAction(ISD::FNEG, VT, Expand);
502 setTargetDAGCombine(ISD::FNEG);
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
2470 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
3491 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3491 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3497 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3504 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3516 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3523 if (LHS.getOpcode() == ISD::FNEG)
3524 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3664 if (LHS.getOpcode() != ISD::FNEG)
3665 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3669 if (RHS.getOpcode() != ISD::FNEG)
3670 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3678 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3688 if (LHS.getOpcode() == ISD::FNEG)
3690 else if (RHS.getOpcode() == ISD::FNEG)
3693 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3699 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3712 if (LHS.getOpcode() == ISD::FNEG)
3714 else if (MHS.getOpcode() == ISD::FNEG)
3717 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3719 if (RHS.getOpcode() != ISD::FNEG)
3720 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3728 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3750 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3751 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3758 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3764 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3770 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3784 if (CvtSrc.getOpcode() == ISD::FNEG) {
3795 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3801 if (CvtSrc.getOpcode() == ISD::FNEG) {
3811 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3978 case ISD::FNEG:
lib/Target/AMDGPU/R600ISelLowering.cpp 1874 if (FNeg.getOpcode() != ISD::FNEG) {
lib/Target/AMDGPU/SIISelLowering.cpp 580 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
652 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
665 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
4059 case ISD::FNEG:
4342 case ISD::FNEG: {
7552 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
7696 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
7793 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
8768 case ISD::FNEG:
9258 if ((Vec.getOpcode() == ISD::FNEG ||
9671 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
lib/Target/ARM/ARMISelLowering.cpp 778 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
944 setOperationAction(ISD::FNEG, MVT::f64, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1428 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
lib/Target/Mips/MipsSEISelLowering.cpp 137 setOperationAction(ISD::FNEG, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 542 setOperationAction(ISD::FNEG, MVT::f16, Expand);
543 setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
lib/Target/PowerPC/PPCISelLowering.cpp 631 setOperationAction(ISD::FNEG, VT, Expand);
851 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
852 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
962 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
1007 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
7280 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
7299 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
7316 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
lib/Target/RISCV/RISCVISelLowering.cpp 953 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
962 if (Op0.getOpcode() == ISD::FNEG) {
1001 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1007 if (Op0.getOpcode() == ISD::FNEG) {
lib/Target/Sparc/SparcISelLowering.cpp 1612 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1719 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1722 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1741 setOperationAction(ISD::FNEG, MVT::f128, Custom);
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3049 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
lib/Target/SystemZ/SystemZISelLowering.cpp 473 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
505 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
2168 if (N->getOpcode() == ISD::FNEG) {
lib/Target/X86/X86ISelLowering.cpp 534 setOperationAction(ISD::FNEG, VT, Custom);
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
678 setOperationAction(ISD::FNEG, MVT::f128, Custom);
815 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
868 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
1113 setOperationAction(ISD::FNEG, VT, Custom);
1372 setOperationAction(ISD::FNEG, VT, Custom);
1854 setTargetDAGCombine(ISD::FNEG);
19741 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
19750 if (User->getOpcode() == ISD::FNEG)
27714 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
41418 if (N->getOpcode() == ISD::FNEG)
44936 case ISD::FNEG: return combineFneg(N, DAG, Subtarget);