|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc93914 /*213514*/ /*SwitchOpcode*/ 62|128,4/*574*/, TARGET_VAL(ISD::FP_TO_SINT),// ->214092
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4283 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc58220 /*127602*/ /*SwitchOpcode*/ 120|128,1/*248*/, TARGET_VAL(ISD::FP_TO_SINT),// ->127854
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7816 /* 29831*/ /*SwitchOpcode*/ 78|128,1/*206*/, TARGET_VAL(ISD::FP_TO_SINT),// ->30041
gen/lib/Target/ARM/ARMGenDAGISel.inc22491 /* 48325*/ OPC_SwitchOpcode /*2 cases */, 105, TARGET_VAL(ISD::FP_TO_SINT),// ->48434
37025 /* 81464*/ /*SwitchOpcode*/ 85|128,4/*597*/, TARGET_VAL(ISD::FP_TO_SINT),// ->82065
gen/lib/Target/ARM/ARMGenFastISel.inc 2718 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67104 /*128895*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FP_TO_SINT),// ->128947
gen/lib/Target/Mips/MipsGenDAGISel.inc29108 /* 55044*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FP_TO_SINT),// ->55072
gen/lib/Target/Mips/MipsGenFastISel.inc 1204 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc69045 /*145833*/ /*SwitchOpcode*/ 2|128,2/*258*/, TARGET_VAL(ISD::FP_TO_SINT),// ->146095
gen/lib/Target/PowerPC/PPCGenDAGISel.inc19094 /* 48355*/ /*SwitchOpcode*/ 122, TARGET_VAL(ISD::FP_TO_SINT),// ->48480
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1706 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12442 /* 23148*/ /*SwitchOpcode*/ 97|128,1/*225*/, TARGET_VAL(ISD::FP_TO_SINT),// ->23377
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc21816 /* 40898*/ /*SwitchOpcode*/ 16|128,1/*144*/, TARGET_VAL(ISD::FP_TO_SINT),// ->41046
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18438 /* 35330*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::FP_TO_SINT),// ->35467
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 971 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc40525 /* 84782*/ /*SwitchOpcode*/ 75|128,3/*459*/, TARGET_VAL(ISD::FP_TO_SINT),// ->85245
gen/lib/Target/X86/X86GenFastISel.inc 5917 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/TargetLowering.h 969 case ISD::STRICT_FP_TO_SINT: EqOpc = ISD::FP_TO_SINT; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1573 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
12812 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
12941 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
12982 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
lib/CodeGen/SelectionDAG/FastISel.cpp 1884 return selectCast(I, ISD::FP_TO_SINT);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2515 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2516 OpToUse = ISD::FP_TO_SINT;
2896 case ISD::FP_TO_SINT:
4180 case ISD::FP_TO_SINT:
4182 Node->getOpcode() == ISD::FP_TO_SINT, dl);
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 844 case ISD::FP_TO_SINT:
939 bool Signed = N->getOpcode() == ISD::FP_TO_SINT;
1649 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
1919 case ISD::FP_TO_SINT:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 119 case ISD::FP_TO_SINT:
501 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
502 NewOpc = ISD::FP_TO_SINT;
1699 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 401 case ISD::FP_TO_SINT:
529 case ISD::FP_TO_SINT:
606 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
607 NewOpc = ISD::FP_TO_SINT;
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 92 case ISD::FP_TO_SINT:
603 case ISD::FP_TO_SINT:
907 case ISD::FP_TO_SINT:
2013 case ISD::FP_TO_SINT:
2836 case ISD::FP_TO_SINT:
4164 case ISD::FP_TO_SINT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4390 case ISD::FP_TO_SINT:
4434 case ISD::FP_TO_SINT:
4485 case ISD::FP_TO_SINT:
7784 case ISD::STRICT_FP_TO_SINT: NewOpc = ISD::FP_TO_SINT; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3436 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
4901 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 328 case ISD::FP_TO_SINT: return "fp_to_sint";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 5963 ISD::FP_TO_SINT;
5981 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
6015 SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val);
6023 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
6025 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT,
lib/CodeGen/TargetLoweringBase.cpp 1621 case FPToSI: return ISD::FP_TO_SINT;
lib/Target/AArch64/AArch64FastISel.cpp 5185 if (!selectCast(I, ISD::FP_TO_SINT))
lib/Target/AArch64/AArch64ISelLowering.cpp 261 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
262 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
595 setTargetDAGCombine(ISD::FP_TO_SINT);
688 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
869 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
2494 if (Op.getOpcode() == ISD::FP_TO_SINT)
3062 case ISD::FP_TO_SINT:
9621 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11732 case ISD::FP_TO_SINT:
12089 case ISD::FP_TO_SINT:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 360 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
361 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
362 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
368 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
369 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
370 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
376 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
377 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
382 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
383 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
384 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 },
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
364 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
1154 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1550 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
2571 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
lib/Target/AMDGPU/R600ISelLowering.cpp 163 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
164 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
276 setTargetDAGCombine(ISD::FP_TO_SINT);
666 case ISD::FP_TO_SINT: {
1872 case ISD::FP_TO_SINT: {
lib/Target/AMDGPU/SIISelLowering.cpp 474 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
492 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 168 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
173 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
290 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
854 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
905 setTargetDAGCombine(ISD::FP_TO_SINT);
962 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
964 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
5365 if (Op.getOpcode() == ISD::FP_TO_SINT)
8524 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
8563 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
8676 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
9167 case ISD::FP_TO_SINT:
13508 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
14443 case ISD::FP_TO_SINT:
lib/Target/ARM/ARMTargetTransformInfo.cpp 262 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
264 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
266 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
280 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
282 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
284 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
297 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
299 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
301 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
303 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
305 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
307 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
309 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
311 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
313 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
315 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
lib/Target/Hexagon/HexagonISelLowering.cpp 1536 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1537 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1538 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
lib/Target/Mips/MipsISelLowering.cpp 361 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
377 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1243 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
2666 if (Val.getOpcode() != ISD::FP_TO_SINT ||
lib/Target/Mips/MipsSEISelLowering.cpp 355 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
1932 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 386 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 232 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
375 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
380 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
502 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
523 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
529 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
698 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
836 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
956 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
1004 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
7358 Op.getOpcode() == ISD::FP_TO_SINT
7364 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
7366 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
7374 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
7422 Op.getOpcode() == ISD::FP_TO_SINT
7429 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
7431 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
7451 if (Op.getOpcode() == ISD::FP_TO_SINT) {
7463 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
7474 True = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, True);
7477 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
7512 Op.getOpcode() == ISD::FP_TO_SINT) &&
8213 (V->getOperand(i).getOpcode() == ISD::FP_TO_SINT &&
10144 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, SDLoc(Op));
10233 case ISD::FP_TO_SINT:
12695 Opcode = ISD::FP_TO_SINT;
13088 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
13099 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
13259 assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT)
13286 unsigned ConvOpcode = (Opcode == ISD::FP_TO_SINT) ?
13421 if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) {
lib/Target/Sparc/SparcISelLowering.cpp 1509 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1511 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
3019 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
3346 case ISD::FP_TO_SINT:
3352 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
lib/Target/SystemZ/SystemZISelLowering.cpp 382 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
383 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal);
398 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
399 setOperationAction(ISD::FP_TO_SINT, MVT::v4f32, Legal);
lib/Target/X86/X86ISelDAGToDAG.cpp 807 case ISD::FP_TO_SINT:
817 case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break;
lib/Target/X86/X86ISelLowering.cpp 259 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
260 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
265 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
268 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
269 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
271 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
272 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
273 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
775 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
938 setOperationAction(ISD::FP_TO_SINT, MVT::v2i8, Custom);
939 setOperationAction(ISD::FP_TO_SINT, MVT::v4i8, Custom);
940 setOperationAction(ISD::FP_TO_SINT, MVT::v8i8, Custom);
941 setOperationAction(ISD::FP_TO_SINT, MVT::v2i16, Custom);
942 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
955 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1120 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
1122 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1302 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1304 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
1306 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
1378 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1379 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i16, MVT::v16i32);
1380 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i8, MVT::v16i32);
1381 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i1, MVT::v16i32);
1473 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1568 setOperationAction(ISD::FP_TO_SINT, VT, Legal);
1746 setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
19515 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT;
19523 if (Op.getOpcode() == ISD::FP_TO_SINT)
19579 SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i64, Src);
19592 SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Src);
25740 return DAG.getNode(ISD::FP_TO_SINT, dl, VT, Amt);
27702 case ISD::FP_TO_SINT:
28116 case ISD::FP_TO_SINT:
28118 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
28131 SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, PromoteVT, Src);
35621 if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) {
lib/Target/X86/X86TargetTransformInfo.cpp 1316 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 },
1317 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 },
1318 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 },
1319 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
1320 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 },
1321 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 },
1503 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
1504 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
1579 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },