reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

70808 /*149255*/  /*SwitchOpcode*/ 1|128,2/*257*/, TARGET_VAL(ISD::FREM),// ->149516

include/llvm/CodeGen/TargetLowering.h

  945       case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
 2310     case ISD::FREM:

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1567   case ISD::FREM:               return visitFREM(N);
12626     return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1, N->getFlags());

lib/CodeGen/SelectionDAG/FastISel.cpp

 1821     return selectBinaryOp(I, ISD::FREM);

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 4012   case ISD::FREM:
 4350   case ISD::FREM:

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

   91     case ISD::FREM:        R = SoftenFloatRes_FREM(N); break;
 1171   case ISD::FREM:       ExpandFloatRes_FREM(N, Lo, Hi); break;
 2082     case ISD::FREM:

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  374   case ISD::FREM:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

  131   case ISD::FREM:
  953   case ISD::FREM:
 2760   case ISD::FREM:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 4001   case ISD::FREM:
 5001     case ISD::FREM:
 5025   case ISD::FREM:
 5123   case ISD::FREM:
 7758   case ISD::STRICT_FREM:       NewOpc = ISD::FREM;       break;

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

  682   void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  257   case ISD::FREM:                       return "frem";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 2485   case ISD::FREM: {

lib/CodeGen/TargetLoweringBase.cpp

 1603   case FRem:           return ISD::FREM;

lib/Target/AArch64/AArch64ISelLowering.cpp

  224   setOperationAction(ISD::FREM, MVT::f32, Expand);
  225   setOperationAction(ISD::FREM, MVT::f64, Expand);
  226   setOperationAction(ISD::FREM, MVT::f80, Expand);
  246   setOperationAction(ISD::FREM, MVT::f128, Expand);
  362   setOperationAction(ISD::FREM,    MVT::f16,   Promote);
  363   setOperationAction(ISD::FREM,    MVT::v4f16, Expand);
  364   setOperationAction(ISD::FREM,    MVT::v8f16, Expand);
  674     setOperationAction(ISD::FREM, MVT::v1f64, Expand);
  867   setOperationAction(ISD::FREM, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  272   setOperationAction(ISD::FREM, MVT::f32, Custom);
  273   setOperationAction(ISD::FREM, MVT::f64, Custom);
  413     setOperationAction(ISD::FREM, VT, Expand);
  563   case ISD::FREM:
 1138   case ISD::FREM: return LowerFREM(Op, DAG);

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

  401   case ISD::FREM:

lib/Target/AMDGPU/SIISelLowering.cpp

 8568   case ISD::FREM:
 8742   case ISD::FREM:

lib/Target/ARM/ARMISelLowering.cpp

  206   setOperationAction(ISD::FREM, VT, Expand);
  334       setOperationAction(ISD::FREM, VT, Expand);
  769     setOperationAction(ISD::FREM, MVT::v2f64, Expand);
  941     setOperationAction(ISD::FREM,       MVT::f64, Expand);
 1304   setOperationAction(ISD::FREM,      MVT::f64, Expand);
 1305   setOperationAction(ISD::FREM,      MVT::f32, Expand);
 1372     setOperationAction(ISD::FREM, MVT::f16, Promote);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1383        {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
 1428     ISD::FREM,    ISD::FNEG,    ISD::FABS,    ISD::FSQRT,   ISD::FSIN,

lib/Target/Mips/MipsISelLowering.cpp

  450   setOperationAction(ISD::FREM,              MVT::f32,   Expand);
  451   setOperationAction(ISD::FREM,              MVT::f64,   Expand);

lib/Target/Mips/MipsSEISelLowering.cpp

  135     setOperationAction(ISD::FREM, MVT::f16, Promote);

lib/Target/NVPTX/NVPTXISelLowering.cpp

  571   for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,

lib/Target/PowerPC/PPCISelLowering.cpp

  241   setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
  275   setOperationAction(ISD::FREM , MVT::f64, Expand);
  280   setOperationAction(ISD::FREM , MVT::f32, Expand);
  630       setOperationAction(ISD::FREM, VT, Expand);
  917         setOperationAction(ISD::FREM, MVT::f128, Expand);
  933     setOperationAction(ISD::FREM, MVT::v4f64, Expand);
  984     setOperationAction(ISD::FREM, MVT::v4f32, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  149       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,

lib/Target/Sparc/SparcISelLowering.cpp

 1619   setOperationAction(ISD::FREM , MVT::f128, Expand);
 1624   setOperationAction(ISD::FREM , MVT::f64, Expand);
 1629   setOperationAction(ISD::FREM , MVT::f32, Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  435       setOperationAction(ISD::FREM, VT, Expand);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

   93          {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})

lib/Target/X86/X86ISelLowering.cpp

  331   setOperationAction(ISD::FREM             , MVT::f32  , Expand);
  332   setOperationAction(ISD::FREM             , MVT::f64  , Expand);
  333   setOperationAction(ISD::FREM             , MVT::f80  , Expand);
  334   setOperationAction(ISD::FREM             , MVT::f128 , Expand);
  733     setOperationAction(ISD::FREM,      VT, Expand);
 1831          {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,
36230   case ISD::FREM: