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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 70 /* 35*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
88 /* 69*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
106 /* 100*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
122 /* 129*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
143 /* 166*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
160 /* 198*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
178 /* 230*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
194 /* 259*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
236 /* 341*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
254 /* 373*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
270 /* 402*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
308 /* 477*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
326 /* 508*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
342 /* 537*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
363 /* 574*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
380 /* 606*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
398 /* 638*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
414 /* 667*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
456 /* 749*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
474 /* 781*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
490 /* 810*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
535 /* 897*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
553 /* 928*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
569 /* 957*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
590 /* 994*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
607 /* 1026*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
625 /* 1058*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
641 /* 1087*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
683 /* 1169*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
701 /* 1201*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
717 /* 1230*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
755 /* 1305*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
773 /* 1336*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
789 /* 1365*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
810 /* 1402*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
827 /* 1434*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
845 /* 1466*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
861 /* 1495*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
903 /* 1577*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
921 /* 1609*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
937 /* 1638*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1879 /* 3390*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1891 /* 3412*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1904 /* 3434*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1914 /* 3452*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1952 /* 3545*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1965 /* 3567*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
1975 /* 3585*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
65529 /*159706*/ OPC_SwitchOpcode /*2 cases */, 35, TARGET_VAL(ISD::SIGN_EXTEND),// ->159745
65573 /*159791*/ OPC_SwitchOpcode /*2 cases */, 34, TARGET_VAL(ISD::SIGN_EXTEND),// ->159829
65666 /*159982*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::SIGN_EXTEND),// ->160005
65670 /*159988*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
65697 /*160035*/ OPC_SwitchOpcode /*2 cases */, 21, TARGET_VAL(ISD::SIGN_EXTEND),// ->160060
65701 /*160042*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
66768 /*162004*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::SIGN_EXTEND),// ->162125
66778 /*162022*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
66799 /*162059*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
66820 /*162096*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
67234 /*162846*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::SIGN_EXTEND),// ->162916
67405 /*163155*/ /*SwitchOpcode*/ 70, TARGET_VAL(ISD::SIGN_EXTEND),// ->163228
69190 /*166413*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::SIGN_EXTEND),// ->166491
69196 /*166423*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
69210 /*166447*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
69224 /*166471*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
69325 /*166661*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::SIGN_EXTEND),// ->166715
69490 /*166969*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::SIGN_EXTEND),// ->167026
83278 /*193139*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::SIGN_EXTEND),// ->193188
83358 /*193307*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::SIGN_EXTEND),// ->193351
86680 /*200142*/ OPC_SwitchOpcode /*3 cases */, 62, TARGET_VAL(ISD::SIGN_EXTEND),// ->200208
86702 /*200187*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
86776 /*200335*/ OPC_SwitchOpcode /*3 cases */, 56, TARGET_VAL(ISD::SIGN_EXTEND),// ->200395
86797 /*200377*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87195 /*201132*/ OPC_SwitchOpcode /*2 cases */, 118, TARGET_VAL(ISD::SIGN_EXTEND),// ->201254
87205 /*201151*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87226 /*201188*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87247 /*201225*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87503 /*201687*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::SIGN_EXTEND),// ->201757
87698 /*202058*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87704 /*202068*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87718 /*202092*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87732 /*202116*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
87888 /*202404*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::SIGN_EXTEND),// ->202458
92632 /*210866*/ OPC_SwitchOpcode /*3 cases */, 60, TARGET_VAL(ISD::SIGN_EXTEND),// ->210930
92653 /*210910*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
94615 /*214822*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::SIGN_EXTEND),// ->214866
94692 /*214971*/ /*SwitchOpcode*/ 59|128,1/*187*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->215162
94858 /*215307*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::SIGN_EXTEND),// ->215361
94944 /*215490*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::SIGN_EXTEND),// ->215534
95225 /*216014*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::SIGN_EXTEND),// ->216058
107950 /*241125*/ /*SwitchOpcode*/ 42|128,2/*298*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->241427
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63046 /*137518*/ /*SwitchOpcode*/ 37|128,2/*293*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->137815
gen/lib/Target/ARM/ARMGenDAGISel.inc 7146 /* 14623*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::SIGN_EXTEND),// ->14721
7152 /* 14633*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
7168 /* 14665*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
7183 /* 14695*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
8103 /* 16831*/ OPC_SwitchOpcode /*6 cases */, 73, TARGET_VAL(ISD::SIGN_EXTEND),// ->16908
8342 /* 17381*/ OPC_SwitchOpcode /*6 cases */, 76, TARGET_VAL(ISD::SIGN_EXTEND),// ->17461
33802 /* 74374*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::SIGN_EXTEND),// ->74472
33808 /* 74384*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
33824 /* 74416*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
33839 /* 74446*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
34036 /* 74882*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::SIGN_EXTEND),// ->74958
47257 /*104859*/ /*SwitchOpcode*/ 60|128,1/*188*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->105051
52814 /*117878*/ /*SwitchOpcode*/ 20|128,2/*276*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->118158
gen/lib/Target/ARM/ARMGenFastISel.inc 2724 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AVR/AVRGenDAGISel.inc 1384 /* 2407*/ /*SwitchOpcode*/ 9, TARGET_VAL(ISD::SIGN_EXTEND),// ->2419
gen/lib/Target/BPF/BPFGenDAGISel.inc 1819 /* 3171*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::SIGN_EXTEND),// ->3204
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67162 /*128999*/ /*SwitchOpcode*/ 25|128,2/*281*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->129284
gen/lib/Target/Mips/MipsGenDAGISel.inc16120 /* 29758*/ /*SwitchOpcode*/ 7|128,5/*647*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->30409
gen/lib/Target/Mips/MipsGenFastISel.inc 1208 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc53038 /*114496*/ OPC_SwitchOpcode /*2 cases */, 61, TARGET_VAL(ISD::SIGN_EXTEND),// ->114561
53177 /*114752*/ OPC_SwitchOpcode /*2 cases */, 103, TARGET_VAL(ISD::SIGN_EXTEND),// ->114859
53197 /*114788*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
53226 /*114838*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
69285 /*146357*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->146494
gen/lib/Target/PowerPC/PPCGenDAGISel.inc10697 /* 26671*/ /*SwitchOpcode*/ 84|128,64/*8276*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->34951
40021 /*100629*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::SIGN_EXTEND),// ->100715
40033 /*100650*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
40054 /*100686*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1712 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2976 /* 5495*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SIGN_EXTEND),// ->5516
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 4245 /* 8415*/ OPC_SwitchOpcode /*3 cases */, 46, TARGET_VAL(ISD::SIGN_EXTEND),// ->8465
4251 /* 8426*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4261 /* 8443*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4275 /* 8469*/ OPC_SwitchOpcode /*2 cases */, 42, TARGET_VAL(ISD::SIGN_EXTEND),// ->8515
4282 /* 8481*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4289 /* 8493*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4464 /* 8800*/ OPC_SwitchOpcode /*2 cases */, 82, TARGET_VAL(ISD::SIGN_EXTEND),// ->8886
4473 /* 8816*/ OPC_SwitchOpcode /*2 cases */, 31, TARGET_VAL(ISD::SIGN_EXTEND),// ->8851
4479 /* 8828*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4494 /* 8855*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4501 /* 8867*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
4786 /* 9404*/ OPC_SwitchOpcode /*2 cases */, 13, TARGET_VAL(ISD::SIGN_EXTEND),// ->9421
4849 /* 9528*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::SIGN_EXTEND),// ->9543
5002 /* 9834*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5163 /* 10145*/ OPC_SwitchOpcode /*3 cases */, 45, TARGET_VAL(ISD::SIGN_EXTEND),// ->10194
5169 /* 10156*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5179 /* 10173*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5192 /* 10198*/ OPC_SwitchOpcode /*2 cases */, 41, TARGET_VAL(ISD::SIGN_EXTEND),// ->10243
5199 /* 10210*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5206 /* 10222*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5374 /* 10522*/ OPC_SwitchOpcode /*2 cases */, 80, TARGET_VAL(ISD::SIGN_EXTEND),// ->10606
5383 /* 10538*/ OPC_SwitchOpcode /*2 cases */, 30, TARGET_VAL(ISD::SIGN_EXTEND),// ->10572
5389 /* 10550*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5403 /* 10576*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
5410 /* 10588*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
14183 /* 26111*/ OPC_SwitchOpcode /*2 cases */, 17, TARGET_VAL(ISD::SIGN_EXTEND),// ->26132
16389 /* 30230*/ OPC_SwitchOpcode /*2 cases */, 13, TARGET_VAL(ISD::SIGN_EXTEND),// ->30247
16858 /* 31186*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
16891 /* 31246*/ OPC_SwitchOpcode /*2 cases */, 14, TARGET_VAL(ISD::SIGN_EXTEND),// ->31264
17432 /* 32319*/ OPC_SwitchOpcode /*2 cases */, 13, TARGET_VAL(ISD::SIGN_EXTEND),// ->32336
17898 /* 33233*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
17921 /* 33273*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
21173 /* 39794*/ OPC_SwitchOpcode /*2 cases */, 12, TARGET_VAL(ISD::SIGN_EXTEND),// ->39810
21388 /* 40186*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::SIGN_EXTEND),// ->40199
26126 /* 49665*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SIGN_EXTEND),// ->49702
26135 /* 49680*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc17998 /* 34554*/ /*SwitchOpcode*/ 22, TARGET_VAL(ISD::SIGN_EXTEND),// ->34579
18002 /* 34560*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
18138 /* 34801*/ /*SwitchOpcode*/ 22, TARGET_VAL(ISD::SIGN_EXTEND),// ->34826
18142 /* 34807*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
18278 /* 35048*/ /*SwitchOpcode*/ 22, TARGET_VAL(ISD::SIGN_EXTEND),// ->35073
18282 /* 35054*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
18432 /* 35319*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::SIGN_EXTEND),// ->35330
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 977 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc56597 /*119844*/ /*SwitchOpcode*/ 123|128,5/*763*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->120611
125318 /*257822*/ /*SwitchOpcode*/ 55, TARGET_VAL(ISD::SIGN_EXTEND),// ->257880
127645 /*262391*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::SIGN_EXTEND),// ->262448
146213 /*298959*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
148035 /*302488*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::SIGN_EXTEND),// ->302545
160204 /*325404*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SIGN_EXTEND),// ->325426
161858 /*328629*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SIGN_EXTEND),// ->328650
187525 /*378938*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SIGN_EXTEND),// ->378960
188264 /*380384*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SIGN_EXTEND),// ->380405
gen/lib/Target/X86/X86GenFastISel.inc 5922 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/TargetLowering.h 221 return ISD::SIGN_EXTEND;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1127 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1551 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1658 case ISD::SIGN_EXTEND:
2135 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2464 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
3092 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3984 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
3985 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
4116 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4117 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
4271 HandOpcode == ISD::SIGN_EXTEND) {
5272 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
6254 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
6258 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
6372 case ISD::SIGN_EXTEND:
6446 case ISD::SIGN_EXTEND:
7376 N0.getOpcode() == ISD::SIGN_EXTEND) &&
7628 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
7638 return DAG.getNode(ISD::SIGN_EXTEND, DL,
8247 NotCond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NotCond);
8259 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
8279 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
8654 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
8757 auto ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
8893 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
8923 FoldOpc = ISD::SIGN_EXTEND;
8960 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
9060 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
9097 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
9238 assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND ||
9381 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
9404 auto ShiftOpcode = N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
9420 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
9421 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0));
9453 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
9476 ISD::SEXTLOAD, ISD::SIGN_EXTEND))
9481 ISD::SIGN_EXTEND))
9507 ISD::SIGN_EXTEND, SetCCs, TLI);
9517 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::SIGN_EXTEND);
9967 N0.getOpcode() == ISD::SIGN_EXTEND)
10400 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
10405 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
10406 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00);
10425 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
10426 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
10560 N0.getOpcode() == ISD::SIGN_EXTEND ||
10808 if (N00.getOpcode() == ISD::SIGN_EXTEND ||
11096 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
12961 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND
13922 Val = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(LD), LDType, Val);
lib/CodeGen/SelectionDAG/FastISel.cpp 519 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
1888 return selectCast(I, ISD::SIGN_EXTEND);
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 76 ExtendKind = ISD::SIGN_EXTEND;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2491 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2768 case ISD::SIGN_EXTEND:
4243 ExtOp = ISD::SIGN_EXTEND;
4264 : ISD::SIGN_EXTEND;
4324 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4337 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 810 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1557 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1565 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1569 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 113 case ISD::SIGN_EXTEND:
421 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
559 if (N->getOpcode() == ISD::SIGN_EXTEND)
1176 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1707 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
3266 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 400 case ISD::SIGN_EXTEND:
581 ISD::SIGN_EXTEND;
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 99 case ISD::SIGN_EXTEND:
427 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
601 case ISD::SIGN_EXTEND:
924 case ISD::SIGN_EXTEND:
2022 case ISD::SIGN_EXTEND:
2838 case ISD::SIGN_EXTEND:
3286 if (Opcode == ISD::SIGN_EXTEND)
3413 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
3827 else if (N.getOpcode() == ISD::SIGN_EXTEND)
3862 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
4157 case ISD::SIGN_EXTEND:
4265 case ISD::SIGN_EXTEND:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 335 return ISD::SIGN_EXTEND;
1112 getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
3004 case ISD::SIGN_EXTEND: {
3539 case ISD::SIGN_EXTEND:
4290 case ISD::SIGN_EXTEND:
4439 case ISD::SIGN_EXTEND:
4496 case ISD::SIGN_EXTEND:
4509 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
4548 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
4579 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
4862 ScalarResult = getNode(ISD::SIGN_EXTEND, DL, LegalSVT, ScalarResult);
4964 ScalarResult = getNode(ISD::SIGN_EXTEND, DL, LegalSVT, ScalarResult);
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 248 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
260 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 1838 ExtendKind = ISD::SIGN_EXTEND;
1880 if (ExtendKind == ISD::SIGN_EXTEND)
3401 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
9204 ExtendKind = ISD::SIGN_EXTEND;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 312 case ISD::SIGN_EXTEND: return "sign_extend";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1653 case ISD::SIGN_EXTEND:
2537 case ISD::SIGN_EXTEND:
3163 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
3211 bool SExt = (N0Opc == ISD::SIGN_EXTEND);
3214 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
4081 : ISD::SIGN_EXTEND;
7207 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
lib/CodeGen/TargetLoweringBase.cpp 1477 ExtendKind = ISD::SIGN_EXTEND;
1619 case SExt: return ISD::SIGN_EXTEND;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 452 if (N.getOpcode() == ISD::SIGN_EXTEND ||
1773 assert(N->getOpcode() == ISD::SIGN_EXTEND);
2927 case ISD::SIGN_EXTEND:
lib/Target/AArch64/AArch64ISelLowering.cpp 603 setTargetDAGCombine(ISD::SIGN_EXTEND);
2135 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2523 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2675 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2699 return N->getOpcode() == ISD::SIGN_EXTEND ||
3873 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
9694 ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
10313 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
11747 case ISD::SIGN_EXTEND:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 301 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
303 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
305 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
307 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
309 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
311 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
313 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
315 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1984 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1985 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
3033 case ISD::SIGN_EXTEND:
lib/Target/AMDGPU/R600ISelLowering.cpp 1193 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
lib/Target/AMDGPU/SIISelLowering.cpp 441 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
442 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
568 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
573 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
2323 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2799 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
4200 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
7238 return DAG.getNode(ISD::SIGN_EXTEND, SL, VT, Op);
8354 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
8354 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) {
8356 if (RHS.getOpcode() != ISD::SIGN_EXTEND)
9039 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
9528 if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND ||
9536 case ISD::SIGN_EXTEND:
9543 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
9789 if (VT == MVT::i32 && LHS.getOpcode() == ISD::SIGN_EXTEND &&
lib/Target/ARC/ARCISelLowering.cpp 273 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
lib/Target/ARM/ARMISelLowering.cpp 926 setTargetDAGCombine(ISD::SIGN_EXTEND);
2143 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5411 CastOpc = ISD::SIGN_EXTEND;
8268 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
8352 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
8364 unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
8505 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
8506 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
8537 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
8538 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
8580 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
8581 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
10861 case ISD::SIGN_EXTEND: {
10991 if (!(N0.getOpcode() == ISD::SIGN_EXTEND &&
10992 N1.getOpcode() == ISD::SIGN_EXTEND) &&
11020 if (N0.getOpcode() == ISD::SIGN_EXTEND)
13569 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
13865 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
13916 case ISD::SIGN_EXTEND:
14453 case ISD::SIGN_EXTEND:
lib/Target/ARM/ARMTargetTransformInfo.cpp 177 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0},
179 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0},
181 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0},
183 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1},
185 {ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 1},
187 {ISD::SIGN_EXTEND, MVT::i64, MVT::i8, 1},
195 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0},
197 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
199 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
214 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
216 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
222 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
224 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
226 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
228 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
230 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
360 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
362 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
364 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 10 },
366 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
368 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 },
370 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 8 },
384 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
lib/Target/AVR/AVRISelLowering.cpp 1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
lib/Target/BPF/BPFISelLowering.cpp 337 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1441 case ISD::SIGN_EXTEND:
1444 EVT T = Opc == ISD::SIGN_EXTEND
1499 case ISD::SIGN_EXTEND:
lib/Target/Hexagon/HexagonISelLowering.cpp 399 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 102 setOperationAction(ISD::SIGN_EXTEND, T, Custom);
135 setOperationAction(ISD::SIGN_EXTEND, T, Custom);
754 ValV = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, ValV);
1546 case ISD::SIGN_EXTEND:
1564 case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
lib/Target/Lanai/LanaiISelLowering.cpp 667 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1382 case ISD::SIGN_EXTEND: {
lib/Target/MSP430/MSP430ISelLowering.cpp 94 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
346 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
821 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
lib/Target/Mips/MipsISelLowering.cpp 1017 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1018 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
3183 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3699 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
lib/Target/Mips/MipsISelLowering.h 316 return ISD::SIGN_EXTEND;
lib/Target/Mips/MipsSEISelLowering.cpp 2306 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2380 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
lib/Target/NVPTX/NVPTXISelLowering.cpp 1522 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
2611 unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
2699 RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND
4584 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 2511 case ISD::SIGN_EXTEND:
2532 N->getOpcode() == ISD::SIGN_EXTEND) &&
2546 N->getOpcode() == ISD::SIGN_EXTEND ?
2556 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2557 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2728 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
3563 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3635 case ISD::SIGN_EXTEND:
4232 (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) ||
5467 N->getOpcode() != ISD::SIGN_EXTEND &&
5481 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
lib/Target/PowerPC/PPCISelLowering.cpp 1128 setTargetDAGCombine(ISD::SIGN_EXTEND);
5576 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5909 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
6472 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
6846 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
6920 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
7838 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
7932 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
12083 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
12095 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
12105 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
12136 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
12148 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
12238 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
12446 (N->getOpcode() == ISD::SIGN_EXTEND &&
12467 else if (N->getOpcode() == ISD::SIGN_EXTEND)
12532 if (N->getOpcode() == ISD::SIGN_EXTEND)
12568 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
12862 if (Op.getOpcode() != ISD::SIGN_EXTEND &&
13395 case ISD::SIGN_EXTEND:
15139 N0.getOpcode() != ISD::SIGN_EXTEND ||
lib/Target/RISCV/RISCVISelLowering.h 127 return ISD::SIGN_EXTEND;
lib/Target/Sparc/SparcISelLowering.cpp 325 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
806 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1148 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 552 if (IndexOpcode == ISD::SIGN_EXTEND ||
859 case ISD::SIGN_EXTEND: {
lib/Target/SystemZ/SystemZISelLowering.cpp 608 setTargetDAGCombine(ISD::SIGN_EXTEND);
1273 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
2117 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
2774 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
3286 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
3356 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
6159 case ISD::SIGN_EXTEND: return combineSIGN_EXTEND(N, DCI);
lib/Target/X86/X86FastISel.cpp 1240 ISD::SIGN_EXTEND;
1614 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND,
2648 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::SIGN_EXTEND, InputReg,
3338 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
3373 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
lib/Target/X86/X86ISelLowering.cpp 780 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
988 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1140 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1141 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1160 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1324 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1414 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1415 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1420 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i8, Custom);
1621 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1634 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1652 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1866 setTargetDAGCombine(ISD::SIGN_EXTEND);
2508 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
3771 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
5831 case ISD::SIGN_EXTEND:
5842 assert((ISD::ANY_EXTEND == Opcode || ISD::SIGN_EXTEND == Opcode ||
9559 ExtractedIndex.getOpcode() == ISD::SIGN_EXTEND)
16957 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
16958 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
17344 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, ExtVecVT, Vec);
17533 DAG.getNode(ISD::SIGN_EXTEND, dl, ExtVecVT, Vec),
17534 DAG.getNode(ISD::SIGN_EXTEND, dl, ExtEltVT, Elt), Idx);
19122 SDValue Extend = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, In);
19334 In = DAG.getNode(ISD::SIGN_EXTEND, DL, InVT, In);
19349 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
20157 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
20166 ExtendOp = ISD::SIGN_EXTEND;
20172 ExtendOp = ISD::SIGN_EXTEND;
21637 Opc == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SIGN_EXTEND
24693 HiZ = DAG.getNode(ISD::SIGN_EXTEND, DL, CurrVT, HiZ);
24720 HiZ = DAG.getNode(ISD::SIGN_EXTEND, DL, CurrVT, HiZ);
25251 unsigned ExAVX = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
25568 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP);
25990 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
27697 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
28044 case ISD::SIGN_EXTEND:
28053 assert(N->getOpcode() == ISD::SIGN_EXTEND && "Unexpected opcode");
28058 In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, In);
28499 Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Mask);
35196 return DAG.getNode(ISD::SIGN_EXTEND, DL, SExtVT, Src);
35296 : DAG.getNode(ISD::SIGN_EXTEND, DL, SExtVT, Src);
35987 if (Root && (Root.getOpcode() == ISD::SIGN_EXTEND ||
37014 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
37519 Carry.getOpcode() == ISD::SIGN_EXTEND ||
37899 return DAG.getNode((Mode == MULU8) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND,
38280 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
38684 case ISD::SIGN_EXTEND:
38790 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
38840 case ISD::SIGN_EXTEND:
40953 if ((Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND ||
41199 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) ||
41211 unsigned Opc = ExtOpc == ISD::SIGN_EXTEND ? ISD::MULHS : ISD::MULHU;
41260 N01.getOpcode() != ISD::SIGN_EXTEND ||
41262 N11.getOpcode() != ISD::SIGN_EXTEND)
42178 N0.getOpcode() == ISD::SIGN_EXTEND)) {
42190 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
42203 if (Ext->getOpcode() != ISD::SIGN_EXTEND &&
42216 bool Sext = Ext->getOpcode() == ISD::SIGN_EXTEND;
42296 if (VT != MVT::i16 && !(ExtendOpcode == ISD::SIGN_EXTEND && VT == MVT::i32))
42302 if (TargetVT == MVT::i64 && ExtendOpcode != ISD::SIGN_EXTEND)
42325 if (Opcode != ISD::SIGN_EXTEND && Opcode != ISD::ZERO_EXTEND &&
42401 if (Opcode == ISD::SIGN_EXTEND)
42853 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
43004 if ((Index.getOpcode() == ISD::SIGN_EXTEND ||
43229 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
43962 if (N00.getOpcode() != ISD::SIGN_EXTEND ||
43963 N01.getOpcode() != ISD::SIGN_EXTEND ||
43964 N10.getOpcode() != ISD::SIGN_EXTEND ||
43965 N11.getOpcode() != ISD::SIGN_EXTEND)
44102 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op0.getOperand(0));
44110 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op1.getOperand(0));
44727 InOpcode == ISD::SIGN_EXTEND ||
44957 case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget);
45065 case ISD::SIGN_EXTEND:
45140 case ISD::SIGN_EXTEND:
45723 : ISD::SIGN_EXTEND;
lib/Target/X86/X86TargetTransformInfo.cpp 1281 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1285 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 },
1286 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 },
1287 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1288 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 },
1289 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
1290 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 },
1345 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1347 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1349 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1351 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
1353 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1355 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1408 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1410 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 },
1414 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 },
1416 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1418 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 },
1420 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1422 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1439 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
1441 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
1443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1445 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1447 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1449 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 },
1451 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1453 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1519 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1521 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1523 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1526 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
1528 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1530 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1532 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1534 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1536 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1538 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1540 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1542 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1586 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
1588 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1590 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
1592 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 },
1594 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1596 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1598 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 },
1600 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 },
1602 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 },
1604 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1606 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
1608 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
lib/Target/XCore/XCoreISelLowering.cpp 1150 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);