|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc83087 /*192795*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
83127 /*192860*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
83221 /*193025*/ /*SwitchOpcode*/ 106|128,2/*362*/, TARGET_VAL(ISD::SRA),// ->193391
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7740 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc 80 /* 61*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
91 /* 80*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
108 /* 109*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
120 /* 132*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
137 /* 162*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
148 /* 182*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
165 /* 212*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
176 /* 232*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
193 /* 262*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
204 /* 282*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
221 /* 312*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
232 /* 332*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
249 /* 362*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
260 /* 382*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
277 /* 412*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
283 /* 423*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
311 /* 493*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
323 /* 514*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
334 /* 534*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
351 /* 564*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
362 /* 584*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
379 /* 614*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
390 /* 634*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
407 /* 664*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
418 /* 684*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
435 /* 714*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
446 /* 734*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
463 /* 764*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
474 /* 784*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
506 /* 861*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
517 /* 880*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
535 /* 910*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
547 /* 933*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
564 /* 963*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
575 /* 983*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
592 /* 1013*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
603 /* 1033*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
620 /* 1063*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
631 /* 1083*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
648 /* 1113*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
659 /* 1133*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
676 /* 1163*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
687 /* 1183*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
704 /* 1213*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
710 /* 1224*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
738 /* 1294*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
750 /* 1315*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
761 /* 1335*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
778 /* 1365*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
789 /* 1385*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
806 /* 1415*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
817 /* 1435*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
834 /* 1465*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
845 /* 1485*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
862 /* 1515*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
873 /* 1535*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
890 /* 1565*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
901 /* 1585*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3141 /* 6166*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3148 /* 6179*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3176 /* 6248*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3227 /* 6354*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3234 /* 6367*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3262 /* 6436*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3345 /* 6596*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3352 /* 6609*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3380 /* 6678*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3431 /* 6784*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3438 /* 6797*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3466 /* 6866*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3501 /* 6956*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3552 /* 7062*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3559 /* 7075*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3587 /* 7144*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3670 /* 7304*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3677 /* 7317*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3705 /* 7386*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3756 /* 7492*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3763 /* 7505*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3791 /* 7574*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3903 /* 7781*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3910 /* 7794*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3938 /* 7863*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3989 /* 7969*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
3996 /* 7982*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4024 /* 8051*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4107 /* 8211*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4114 /* 8224*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4142 /* 8293*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4193 /* 8399*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4200 /* 8412*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4228 /* 8481*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4263 /* 8571*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4314 /* 8677*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4321 /* 8690*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4349 /* 8759*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4432 /* 8919*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4439 /* 8932*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4467 /* 9001*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4518 /* 9107*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4525 /* 9120*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4553 /* 9189*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6161 /* 12659*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6168 /* 12672*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6196 /* 12741*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6247 /* 12847*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6254 /* 12860*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6282 /* 12929*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6359 /* 13078*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6366 /* 13091*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6394 /* 13160*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6445 /* 13266*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6452 /* 13279*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6480 /* 13348*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6564 /* 13510*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6571 /* 13523*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6599 /* 13592*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6650 /* 13698*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6657 /* 13711*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6685 /* 13780*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6763 /* 13930*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6770 /* 13943*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6798 /* 14012*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6849 /* 14118*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6856 /* 14131*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6884 /* 14200*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6968 /* 14362*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
6975 /* 14375*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7003 /* 14444*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7054 /* 14550*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7061 /* 14563*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7089 /* 14632*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7166 /* 14781*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7173 /* 14794*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7201 /* 14863*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7252 /* 14969*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7259 /* 14982*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7287 /* 15051*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7371 /* 15213*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7378 /* 15226*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7406 /* 15295*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7457 /* 15401*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7464 /* 15414*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7492 /* 15483*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7570 /* 15633*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7577 /* 15646*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7605 /* 15715*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7656 /* 15821*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7663 /* 15834*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
7691 /* 15903*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10763 /* 22634*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10770 /* 22647*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10798 /* 22716*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10851 /* 22825*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10858 /* 22838*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10886 /* 22907*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10963 /* 23056*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10970 /* 23069*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
10998 /* 23138*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11051 /* 23247*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11058 /* 23260*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11086 /* 23329*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11170 /* 23491*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11177 /* 23504*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11205 /* 23573*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11258 /* 23682*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11265 /* 23695*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11293 /* 23764*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11371 /* 23914*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11378 /* 23927*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11406 /* 23996*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11459 /* 24105*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11466 /* 24118*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11494 /* 24187*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11578 /* 24349*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11585 /* 24362*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11613 /* 24431*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11666 /* 24540*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11673 /* 24553*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11701 /* 24622*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11778 /* 24771*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11785 /* 24784*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11813 /* 24853*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11866 /* 24962*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11873 /* 24975*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11901 /* 25044*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11985 /* 25206*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
11992 /* 25219*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12020 /* 25288*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12073 /* 25397*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12080 /* 25410*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12108 /* 25479*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12186 /* 25629*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12193 /* 25642*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12221 /* 25711*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12274 /* 25820*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12281 /* 25833*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12309 /* 25902*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12395 /* 26070*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12402 /* 26083*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12430 /* 26152*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12477 /* 26250*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12484 /* 26263*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12512 /* 26332*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12566 /* 26443*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12573 /* 26456*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12601 /* 26525*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12649 /* 26624*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12656 /* 26637*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12684 /* 26706*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12764 /* 26860*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12771 /* 26873*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12799 /* 26942*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12846 /* 27040*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12853 /* 27053*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12881 /* 27122*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12935 /* 27233*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12942 /* 27246*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
12970 /* 27315*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13018 /* 27414*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13025 /* 27427*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13053 /* 27496*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13107 /* 27607*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13114 /* 27620*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13142 /* 27689*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13189 /* 27787*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13196 /* 27800*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13224 /* 27869*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13278 /* 27980*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13285 /* 27993*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13313 /* 28062*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13361 /* 28161*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13368 /* 28174*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13396 /* 28243*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13476 /* 28397*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13483 /* 28410*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13511 /* 28479*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13558 /* 28577*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13565 /* 28590*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13593 /* 28659*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13647 /* 28770*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13654 /* 28783*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13682 /* 28852*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13730 /* 28951*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13737 /* 28964*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13765 /* 29033*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13898 /* 29351*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
13904 /* 29361*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
14018 /* 29617*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
14024 /* 29627*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
20461 /* 43489*/ OPC_SwitchOpcode /*2 cases */, 71|128,113/*14535*/, TARGET_VAL(ISD::SRA),// ->58029
20467 /* 43501*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27711 /* 58064*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27718 /* 58077*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27748 /* 58148*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27778 /* 58219*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27785 /* 58232*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27814 /* 58302*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27842 /* 58371*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27849 /* 58384*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27879 /* 58455*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27909 /* 58526*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27916 /* 58539*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
27945 /* 58609*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
47813 /*102977*/ /*SwitchOpcode*/ 70|128,1/*198*/, TARGET_VAL(ISD::SRA),// ->103179
60045 /*131365*/ /*SwitchOpcode*/ 63, TARGET_VAL(ISD::SRA),// ->131431
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 155 /* 360*/ /*SwitchOpcode*/ 99|128,2/*355*/, TARGET_VAL(ISD::SRA),// ->719
gen/lib/Target/ARC/ARCGenDAGISel.inc 755 /* 1263*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SRA),// ->1314
gen/lib/Target/ARM/ARMGenDAGISel.inc 61 /* 11*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
108 /* 101*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
169 /* 229*/ OPC_SwitchOpcode /*2 cases */, 36, TARGET_VAL(ISD::SRA),// ->269
242 /* 381*/ OPC_SwitchOpcode /*2 cases */, 36, TARGET_VAL(ISD::SRA),// ->421
310 /* 516*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
362 /* 625*/ OPC_SwitchOpcode /*2 cases */, 45, TARGET_VAL(ISD::SRA),// ->674
558 /* 1073*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::SRA),// ->1111
623 /* 1207*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::SRA),// ->1245
711 /* 1391*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4011 /* 8175*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4017 /* 8185*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4045 /* 8245*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4051 /* 8255*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4088 /* 8329*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4111 /* 8381*/ /*SwitchOpcode*/ 59, TARGET_VAL(ISD::SRA),// ->8443
4153 /* 8462*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4177 /* 8515*/ /*SwitchOpcode*/ 60, TARGET_VAL(ISD::SRA),// ->8578
4232 /* 8628*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4248 /* 8661*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4272 /* 8704*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4288 /* 8737*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4329 /* 8820*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4346 /* 8854*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4371 /* 8898*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4388 /* 8932*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
26481 /* 57176*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::SRA),// ->57215
31522 /* 69387*/ OPC_SwitchOpcode /*2 cases */, 109, TARGET_VAL(ISD::SRA),// ->69500
31528 /* 69398*/ OPC_SwitchOpcode /*2 cases */, 48, TARGET_VAL(ISD::SRA),// ->69450
31582 /* 69510*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
31611 /* 69567*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
31626 /* 69598*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
31649 /* 69639*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
31664 /* 69670*/ OPC_SwitchOpcode /*2 cases */, 31, TARGET_VAL(ISD::SRA),// ->69705
32933 /* 72491*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::SRA),// ->72765
gen/lib/Target/ARM/ARMGenFastISel.inc 5180 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/BPF/BPFGenDAGISel.inc 1580 /* 2744*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::SRA),// ->2818
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc21335 /* 40699*/ OPC_SwitchOpcode /*4 cases */, 50, TARGET_VAL(ISD::SRA),// ->40753
21456 /* 40920*/ OPC_SwitchOpcode /*4 cases */, 52, TARGET_VAL(ISD::SRA),// ->40976
21586 /* 41149*/ OPC_SwitchOpcode /*3 cases */, 31, TARGET_VAL(ISD::SRA),// ->41184
21640 /* 41256*/ OPC_SwitchOpcode /*4 cases */, 32, TARGET_VAL(ISD::SRA),// ->41292
24793 /* 47659*/ OPC_SwitchOpcode /*4 cases */, 50, TARGET_VAL(ISD::SRA),// ->47713
24914 /* 47880*/ OPC_SwitchOpcode /*4 cases */, 52, TARGET_VAL(ISD::SRA),// ->47936
25044 /* 48109*/ OPC_SwitchOpcode /*3 cases */, 31, TARGET_VAL(ISD::SRA),// ->48144
25098 /* 48215*/ OPC_SwitchOpcode /*3 cases */, 32, TARGET_VAL(ISD::SRA),// ->48251
26159 /* 50253*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::SRA),// ->50339
26736 /* 51393*/ OPC_SwitchOpcode /*4 cases */, 50, TARGET_VAL(ISD::SRA),// ->51447
26857 /* 51614*/ OPC_SwitchOpcode /*4 cases */, 52, TARGET_VAL(ISD::SRA),// ->51670
26987 /* 51843*/ OPC_SwitchOpcode /*3 cases */, 31, TARGET_VAL(ISD::SRA),// ->51878
27041 /* 51949*/ OPC_SwitchOpcode /*3 cases */, 32, TARGET_VAL(ISD::SRA),// ->51985
53875 /*101747*/ OPC_SwitchOpcode /*3 cases */, 18, TARGET_VAL(ISD::SRA),// ->101769
53911 /*101814*/ OPC_SwitchOpcode /*3 cases */, 19, TARGET_VAL(ISD::SRA),// ->101837
63867 /*122505*/ OPC_SwitchOpcode /*2 cases */, 52, TARGET_VAL(ISD::SRA),// ->122561
64215 /*123348*/ /*SwitchOpcode*/ 15|128,3/*399*/, TARGET_VAL(ISD::SRA),// ->123751
64221 /*123361*/ OPC_SwitchOpcode /*2 cases */, 58, TARGET_VAL(ISD::SRA),// ->123423
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 927 /* 1666*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::SRA),// ->1720
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4685 /* 9337*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::SRA),// ->9368
gen/lib/Target/Mips/MipsGenDAGISel.inc16226 /* 30003*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SRA),// ->30083
20694 /* 38633*/ /*SwitchOpcode*/ 118|128,7/*1014*/, TARGET_VAL(ISD::SRA),// ->39651
gen/lib/Target/Mips/MipsGenFastISel.inc 3423 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3705 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
3789 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc54219 /*116646*/ /*SwitchOpcode*/ 116, TARGET_VAL(ISD::SRA),// ->116765
gen/lib/Target/PowerPC/PPCGenDAGISel.inc27394 /* 66406*/ /*SwitchOpcode*/ 127, TARGET_VAL(ISD::SRA),// ->66536
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3251 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3383 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 6464 /* 11939*/ /*SwitchOpcode*/ 69|128,1/*197*/, TARGET_VAL(ISD::SRA),// ->12140
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2173 /* 4000*/ /*SwitchOpcode*/ 72, TARGET_VAL(ISD::SRA),// ->4075
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 4249 /* 8422*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4259 /* 8439*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4273 /* 8465*/ /*SwitchOpcode*/ 114, TARGET_VAL(ISD::SRA),// ->8582
4287 /* 8489*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4319 /* 8542*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4346 /* 8592*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4359 /* 8613*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4382 /* 8656*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4390 /* 8670*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4407 /* 8699*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4421 /* 8723*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4430 /* 8738*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4448 /* 8769*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4461 /* 8792*/ /*SwitchOpcode*/ 92|128,2/*348*/, TARGET_VAL(ISD::SRA),// ->9144
4477 /* 8824*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4492 /* 8851*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SRA),// ->8885
4531 /* 8917*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4551 /* 8957*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SRA),// ->9008
4591 /* 9029*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4605 /* 9053*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4628 /* 9093*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
4642 /* 9117*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5167 /* 10152*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5177 /* 10169*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5190 /* 10194*/ /*SwitchOpcode*/ 112, TARGET_VAL(ISD::SRA),// ->10309
5204 /* 10218*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5235 /* 10270*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5261 /* 10319*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5274 /* 10340*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5296 /* 10382*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5304 /* 10396*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5320 /* 10424*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5333 /* 10447*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5342 /* 10462*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5359 /* 10492*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5371 /* 10514*/ /*SwitchOpcode*/ 83|128,2/*339*/, TARGET_VAL(ISD::SRA),// ->10857
5387 /* 10546*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5401 /* 10572*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::SRA),// ->10605
5439 /* 10637*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5458 /* 10676*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::SRA),// ->10726
5497 /* 10746*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5510 /* 10769*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5532 /* 10808*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
5545 /* 10831*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRA),
18285 /* 34021*/ /*SwitchOpcode*/ 38|128,2/*294*/, TARGET_VAL(ISD::SRA),// ->34319
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18101 /* 34730*/ /*SwitchOpcode*/ 115|128,1/*243*/, TARGET_VAL(ISD::SRA),// ->34977
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1918 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 1183 /* 2377*/ /*SwitchOpcode*/ 30|128,5/*670*/, TARGET_VAL(ISD::SRA),// ->3051
18847 /* 37879*/ /*SwitchOpcode*/ 94|128,4/*606*/, TARGET_VAL(ISD::SRA),// ->38489
gen/lib/Target/X86/X86GenFastISel.inc13527 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14118 case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 574 /* 927*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::SRA),// ->1011
include/llvm/CodeGen/TargetLowering.h 2303 case ISD::SRA:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1261 if (Opc == ISD::SRA)
1532 case ISD::SRA: return visitSRA(N);
1654 case ISD::SRA:
2065 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2897 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2900 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
2900 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3098 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3142 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3723 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
3732 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
3969 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
4319 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
6517 Value.getOpcode() == ISD::SRA) {
7000 SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
7001 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
7176 BinOpLHSVal.getOpcode() == ISD::SRA ||
7444 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
7491 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
7557 return DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, N0C, N1C);
7578 if (N0.getOpcode() == ISD::SRA) {
7600 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue);
7679 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
7688 N0.getOperand(0).getOpcode() == ISD::SRA) &&
7700 DAG.getNode(ISD::SRA, DL, LargeVT, N0Op0.getOperand(0), Amt);
7842 if (N0.getOpcode() == ISD::SRA)
8202 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
8209 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
8715 SDValue Shift = DAG.getNode(ISD::SRA, DL, VT, LHS,
9404 auto ShiftOpcode = N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
10453 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
19956 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);
20071 TLI.isOperationLegal(ISD::SRA, VT)) {
20087 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
lib/CodeGen/SelectionDAG/FastISel.cpp 637 ISDOpcode = ISD::SRA;
1827 return selectBinaryOp(I, ISD::SRA);
1987 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1173 case ISD::SRA:
2881 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3658 case ISD::SRA:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 87 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
677 ShiftOp = ISD::SRA;
757 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
895 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
1195 case ISD::SRA:
1776 case ISD::SRA:
1886 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1888 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1891 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1893 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1897 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1905 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1952 case ISD::SRA:
1953 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1955 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1974 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2058 case ISD::SRA:
2060 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2066 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2068 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2415 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2550 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2677 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2745 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
3175 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3235 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3270 ISD::SRA, dl, NVT, Lo,
3303 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
3617 case ISD::SRA:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 379 case ISD::SRA:
736 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
946 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
959 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
1016 return DAG.getNode(ISD::SRA, DL, VT,
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 142 case ISD::SRA:
949 case ISD::SRA:
2822 case ISD::SRA:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2818 case ISD::SRA:
3556 case ISD::SRA:
4705 case ISD::SRA: return std::make_pair(C1.ashr(C2), true);
5137 case ISD::SRA:
9155 case ISD::SRA:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3165 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 691 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 240 case ISD::SRA: return "sra";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1429 case ISD::SRA: {
2501 case ISD::SRA:
2928 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
4614 Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
4728 Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
5918 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
6335 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) ||
6341 DAG.getNode(ISD::SRA, dl, VT, Op,
7074 SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo,
7191 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
7250 DAG.getNode(ISD::SRA, dl, VT, LHS,
7254 DAG.getNode(ISD::SRA, dl, VT, RHS,
7298 SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
lib/CodeGen/TargetLoweringBase.cpp 1606 case AShr: return ISD::SRA;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 367 case ISD::SRA:
1645 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1708 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1766 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1768 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1782 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1812 case ISD::SRA:
2506 case ISD::SRA:
2914 case ISD::SRA:
lib/Target/AArch64/AArch64ISelLowering.cpp 846 setOperationAction(ISD::SRA, VT, Custom);
1957 if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
2159 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
2187 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
3040 case ISD::SRA:
5604 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5639 Opc == ISD::SRA
8023 case ISD::SRA:
8028 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
8036 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
9304 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
9364 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
11440 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
11511 case ISD::SRA:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 876 case ISD::SRA:
1924 bool Signed = N->getOpcode() == ISD::SRA;
1984 case ISD::SRA:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 371 setOperationAction(ISD::SRA, VT, Expand);
491 setTargetDAGCombine(ISD::SRA);
1559 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
2104 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2212 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2213 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2417 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
3097 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3107 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3219 Src.getOpcode() == ISD::SRA ||
3951 case ISD::SRA: {
4045 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 364 case ISD::SRA:
lib/Target/AMDGPU/R600ISelLowering.cpp 850 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
854 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
855 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
lib/Target/AMDGPU/SIISelLowering.cpp 603 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
625 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
4068 case ISD::SRA:
lib/Target/ARC/ARCISelLowering.cpp 102 setOperationAction(ISD::SRA, MVT::i32, Legal);
192 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS,
lib/Target/ARM/ARMISelDAGToDAG.cpp 2750 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
2787 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
3059 case ISD::SRA:
lib/Target/ARM/ARMISelLowering.cpp 186 setOperationAction(ISD::SRA, VT, Custom);
254 setOperationAction(ISD::SRA, VT, Custom);
904 setTargetDAGCombine(ISD::SRA);
1050 setOperationAction(ISD::SRA, MVT::i64, Custom);
1771 if (Op.getOpcode() != ISD::SRA)
3639 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3661 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4418 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4906 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5800 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5818 SDValue HiBigShift = Opc == ISD::SRA
6054 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6059 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
6070 (N->getOpcode() == ISD::SRA ? ARMISD::VSHLs : ARMISD::VSHLu);
6083 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6112 } else if (ShOpc == ISD::SRA)
9181 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
9289 case ISD::SRA:
11165 if (SRA.getOpcode() != ISD::SRA) {
11168 if (SRA.getOpcode() != ISD::SRA)
13813 case ISD::SRA:
13817 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
14450 case ISD::SRA:
16193 Tmp = DAG.getNode(ISD::SRA, dl, HalfT, Hi,
lib/Target/ARM/ARMSelectionDAGInfo.h 28 case ISD::SRA: return ARM_AM::asr;
lib/Target/AVR/AVRISelLowering.cpp 81 setOperationAction(ISD::SRA, MVT::i8, Custom);
84 setOperationAction(ISD::SRA, MVT::i16, Custom);
303 case ISD::SRA:
313 case ISD::SRA:
688 case ISD::SRA:
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1467 case ISD::SRA: {
lib/Target/Hexagon/HexagonISelLowering.cpp 1462 setOperationAction(ISD::SRA, VT, Custom);
2046 case ISD::SRA:
2858 case ISD::SRA:
2906 case ISD::SRA:
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 107 setOperationAction(ISD::SRA, T, Custom);
159 setOperationAction(ISD::SRA, T, Custom);
1541 case ISD::SRA:
1567 case ISD::SRA:
lib/Target/Lanai/LanaiAluCode.h 138 case ISD::SRA:
lib/Target/MSP430/MSP430ISelLowering.cpp 71 setOperationAction(ISD::SRA, MVT::i8, Custom);
74 setOperationAction(ISD::SRA, MVT::i16, Custom);
339 case ISD::SRA: return LowerShifts(Op, DAG);
969 case ISD::SRA:
973 Victim = (Opc == ISD::SRA)
1191 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
lib/Target/Mips/MipsISelLowering.cpp 804 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
2510 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2514 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
3366 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3420 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
lib/Target/Mips/MipsSEISelLowering.cpp 102 setTargetDAGCombine(ISD::SRA);
165 setTargetDAGCombine(ISD::SRA);
341 setOperationAction(ISD::SRA, Ty, Legal);
1041 case ISD::SRA:
2206 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2212 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 487 case ISD::SRA:
3411 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
3441 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
3537 if (N->getOpcode() == ISD::SRA) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 1972 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
lib/Target/PowerPC/PPCISelLowering.cpp 802 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
811 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
817 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
879 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1111 setTargetDAGCombine(ISD::SRA);
7799 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
12574 ISD::SRA, dl, N->getValueType(0),
13374 case ISD::SRA:
15118 case ISD::SRA:
lib/Target/RISCV/RISCVISelLowering.cpp 106 setOperationAction(ISD::SRA, MVT::i32, Custom);
784 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
801 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero;
820 case ISD::SRA:
890 case ISD::SRA:
lib/Target/Sparc/SparcISelLowering.cpp 2950 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2951 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2964 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 904 case ISD::SRA: {
914 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
1855 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA;
1874 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result,
lib/Target/SystemZ/SystemZISelLowering.cpp 365 setOperationAction(ISD::SRA, VT, Custom);
3311 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
3312 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
5036 case ISD::SRA:
5463 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
5477 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
6002 if (CompareLHS->getOpcode() == ISD::SRA) {
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp 174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL,
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 146 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) {
1015 case ISD::SRA:
1537 case ISD::SRA:
lib/Target/X86/X86ISelDAGToDAG.cpp 691 case ISD::SRA:
829 case ISD::SRA:
840 case ISD::SRA: NewOpc = X86ISD::VSRAV; break;
3470 if (N0->getOpcode() != ISD::SRL && N0->getOpcode() != ISD::SRA)
4472 case ISD::SRA:
lib/Target/X86/X86ISelLowering.cpp 1002 setOperationAction(ISD::SRA, VT, Custom);
1136 setOperationAction(ISD::SRA, VT, Custom);
1457 setOperationAction(ISD::SRA, VT, Custom);
1673 setOperationAction(ISD::SRA, VT, Custom);
1847 setTargetDAGCombine(ISD::SRA);
9207 case ISD::SRA:
18243 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
18253 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
20350 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i64));
20769 Result = DAG.getNode(ISD::SRA, dl, VT, Result,
22425 case ISD::SRA:
25455 return (Opcode == ISD::SRA) ? AShift : LShift;
25483 return (Opcode == ISD::SRA) ? AShift : LShift;
25550 Op.getOpcode() == ISD::SRA)
25563 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
25595 if (Op.getOpcode() == ISD::SRA) {
25662 if (Opcode == ISD::SRA) {
25790 if (Opc == ISD::SRL || Opc == ISD::SRA) {
25796 if (Opc == ISD::SRA)
25802 if (VT == MVT::v2i64 && Opc != ISD::SRA) {
25815 Opc == ISD::SRA) {
25901 if (Opc == ISD::SRA && ConstantAmt &&
25990 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
25999 if (ConstantAmt && (Opc == ISD::SRA || Opc == ISD::SRL) &&
26016 R = Opc == ISD::SRA ? DAG.getSExtOrTrunc(R, dl, ExVT)
26107 if (Opc == ISD::SRA) {
27751 case ISD::SRA:
27910 ISD::SRA, dl, HalfT, Hi,
38358 return DAG.getNode(ISD::SRA, DL, VT, NN,
39848 if (Shift.getOpcode() != ISD::SRA || !Shift.hasOneUse() ||
44922 case ISD::SRA: return combineShiftRightArithmetic(N, DAG);
45069 case ISD::SRA:
45145 case ISD::SRA:
lib/Target/X86/X86TargetTransformInfo.cpp 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
303 { ISD::SRA, MVT::v2i64, 1 },
304 { ISD::SRA, MVT::v4i64, 1 },
305 { ISD::SRA, MVT::v8i64, 1 },
318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
452 { ISD::SRA, MVT::v16i16, 1 }, // psraw.
473 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
474 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw
503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw
507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw
511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence.
526 { ISD::SRA, MVT::v16i32, 1 },
531 { ISD::SRA, MVT::v2i64, 1 },
532 { ISD::SRA, MVT::v4i64, 1 },
533 { ISD::SRA, MVT::v8i64, 1 },
560 { ISD::SRA, MVT::v4i32, 1 },
563 { ISD::SRA, MVT::v8i32, 1 },
589 { ISD::SRA, MVT::v16i8, 2 },
592 { ISD::SRA, MVT::v8i16, 2 },
595 { ISD::SRA, MVT::v4i32, 2 },
598 { ISD::SRA, MVT::v2i64, 2 },
602 { ISD::SRA, MVT::v32i8, 4+2 },
605 { ISD::SRA, MVT::v16i16, 4+2 },
608 { ISD::SRA, MVT::v8i32, 4+2 },
611 { ISD::SRA, MVT::v4i64, 4+2 },
619 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&
638 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split.
639 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split.
640 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle.
641 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split.
649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
674 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence.
675 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
676 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence.
677 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
791 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence.
792 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split.
793 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence.
794 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
795 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend.
796 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split.
820 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.
821 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.
822 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
823 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence.
824 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split.