|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99014 /*223115*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::UDIV),// ->223142
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7743 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenDAGISel.inc38308 /* 84403*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::UDIV),// ->84450
gen/lib/Target/ARM/ARMGenFastISel.inc 5185 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/BPF/BPFGenDAGISel.inc 1658 /* 2886*/ /*SwitchOpcode*/ 65, TARGET_VAL(ISD::UDIV),// ->2954
gen/lib/Target/Mips/MipsGenDAGISel.inc16344 /* 30286*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::UDIV),// ->30322
26501 /* 50172*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::UDIV),// ->50265
gen/lib/Target/Mips/MipsGenFastISel.inc 3428 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58085 /*123456*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::UDIV),// ->123540
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28496 /* 68489*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::UDIV),// ->68516
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3255 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12227 /* 22756*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::UDIV),// ->22801
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2481 /* 4555*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::UDIV),// ->4597
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16800 /* 32571*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::UDIV),// ->32598
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1923 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2122 /* 3703*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::UDIV),// ->3716
include/llvm/CodeGen/TargetLowering.h 2305 case ISD::UDIV:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1515 case ISD::UDIV: return visitUDIV(N);
3531 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3536 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3568 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3584 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3659 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
3784 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
3931 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
5933 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
19602 if (Opcode != ISD::UDIV && Opcode != ISD::SDIV &&
lib/CodeGen/SelectionDAG/FastISel.cpp 1813 return selectBinaryOp(I, ISD::UDIV);
1979 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3200 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3217 case ISD::UDIV:
4069 case ISD::UDIV:
4225 case ISD::UDIV:
4245 case ISD::UDIV:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 136 case ISD::UDIV:
1711 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 365 case ISD::UDIV:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 138 case ISD::UDIV:
942 case ISD::UDIV:
2762 case ISD::UDIV:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2736 case ISD::UDIV: {
4716 case ISD::UDIV:
4772 case ISD::UDIV:
5100 case ISD::UDIV:
5378 case ISD::UDIV:
5400 case ISD::UDIV:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 683 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 229 case ISD::UDIV: return "udiv";
lib/CodeGen/TargetLoweringBase.cpp 812 case ISD::UDIV:
1598 case UDiv: return ISD::UDIV;
lib/Target/AArch64/AArch64ISelLowering.cpp 863 setOperationAction(ISD::UDIV, VT, Expand);
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 523 case ISD::UDIV:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 309 setOperationAction(ISD::UDIV, VT, Expand);
379 setOperationAction(ISD::UDIV, VT, Expand);
1801 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
lib/Target/AMDGPU/SIISelLowering.cpp 448 setOperationAction(ISD::UDIV, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 202 setOperationAction(ISD::UDIV, VT, Expand);
274 setOperationAction(ISD::UDIV, VT, Expand);
841 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
842 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
1098 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1103 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1106 setOperationAction(ISD::UDIV, MVT::i64, Custom);
9205 case ISD::UDIV:
9311 case ISD::UDIV:
15979 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
lib/Target/ARM/ARMTargetTransformInfo.cpp 659 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
663 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
667 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
671 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
676 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
680 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
684 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
688 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
916 case ISD::UDIV:
lib/Target/AVR/AVRISelLowering.cpp 144 setOperationAction(ISD::UDIV, MVT::i8, Expand);
145 setOperationAction(ISD::UDIV, MVT::i16, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1374 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1420 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
lib/Target/Lanai/LanaiISelLowering.cpp 107 setOperationAction(ISD::UDIV, MVT::i32, Expand);
lib/Target/Lanai/LanaiTargetTransformInfo.h 93 case ISD::UDIV:
lib/Target/MSP430/MSP430ISelLowering.cpp 128 setOperationAction(ISD::UDIV, MVT::i8, Promote);
134 setOperationAction(ISD::UDIV, MVT::i16, LibCall);
lib/Target/Mips/MipsFastISel.cpp 1935 case ISD::UDIV:
2050 if (!selectBinaryOp(I, ISD::UDIV))
2051 return selectDivRem(I, ISD::UDIV);
lib/Target/Mips/MipsISelLowering.cpp 395 setOperationAction(ISD::UDIV, MVT::i32, Expand);
399 setOperationAction(ISD::UDIV, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 240 setOperationAction(ISD::UDIV, MVT::i32, Legal);
287 setOperationAction(ISD::UDIV, MVT::i64, Legal);
346 setOperationAction(ISD::UDIV, Ty, Legal);
1816 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 4552 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
lib/Target/PowerPC/PPCISelLowering.cpp 627 setOperationAction(ISD::UDIV, VT, Expand);
9545 (Op.getOpcode() == ISD::UREM && UI->getOpcode() == ISD::UDIV))
lib/Target/RISCV/RISCVISelLowering.cpp 115 setOperationAction(ISD::UDIV, XLenVT, Expand);
123 setOperationAction(ISD::UDIV, MVT::i32, Custom);
826 case ISD::UDIV:
899 case ISD::UDIV:
lib/Target/Sparc/SparcISelDAGToDAG.cpp 342 case ISD::UDIV: {
lib/Target/Sparc/SparcISelLowering.cpp 1661 setOperationAction(ISD::UDIV, MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 160 setOperationAction(ISD::UDIV, VT, Expand);
618 setTargetDAGCombine(ISD::UDIV);
6175 case ISD::UDIV:
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 175 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
lib/Target/X86/X86ISelLowering.cpp 313 setOperationAction(ISD::UDIV, VT, Expand);
748 setOperationAction(ISD::UDIV, VT, Expand);
850 setOperationAction(ISD::UDIV, VT, Custom);
1817 setOperationAction(ISD::UDIV, MVT::i128, Custom);
25394 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
27938 case ISD::UDIV:
lib/Target/X86/X86TargetTransformInfo.cpp 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
278 if (ISD == ISD::UDIV)
351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence
370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence
389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split.
411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split.
427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
877 ISD == ISD::UDIV || ISD == ISD::UREM)) {