|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineInstrBuilder.h 499 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
lib/CodeGen/InlineSpiller.cpp 946 .addReg(NewVReg, getKillRegState(isKill));
lib/CodeGen/MachineInstrBundle.cpp 224 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
lib/CodeGen/PrologEpilogInserter.cpp 549 .addReg(Reg, getKillRegState(true));
576 .addReg(CI.getDstReg(), getKillRegState(true));
lib/CodeGen/SelectionDAG/FastISel.cpp 2056 .addReg(Op0, getKillRegState(Op0IsKill));
2059 .addReg(Op0, getKillRegState(Op0IsKill));
2079 .addReg(Op0, getKillRegState(Op0IsKill))
2080 .addReg(Op1, getKillRegState(Op1IsKill));
2083 .addReg(Op0, getKillRegState(Op0IsKill))
2084 .addReg(Op1, getKillRegState(Op1IsKill));
2105 .addReg(Op0, getKillRegState(Op0IsKill))
2106 .addReg(Op1, getKillRegState(Op1IsKill))
2107 .addReg(Op2, getKillRegState(Op2IsKill));
2110 .addReg(Op0, getKillRegState(Op0IsKill))
2111 .addReg(Op1, getKillRegState(Op1IsKill))
2112 .addReg(Op2, getKillRegState(Op2IsKill));
2129 .addReg(Op0, getKillRegState(Op0IsKill))
2133 .addReg(Op0, getKillRegState(Op0IsKill))
2152 .addReg(Op0, getKillRegState(Op0IsKill))
2157 .addReg(Op0, getKillRegState(Op0IsKill))
2197 .addReg(Op0, getKillRegState(Op0IsKill))
2198 .addReg(Op1, getKillRegState(Op1IsKill))
2202 .addReg(Op0, getKillRegState(Op0IsKill))
2203 .addReg(Op1, getKillRegState(Op1IsKill))
2235 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
lib/CodeGen/TargetInstrInfo.cpp 839 .addReg(RegX, getKillRegState(KillX))
840 .addReg(RegY, getKillRegState(KillY));
843 .addReg(RegA, getKillRegState(KillA))
844 .addReg(NewVR, getKillRegState(true));
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 278 .addReg(Src, getKillRegState(IsKill));
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 206 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
223 .addReg(StatusReg, getKillRegState(StatusDead))
287 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
295 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
303 .addUse(StatusReg, getKillRegState(StatusDead))
316 .addReg(StatusReg, getKillRegState(StatusDead))
lib/Target/AArch64/AArch64FastISel.cpp 393 ResultReg).addReg(ZeroReg, getKillRegState(true));
430 .addReg(TmpReg, getKillRegState(true));
1347 .addReg(LHSReg, getKillRegState(LHSIsKill))
1348 .addReg(RHSReg, getKillRegState(RHSIsKill));
1391 .addReg(LHSReg, getKillRegState(LHSIsKill))
1434 .addReg(LHSReg, getKillRegState(LHSIsKill))
1435 .addReg(RHSReg, getKillRegState(RHSIsKill))
1479 .addReg(LHSReg, getKillRegState(LHSIsKill))
1480 .addReg(RHSReg, getKillRegState(RHSIsKill))
1538 .addReg(LHSReg, getKillRegState(LHSIsKill));
1549 .addReg(LHSReg, getKillRegState(LHSIsKill))
1550 .addReg(RHSReg, getKillRegState(RHSIsKill));
1915 .addReg(ResultReg, getKillRegState(true))
2411 .addReg(SrcReg, getKillRegState(SrcIsKill));
2542 .addReg(ConstrainedCondReg, getKillRegState(CondRegIsKill))
2585 .addReg(AArch64::WZR, getKillRegState(true));
2625 .addReg(AArch64::WZR, getKillRegState(true))
2626 .addReg(AArch64::WZR, getKillRegState(true))
2630 .addReg(TmpReg1, getKillRegState(true))
2631 .addReg(AArch64::WZR, getKillRegState(true))
2644 .addReg(AArch64::WZR, getKillRegState(true))
2645 .addReg(AArch64::WZR, getKillRegState(true))
2815 .addReg(CondReg, getKillRegState(CondIsKill))
3056 .addReg(DstReg, getKillRegState(true));
3641 .addReg(SrcReg, getKillRegState(SrcRegIsKill));
3999 .addReg(SrcReg, getKillRegState(SrcIsKill));
4129 .addReg(Op0, getKillRegState(Op0IsKill));
4177 .addReg(Op0, getKillRegState(Op0IsKill))
4236 .addReg(Op0, getKillRegState(Op0IsKill));
4298 .addReg(Op0, getKillRegState(Op0IsKill))
4357 .addReg(Op0, getKillRegState(Op0IsKill));
4407 .addReg(Op0, getKillRegState(Op0IsKill))
4563 .addReg(Reg, getKillRegState(true))
4607 .addReg(SrcReg, getKillRegState(SrcIsKill))
lib/Target/AArch64/AArch64FrameLowering.cpp 1764 return getKillRegState(!IsLiveIn);
2380 .addReg(DstReg, getKillRegState(true))
lib/Target/AArch64/AArch64InstrInfo.cpp 2433 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
2457 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
2486 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
2489 .addReg(SrcReg, getKillRegState(KillSrc))
2511 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
2516 .addReg(SrcReg, getKillRegState(KillSrc));
2529 .addReg(SrcReg, getKillRegState(KillSrc));
2539 .addReg(SrcReg, getKillRegState(KillSrc));
2548 .addReg(SrcReg, getKillRegState(KillSrc))
2559 .addReg(SrcReg, getKillRegState(KillSrc));
2643 .addReg(SrcReg, getKillRegState(KillSrc));
2647 .addReg(SrcReg, getKillRegState(KillSrc))
2668 .addReg(SrcReg, getKillRegState(KillSrc));
2671 .addReg(SrcReg, getKillRegState(KillSrc));
2685 .addReg(SrcReg, getKillRegState(KillSrc));
2688 .addReg(SrcReg, getKillRegState(KillSrc));
2702 .addReg(SrcReg, getKillRegState(KillSrc));
2709 .addReg(SrcReg, getKillRegState(KillSrc));
2723 .addReg(SrcReg, getKillRegState(KillSrc));
2730 .addReg(SrcReg, getKillRegState(KillSrc));
2739 .addReg(SrcReg, getKillRegState(KillSrc));
2745 .addReg(SrcReg, getKillRegState(KillSrc));
2752 .addReg(SrcReg, getKillRegState(KillSrc));
2758 .addReg(SrcReg, getKillRegState(KillSrc));
2766 .addReg(SrcReg, getKillRegState(KillSrc))
2775 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
2798 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0)
2799 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1)
2903 .addReg(SrcReg, getKillRegState(isKill))
4022 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4023 .addReg(SrcReg1, getKillRegState(Src1IsKill))
4024 .addReg(SrcReg2, getKillRegState(Src2IsKill));
4027 .addReg(SrcReg2, getKillRegState(Src2IsKill))
4028 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4029 .addReg(SrcReg1, getKillRegState(Src1IsKill))
4033 .addReg(SrcReg2, getKillRegState(Src2IsKill))
4034 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4035 .addReg(SrcReg1, getKillRegState(Src1IsKill));
4087 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4088 .addReg(SrcReg1, getKillRegState(Src1IsKill))
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill());
433 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill());
439 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill());
639 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill());
lib/Target/AMDGPU/SIInstrInfo.cpp 521 .addReg(SrcReg, getKillRegState(KillSrc));
537 .addReg(SrcReg, getKillRegState(KillSrc));
553 .addReg(SrcReg, getKillRegState(KillSrc));
559 .addReg(SrcReg, getKillRegState(KillSrc));
571 .addReg(SrcReg, getKillRegState(KillSrc));
579 .addReg(SrcReg, getKillRegState(KillSrc));
585 .addReg(SrcReg, getKillRegState(KillSrc));
597 .addReg(SrcReg, getKillRegState(KillSrc));
604 .addReg(SrcReg, getKillRegState(KillSrc))
677 .addReg(SrcReg, getKillRegState(KillSrc));
729 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
1078 .addReg(SrcReg, getKillRegState(isKill)) // data
1101 MIB.addReg(SrcReg, getKillRegState(isKill)) // data
lib/Target/AMDGPU/SIRegisterInfo.cpp 569 .addReg(Src, getKillRegState(IsKill));
694 SOffsetRegState |= getKillRegState(Scavenged);
696 SrcDstRegState |= getKillRegState(IsKill);
706 .addReg(SubReg, getKillRegState(IsKill));
716 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill))
787 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
807 .addReg(SubReg, getKillRegState(IsKill))
833 SuperKillState |= getKillRegState(IsKill);
lib/Target/ARC/ARCInstrInfo.cpp 290 .addReg(SrcReg, getKillRegState(KillSrc));
316 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/ARC/ARCRegisterInfo.cpp 107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
lib/Target/ARM/ARMBaseInstrInfo.cpp 785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
803 MIB.addReg(SrcReg, getKillRegState(KillSrc))
839 .addReg(SrcReg, getKillRegState(KillSrc))
862 MIB.addReg(SrcReg, getKillRegState(KillSrc));
864 MIB.addReg(SrcReg, getKillRegState(KillSrc));
932 .addReg(SrcReg, getKillRegState(KillSrc))
938 .addReg(SrcReg, getKillRegState(KillSrc))
944 .addReg(SrcReg, getKillRegState(KillSrc))
950 .addReg(SrcReg, getKillRegState(KillSrc))
1044 .addReg(SrcReg, getKillRegState(isKill))
1055 .addReg(SrcReg, getKillRegState(isKill))
1062 .addReg(SrcReg, getKillRegState(isKill))
1069 .addReg(SrcReg, getKillRegState(isKill))
1080 .addReg(SrcReg, getKillRegState(isKill))
1088 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1099 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1112 .addReg(SrcReg, getKillRegState(isKill))
1117 .addReg(SrcReg, getKillRegState(isKill))
1125 MIB.addReg(SrcReg, getKillRegState(isKill))
1141 .addReg(SrcReg, getKillRegState(isKill))
1150 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1166 .addReg(SrcReg, getKillRegState(isKill))
1175 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1189 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
3320 .addReg(Reg1, getKillRegState(isKill))
lib/Target/ARM/ARMConstantIslandPass.cpp 1974 .addReg(Reg, getKillRegState(RegKilled))
2298 getKillRegState(BaseRegKill))
2299 .addReg(IdxReg, getKillRegState(IdxRegKill))
lib/Target/ARM/ARMExpandPseudoInsts.cpp 715 getKillRegState(MO.isKill()));
777 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
976 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
1091 .addReg(DestLo, getKillRegState(Dest.isDead()))
1096 .addReg(DestHi, getKillRegState(Dest.isDead()))
1114 unsigned Flags = getKillRegState(New.isDead());
lib/Target/ARM/ARMFastISel.cpp 3066 ResultReg).addReg(DstReg, getKillRegState(true));
lib/Target/ARM/ARMFrameLowering.cpp 1029 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1032 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 737 .addReg(Base, getKillRegState(KillOldBase));
740 .addReg(Base, getKillRegState(KillOldBase))
750 .addReg(Base, getKillRegState(KillOldBase))
756 .addReg(Base, getKillRegState(KillOldBase))
761 .addReg(Base, getKillRegState(KillOldBase))
803 .addReg(Base, getKillRegState(BaseKill));
812 MIB.addReg(Base, getKillRegState(BaseKill));
818 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
842 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
843 .addReg(Regs[1].first, getKillRegState(Regs[1].second));
1319 .addReg(Base, getKillRegState(BaseKill))
1443 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1446 getKillRegState(MO.isKill())))
1484 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1493 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1631 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1639 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1640 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1699 .addReg(BaseReg, getKillRegState(BaseKill))
1707 .addReg(BaseReg, getKillRegState(BaseKill))
1710 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
1712 getKillRegState(OddDeadKill) | getUndefRegState(OddUndef))
lib/Target/ARM/MLxExpansionPass.cpp 291 .addReg(Src1Reg, getKillRegState(Src1Kill))
292 .addReg(Src2Reg, getKillRegState(Src2Kill));
302 MIB.addReg(TmpReg, getKillRegState(true))
303 .addReg(AccReg, getKillRegState(AccKill));
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
lib/Target/ARM/Thumb1FrameLowering.cpp 859 MIB.addReg(Reg, getKillRegState(isKill));
906 .addReg(*HiRegToSave, getKillRegState(isKill))
lib/Target/ARM/Thumb1InstrInfo.cpp 52 .addReg(SrcReg, getKillRegState(KillSrc))
62 .addReg(SrcReg, getKillRegState(KillSrc))
70 .addReg(SrcReg, getKillRegState(KillSrc));
97 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/ARM/Thumb2InstrInfo.cpp 130 .addReg(SrcReg, getKillRegState(KillSrc))
150 .addReg(SrcReg, getKillRegState(isKill))
168 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
lib/Target/ARM/Thumb2SizeReduction.cpp 599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
lib/Target/AVR/AVRExpandPseudoInsts.cpp 154 .addReg(DstLoReg, getKillRegState(DstIsKill))
155 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
159 .addReg(DstHiReg, getKillRegState(DstIsKill))
160 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
187 .addReg(DstLoReg, getKillRegState(DstIsKill))
188 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
195 .addReg(DstHiReg, getKillRegState(DstIsKill))
196 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
235 .addReg(DstLoReg, getKillRegState(SrcIsKill))
245 .addReg(DstHiReg, getKillRegState(SrcIsKill))
283 .addReg(DstLoReg, getKillRegState(SrcIsKill));
287 .addReg(DstHiReg, getKillRegState(SrcIsKill));
340 .addReg(DstLoReg, getKillRegState(SrcIsKill))
348 .addReg(DstHiReg, getKillRegState(SrcIsKill))
400 .addReg(DstLoReg, getKillRegState(DstIsKill));
407 .addReg(DstHiReg, getKillRegState(DstIsKill));
432 .addReg(DstLoReg, getKillRegState(DstIsKill))
433 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
436 .addReg(DstHiReg, getKillRegState(DstIsKill))
437 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
464 .addReg(DstLoReg, getKillRegState(DstIsKill))
465 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
471 .addReg(DstHiReg, getKillRegState(DstIsKill))
472 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
608 .addReg(SrcReg, getKillRegState(SrcIsKill))
725 .addReg(SrcReg, getKillRegState(SrcIsKill))
774 .addReg(SrcReg, getKillRegState(SrcIsKill));
1002 MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
1003 MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
1026 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1031 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1058 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1064 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1092 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1098 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1128 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1131 .addReg(DstReg, getKillRegState(DstIsKill))
1133 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1190 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1194 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1216 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1221 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1261 .addReg(DstLoReg, getKillRegState(DstIsKill));
1266 .addReg(DstHiReg, getKillRegState(DstIsKill));
1293 .addReg(DstHiReg, getKillRegState(DstIsKill));
1297 .addReg(DstLoReg, getKillRegState(DstIsKill));
1336 .addReg(DstHiReg, getKillRegState(DstIsKill));
1340 .addReg(DstLoReg, getKillRegState(DstIsKill));
1388 .addReg(SrcReg, getKillRegState(SrcIsKill));
1432 .addReg(SrcReg, getKillRegState(SrcIsKill));
1492 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1502 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
lib/Target/AVR/AVRFrameLowering.cpp 266 .addReg(Reg, getKillRegState(IsNotLiveIn))
335 getKillRegState(SrcIsKill));
338 getKillRegState(SrcIsKill));
341 .addReg(SrcReg, getKillRegState(SrcIsKill));
lib/Target/AVR/AVRInstrInfo.cpp 53 .addReg(SrcReg, getKillRegState(KillSrc));
62 .addReg(SrcLo, getKillRegState(KillSrc));
64 .addReg(SrcHi, getKillRegState(KillSrc));
78 .addReg(SrcReg, getKillRegState(KillSrc));
155 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/AVR/AVRRelaxMemOperations.cpp 112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill()));
lib/Target/BPF/BPFInstrInfo.cpp 37 .addReg(SrcReg, getKillRegState(KillSrc));
40 .addReg(SrcReg, getKillRegState(KillSrc));
135 .addReg(SrcReg, getKillRegState(IsKill))
140 .addReg(SrcReg, getKillRegState(IsKill))
lib/Target/Hexagon/HexagonCopyToCombine.cpp 762 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
809 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
858 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
859 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
lib/Target/Hexagon/HexagonFrameLowering.cpp 1608 .addReg(SrcR, getKillRegState(IsKill));
1677 .addReg(SrcR, getKillRegState(IsKill))
1766 .addReg(SrcLo, getKillRegState(IsKill))
1777 .addReg(SrcHi, getKillRegState(IsKill))
1848 .addReg(SrcR, getKillRegState(IsKill))
2315 .addReg(FoundR, getKillRegState(&MI == &EI));
lib/Target/Hexagon/HexagonInstrInfo.cpp 792 unsigned KillFlag = getKillRegState(KillSrc);
892 unsigned KillFlag = getKillRegState(isKill);
1064 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1237 unsigned K1 = getKillRegState(Op1.isKill());
1238 unsigned K2 = getKillRegState(Op2.isKill());
1239 unsigned K3 = getKillRegState(Op3.isKill());
lib/Target/Hexagon/HexagonNewValueJump.cpp 693 .addReg(cmpReg1, getKillRegState(MO1IsKill))
694 .addReg(cmpOp2, getKillRegState(MO2IsKill))
699 .addReg(cmpReg1, getKillRegState(MO1IsKill))
lib/Target/Hexagon/HexagonStoreWidening.cpp 435 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
458 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
lib/Target/Lanai/LanaiInstrInfo.cpp 45 .addReg(SourceRegister, getKillRegState(KillSource))
63 .addReg(SourceRegister, getKillRegState(IsKill))
lib/Target/Lanai/LanaiMemAluCombiner.cpp 261 InstrBuilder.addReg(Base.getReg(), getKillRegState(true));
lib/Target/MSP430/MSP430InstrInfo.cpp 54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
103 .addReg(SrcReg, getKillRegState(KillSrc));
lib/Target/Mips/Mips16InstrInfo.cpp 96 MIB.addReg(SrcReg, getKillRegState(KillSrc));
123 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
lib/Target/Mips/MipsFastISel.cpp 1475 .addReg(DstReg, getKillRegState(true));
2141 .addReg(Op0, getKillRegState(Op0IsKill))
2142 .addReg(Op1, getKillRegState(Op1IsKill))
lib/Target/Mips/MipsISelLowering.cpp 1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
lib/Target/Mips/MipsSEFrameLowering.cpp 193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
lib/Target/Mips/MipsSEInstrInfo.cpp 112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
139 .addReg(SrcReg, getKillRegState(KillSrc));
180 MIB.addReg(SrcReg, getKillRegState(KillSrc));
319 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
744 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
745 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
755 unsigned KillSrc = getKillRegState(Src.isKill());
lib/Target/NVPTX/NVPTXInstrInfo.cpp 69 .addReg(SrcReg, getKillRegState(KillSrc));
lib/Target/PowerPC/PPCFrameLowering.cpp 982 .addReg(TempReg, getKillRegState(true))
1028 .addReg(ScratchReg, getKillRegState(true))
1036 .addReg(TempReg, getKillRegState(true))
1118 .addReg(TOCReg, getKillRegState(true))
1611 .addReg(TempReg, getKillRegState(i == e-1));
1689 .addReg(TempReg, getKillRegState(i == e-1));
2251 getKillRegState(true)),
2258 .addReg(Reg, getKillRegState(true));
2297 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2301 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2305 .addReg(MoveReg, getKillRegState(true)));
2415 .addReg(CSI[i].getDstReg(), getKillRegState(true));
lib/Target/PowerPC/PPCInstrInfo.cpp 429 .addReg(Reg2, getKillRegState(Reg2IsKill))
430 .addReg(Reg1, getKillRegState(Reg1IsKill))
936 getKillRegState(KillSrc);
948 getKillRegState(KillSrc);
953 getKillRegState(KillSrc);
961 getKillRegState(KillSrc);
968 getKillRegState(KillSrc);
973 getKillRegState(KillSrc);
978 getKillRegState(KillSrc);
1022 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1024 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1210 BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
lib/Target/PowerPC/PPCRegisterInfo.cpp 568 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
576 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
593 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
601 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
663 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
789 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
876 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
lib/Target/RISCV/RISCVISelLowering.cpp 1201 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
1206 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
lib/Target/RISCV/RISCVInstrInfo.cpp 91 .addReg(SrcReg, getKillRegState(KillSrc))
106 .addReg(SrcReg, getKillRegState(KillSrc))
107 .addReg(SrcReg, getKillRegState(KillSrc));
132 .addReg(SrcReg, getKillRegState(IsKill))
lib/Target/Sparc/SparcInstrInfo.cpp 323 .addReg(SrcReg, getKillRegState(KillSrc));
331 .addReg(SrcReg, getKillRegState(KillSrc));
335 .addReg(SrcReg, getKillRegState(KillSrc));
346 .addReg(SrcReg, getKillRegState(KillSrc));
363 .addReg(SrcReg, getKillRegState(KillSrc));
367 .addReg(SrcReg, getKillRegState(KillSrc));
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
423 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
428 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
lib/Target/SystemZ/SystemZFrameLowering.cpp 124 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
lib/Target/SystemZ/SystemZInstrInfo.cpp 79 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
263 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
781 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
802 .addReg(SrcRegHi, getKillRegState(KillSrc))
803 .addReg(SrcRegLo, getKillRegState(KillSrc));
818 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
834 .addReg(SrcReg, getKillRegState(KillSrc))
868 .addReg(SrcReg, getKillRegState(KillSrc));
882 .addReg(SrcReg, getKillRegState(isKill)),
977 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
lib/Target/X86/X86FastISel.cpp 503 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
649 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill));
2112 .addReg(KCondReg, getKillRegState(CondIsKill));
2117 .addReg(CondReg, getKillRegState(CondIsKill))
2330 .addReg(KCondReg, getKillRegState(CondIsKill));
2335 .addReg(CondReg, getKillRegState(CondIsKill))
2383 .addReg(OpReg, getKillRegState(OpIsKill));
2925 .addReg(LHSReg, getKillRegState(LHSIsKill));
2952 .addReg(LHSReg, getKillRegState(LHSIsKill));
2963 .addReg(LHSReg, getKillRegState(LHSIsKill));
3148 .addReg(DstReg, getKillRegState(true));
3990 .addReg(Op0, getKillRegState(Op0IsKill))
3991 .addReg(Op1, getKillRegState(Op1IsKill))
3992 .addReg(Op2, getKillRegState(Op2IsKill))
3993 .addReg(Op3, getKillRegState(Op3IsKill));
3996 .addReg(Op0, getKillRegState(Op0IsKill))
3997 .addReg(Op1, getKillRegState(Op1IsKill))
3998 .addReg(Op2, getKillRegState(Op2IsKill))
3999 .addReg(Op3, getKillRegState(Op3IsKill));
lib/Target/X86/X86FrameLowering.cpp 2106 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
lib/Target/X86/X86InstrBuilder.h 159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
lib/Target/X86/X86InstrInfo.cpp 801 .addReg(Src, getKillRegState(IsKill));
853 .addReg(Src2, getKillRegState(IsKill2));
962 .addReg(SrcReg, getKillRegState(isKill))
996 .addReg(SrcReg, getKillRegState(isKill));
1018 .addReg(SrcReg, getKillRegState(isKill));
1102 .addReg(SrcReg, getKillRegState(isKill));
1143 .addReg(SrcReg, getKillRegState(isKill));
3032 .addReg(SrcReg, getKillRegState(KillSrc));
3258 .addReg(SrcReg, getKillRegState(isKill));
5542 getKillRegState(ImpOp.isKill()) |
lib/Target/XCore/XCoreInstrInfo.cpp 340 .addReg(SrcReg, getKillRegState(KillSrc))
352 .addReg(SrcReg, getKillRegState(KillSrc));
375 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/XCore/XCoreRegisterInfo.cpp 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))