reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
215 int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; } 218 int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; } 230 return ScheduleInfo[Node->NodeNum].ZeroLatencyDepth; 239 return ScheduleInfo[Node->NodeNum].ZeroLatencyHeight;include/llvm/CodeGen/MachineScheduler.h
454 return SUPressureDiffs[SU->NodeNum]; 457 return SUPressureDiffs[SU->NodeNum];include/llvm/CodeGen/ScheduleDAG.h
344 bool isBoundaryNode() const { return NodeNum == BoundaryID; }
include/llvm/CodeGen/ScheduleDFS.h146 return DFSNodeData[SU->NodeNum].InstrCount; 159 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth()); 172 assert(SU->NodeNum < DFSNodeData.size() && "New Node"); 173 return DFSNodeData[SU->NodeNum].SubtreeID;lib/CodeGen/LatencyPriorityQueue.cpp
32 unsigned LHSNum = LHS->NodeNum; 33 unsigned RHSNum = RHS->NodeNum; 82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;lib/CodeGen/MachinePipeliner.cpp
790 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) 790 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) 811 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) 811 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) 1152 int N = SI.getSUnit()->NodeNum; 1166 int N = SI.getSUnit()->NodeNum; 1179 int N = PI.getSUnit()->NodeNum; 1245 if (Blocked.test(W->NodeNum)) 1246 unblock(W->NodeNum); 1597 return A->NodeNum > B->NodeNum; 1597 return A->NodeNum > B->NodeNum; 1615 dbgs() << "Excess register pressure: SU(" << SU->NodeNum << ") " 1774 if (NI.getNode(0)->NodeNum == NJ.getNode(0)->NodeNum) { 1774 if (NI.getNode(0)->NodeNum == NJ.getNode(0)->NodeNum) { 1841 (getASAP(SU) == getASAP(maxASAP) && SU->NodeNum > maxASAP->NodeNum)) 1841 (getASAP(SU) == getASAP(maxASAP) && SU->NodeNum > maxASAP->NodeNum)) 1869 LLVM_DEBUG(dbgs() << maxHeight->NodeNum << " "); 1914 LLVM_DEBUG(dbgs() << maxDepth->NodeNum << " "); 1953 dbgs() << " " << I->NodeNum << " "; 1992 dbgs() << "Inst (" << SU->NodeNum << ") "; 2742 LLVM_DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum 2742 LLVM_DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum 2743 << " are scheduled before node " << SU->NodeNum 2864 os << " SU(" << I->NodeNum << ") " << *(I->getInstr()); 2877 os << "(" << CI->NodeNum << ") ";lib/CodeGen/MachineScheduler.cpp
599 dbgs() << SU->NodeNum << " "; 1118 LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " 1153 LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") " 1364 LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU(" 1365 << SU->NodeNum << ") = " << CyclicLatency << "c\n"); 1482 return std::make_tuple(BaseOp->getReg(), Offset, SU->NodeNum) < 1484 RHS.SU->NodeNum); 1500 return SU->NodeNum < RHS.SU->NodeNum; 1500 return SU->NodeNum < RHS.SU->NodeNum; 1577 LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU(" 1578 << SUb->NodeNum << ")\n"); 1586 LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum 1610 ChainPredID = Pred.getSUnit()->NodeNum; 1794 LLVM_DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n"); 1798 LLVM_DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU(" 1799 << GlobalSU->NodeNum << ")\n"); 1804 LLVM_DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU(" 1805 << FirstLocalSU->NodeNum << ")\n"); 2002 LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops=" 2010 LLVM_DEBUG(dbgs() << " hazard: SU(" << SU->NodeNum << ") must " 2028 LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") " 2053 << LateSU->NodeNum << ") " << RemLatency << "c\n"); 2298 << SU->NodeNum << ") " << TopLatency << "c\n"); 2303 << SU->NodeNum << ") " << BotLatency << "c\n"); 2627 dbgs() << " Cand SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); 2980 << " Try SU(" << Cand.SU->NodeNum << ") " 3091 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) 3091 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) 3092 || (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { 3092 || (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { 3248 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " 3395 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) 3395 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) 3441 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " 3532 << "SU(" << SU->NodeNum << ") " 3589 return A->NodeNum > B->NodeNum; 3589 return A->NodeNum > B->NodeNum; 3591 return A->NodeNum < B->NodeNum; 3591 return A->NodeNum < B->NodeNum; 3717 SS << "SU:" << SU->NodeNum;lib/CodeGen/ScheduleDAG.cpp
360 dbgs() << "SU(" << SU.NodeNum << ")"; 481 int NodeNum = SU.NodeNum; 498 if (SU->NodeNum < DAGSize) 499 Allocate(SU->NodeNum, --Id); 502 if (SU->NodeNum < DAGSize && !--Node2Index[SU->NodeNum]) 502 if (SU->NodeNum < DAGSize && !--Node2Index[SU->NodeNum]) 516 assert(Node2Index[SU.NodeNum] > Node2Index[PD.getSUnit()->NodeNum] && 516 assert(Node2Index[SU.NodeNum] > Node2Index[PD.getSUnit()->NodeNum] && 550 LowerBound = Node2Index[Y->NodeNum]; 551 UpperBound = Node2Index[X->NodeNum]; 579 Visited.set(SU->NodeNum); 582 unsigned s = SuccDep.getSUnit()->NodeNum; 602 int LowerBound = Node2Index[StartSU.NodeNum]; 603 int UpperBound = Node2Index[TargetSU.NodeNum]; 624 unsigned s = Succ->NodeNum; 658 unsigned s = Pred->NodeNum; 722 LowerBound = Node2Index[TargetSU->NodeNum]; 723 UpperBound = Node2Index[SU->NodeNum];lib/CodeGen/ScheduleDAGInstrs.cpp
102 dbgs() << "SU(" << su->NodeNum << ")"; 698 if ((*SUItr)->NodeNum <= BarrierChain->NodeNum) 698 if ((*SUItr)->NodeNum <= BarrierChain->NodeNum) 819 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI); 891 << BarrierChain->NodeNum << ").\n";); 1050 NodeNums.push_back(SU->NodeNum); 1053 NodeNums.push_back(SU->NodeNum); 1066 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) { 1066 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) { 1070 << BarrierChain->NodeNum << ").\n";); 1074 << BarrierChain->NodeNum << ").\n";); 1247 return R.DFSNodeData[SU->NodeNum].SubtreeID 1254 R.DFSNodeData[SU->NodeNum].InstrCount = 1264 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum; 1264 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum; 1265 RootData RData(SU->NodeNum); 1273 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount; 1277 unsigned PredNum = PredDep.getSUnit()->NodeNum; 1286 RootSet[PredNum].ParentNodeID = SU->NodeNum; 1297 RootSet[SU->NodeNum] = RData; 1304 R.DFSNodeData[Succ->NodeNum].InstrCount 1305 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount; 1340 unsigned PredTree = SubtreeClasses[P.first->NodeNum]; 1341 unsigned SuccTree = SubtreeClasses[P.second->NodeNum]; 1359 unsigned PredNum = PredSU->NodeNum; 1374 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum; 1375 SubtreeClasses.join(Succ->NodeNum, PredNum);lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
186 unsigned LHSNum = LHS->NodeNum; 187 unsigned RHSNum = RHS->NodeNum; 233 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 422 ResCount += (NumNodesSolelyBlocking[SU->NodeNum] * ScaleTwo);lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
238 LLVM_DEBUG(dbgs() << "Unfolding SU # " << SU->NodeNum << "\n"); 252 N->setNodeId(NewSU->NodeNum); 274 LoadNode->setNodeId(LoadSU->NodeNum); 348 LLVM_DEBUG(dbgs() << "Duplicating SU # " << SU->NodeNum << "\n"); 595 LLVM_DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum 596 << " to SU #" << Copies.front()->NodeNum << "\n"); 601 LLVM_DEBUG(dbgs() << "Adding an edge from SU # " << NewDef->NodeNum 602 << " to SU #" << TrySU->NodeNum << "\n");lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
281 if (NewNode->NodeNum >= NumSUnits) 291 if (NewNode->NodeNum >= NumSUnits) 1013 LoadNode->setNodeId(LoadSU->NodeNum); 1032 N->setNodeId(NewSU->NodeNum); 1048 LLVM_DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n"); 1183 LLVM_DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"); 1449 LLVM_DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n'); 1473 dbgs() << " SU #" << CurSU->NodeNum << '\n'); 1524 LLVM_DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum 1525 << ") to SU(" << TrySU->NodeNum << ")\n"); 1578 LLVM_DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum 1579 << " to SU #" << Copies.front()->NodeNum << "\n"); 1584 LLVM_DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum 1585 << " to SU #" << TrySU->NodeNum << "\n"); 1943 if (SUNumbers[SU->NodeNum] != 0) 1944 return SUNumbers[SU->NodeNum]; 1964 if (SUNumbers[PredSU->NodeNum] == 0) { 1987 unsigned PredSethiUllman = SUNumbers[PredSU->NodeNum]; 1999 SUNumbers[TempSU->NodeNum] = SethiUllmanNumber; 2003 assert(SUNumbers[SU->NodeNum] > 0 && "SethiUllman should never be zero!"); 2004 return SUNumbers[SU->NodeNum]; 2024 SethiUllmanNumbers[SU->NodeNum] = 0; 2031 assert(SU->NodeNum < SethiUllmanNumbers.size()); 2055 return SethiUllmanNumbers[SU->NodeNum]; 2230 LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum 2413 LLVM_DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"); 2451 LLVM_DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"); 2511 LLVM_DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum 2512 << ") depth " << LDepth << " vs SU (" << right->NodeNum 2535 LLVM_DEBUG(dbgs() << " SU (" << left->NodeNum << ") " 2536 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum 2681 LLVM_DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU(" 2682 << right->NodeNum << ")\n"); 2686 LLVM_DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU(" 2687 << left->NodeNum << ")\n"); 2749 LLVM_DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum 2750 << "): " << LPDiff << " != SU(" << right->NodeNum 2763 LLVM_DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses 2764 << " != SU(" << right->NodeNum << "): " << RLiveUses 2779 LLVM_DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): " 2780 << left->getDepth() << " != SU(" << right->NodeNum 3026 dbgs() << " Prescheduling SU #" << SU.NodeNum << " next to PredSU #" 3027 << PredSU->NodeNum 3119 << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n"); 3119 << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n");lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
372 N->setNodeId(NodeSUnit->NodeNum); 389 N->setNodeId(NodeSUnit->NodeNum); 412 N->setNodeId(NodeSUnit->NodeNum);lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
277 O << "SU(" << SU->NodeNum << "): ";
lib/Target/AMDGPU/AMDGPUSubtarget.cpp782 if (Pred->NodeNum < Succ->NodeNum) 782 if (Pred->NodeNum < Succ->NodeNum)lib/Target/AMDGPU/GCNILPSched.cpp
60 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; 88 assert(SU->NodeNum < SUNumbers.size()); 102 return SUNumbers[SU->NodeNum]; 152 LLVM_DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum 153 << ") depth " << LDepth << " vs SU (" << right->NodeNum 172 LLVM_DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): " 173 << left->getDepth() << " != SU(" << right->NodeNum 301 SUSavedCopy[SU.NodeNum] = SU; 331 << ' ' << C.SU->NodeNum; 352 SU = SUSavedCopy[SU.NodeNum];lib/Target/AMDGPU/GCNMinRegStrategy.cpp
46 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max(); 51 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max(); 56 assert(NumPreds[SU->NodeNum] != std::numeric_limits<unsigned>::max()); 57 return NumPreds[SU->NodeNum]; 62 assert(NumPreds[SU->NodeNum] != std::numeric_limits<unsigned>::max()); 63 return --NumPreds[SU->NodeNum]; 154 LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would left non-ready " 165 LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would make ready " << Res 176 Num = findMax(Num, [=](const Candidate &C) { return -(int64_t)C.SU->NodeNum; }); 207 LLVM_DEBUG(dbgs() << "Make the predecessors of SU(" << SchedSU->NodeNum 214 LLVM_DEBUG(dbgs() << " SU(" << C.SU->NodeNum << ')'); 253 << ' ' << C.SU->NodeNum << "(P" << C.Priority << ')';lib/Target/AMDGPU/GCNSchedStrategy.cpp
307 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
lib/Target/AMDGPU/SIMachineScheduler.cpp198 NodeNum2Index[SU->NodeNum] = SUnits.size(); 205 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); 257 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { 257 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { 274 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; 275 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; 277 HasLowLatencyNonWaitedParent[NodeNum2Index[SU->NodeNum]]; 487 if (SuccSU->NodeNum >= DAG->SUnits.size()) 512 if (HasLowLatencyNonWaitedParent[NodeNum2Index[SU->NodeNum]]) 515 if (DAG->IsLowLatencySU[SU->NodeNum]) { 518 NodeNum2Index.find(Succ.getSUnit()->NodeNum); 530 if (DAG->IsHighLatencySU[SU->NodeNum]) 653 if (SU->NodeNum >= DAG->SUnits.size()) 655 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID; 663 if (DAG->IsHighLatencySU[SU->NodeNum]) { 664 CurrentColoring[SU->NodeNum] = NextReservedID++; 689 if (DAG->IsHighLatencySU[SU->NodeNum]) 705 if (DAG->IsHighLatencySU[SU.NodeNum]) { 777 FormingGroup.insert(SU.NodeNum); 780 CurrentColoring[SU.NodeNum] = ProposedColor; 790 FormingGroup.insert(SU.NodeNum); 791 CurrentColoring[SU.NodeNum] = ProposedColor; 821 if (CurrentColoring[SU->NodeNum]) { 822 CurrentTopDownReservedDependencyColoring[SU->NodeNum] = 823 CurrentColoring[SU->NodeNum]; 829 if (PredDep.isWeak() || Pred->NodeNum >= DAGSize) 831 if (CurrentTopDownReservedDependencyColoring[Pred->NodeNum] > 0) 832 SUColors.insert(CurrentTopDownReservedDependencyColoring[Pred->NodeNum]); 839 CurrentTopDownReservedDependencyColoring[SU->NodeNum] = 845 CurrentTopDownReservedDependencyColoring[SU->NodeNum] = Pos->second; 847 CurrentTopDownReservedDependencyColoring[SU->NodeNum] = 863 if (CurrentColoring[SU->NodeNum]) { 864 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] = 865 CurrentColoring[SU->NodeNum]; 871 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 873 if (CurrentBottomUpReservedDependencyColoring[Succ->NodeNum] > 0) 874 SUColors.insert(CurrentBottomUpReservedDependencyColoring[Succ->NodeNum]); 881 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] = 887 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] = Pos->second; 889 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] = 909 if (CurrentColoring[SU->NodeNum]) 912 SUColors.first = CurrentTopDownReservedDependencyColoring[SU->NodeNum]; 913 SUColors.second = CurrentBottomUpReservedDependencyColoring[SU->NodeNum]; 918 CurrentColoring[SU->NodeNum] = Pos->second; 920 CurrentColoring[SU->NodeNum] = NextNonReservedID; 946 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 949 if (CurrentBottomUpReservedDependencyColoring[SU->NodeNum] > 0 || 950 CurrentTopDownReservedDependencyColoring[SU->NodeNum] > 0) 955 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 957 if (CurrentBottomUpReservedDependencyColoring[Succ->NodeNum] > 0 || 958 CurrentTopDownReservedDependencyColoring[Succ->NodeNum] > 0) 959 SUColors.insert(CurrentColoring[Succ->NodeNum]); 960 SUColorsPending.insert(PendingColoring[Succ->NodeNum]); 966 PendingColoring[SU->NodeNum] = *SUColors.begin(); 969 PendingColoring[SU->NodeNum] = NextNonReservedID++; 989 assert(i == SU->NodeNum); 995 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 1015 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 1020 if (SU->Preds.size() > 0 && !DAG->IsLowLatencySU[SU->NodeNum]) 1025 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1027 SUColors.insert(CurrentColoring[Succ->NodeNum]); 1030 CurrentColoring[SU->NodeNum] = *SUColors.begin(); 1041 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 1046 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1048 SUColors.insert(CurrentColoring[Succ->NodeNum]); 1051 CurrentColoring[SU->NodeNum] = *SUColors.begin(); 1062 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 1067 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1069 SUColors.insert(CurrentColoring[Succ->NodeNum]); 1072 CurrentColoring[SU->NodeNum] = *SUColors.begin(); 1082 unsigned color = CurrentColoring[SU->NodeNum]; 1088 unsigned color = CurrentColoring[SU->NodeNum]; 1091 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 1099 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1101 SUColors.insert(CurrentColoring[Succ->NodeNum]); 1105 CurrentColoring[SU->NodeNum] = *SUColors.begin(); 1123 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize) 1128 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1133 CurrentColoring[SU->NodeNum] = GroupID; 1228 unsigned Color = CurrentColoring[SU->NodeNum]; 1236 Node2CurrentBlock[SU->NodeNum] = RealID[Color]; 1245 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1247 if (Node2CurrentBlock[Succ->NodeNum] != SUID) 1248 CurrentBlocks[SUID]->addSucc(CurrentBlocks[Node2CurrentBlock[Succ->NodeNum]], 1253 if (PredDep.isWeak() || Pred->NodeNum >= DAGSize) 1255 if (Node2CurrentBlock[Pred->NodeNum] != SUID) 1256 CurrentBlocks[SUID]->addPred(CurrentBlocks[Node2CurrentBlock[Pred->NodeNum]]); 1793 Res.SUs.push_back(SU->NodeNum); 1845 if (Pred->NodeNum >= DAGSize) 1847 unsigned PredPos = ScheduledSUnitsInv[Pred->NodeNum]; 1863 ScheduledSUnits[BestPos] = SU->NodeNum; 1864 ScheduledSUnitsInv[SU->NodeNum] = BestPos; 1877 if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize) 1890 ScheduledSUnits[MinPos] = SU->NodeNum; 1891 ScheduledSUnitsInv[SU->NodeNum] = MinPos; 2037 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "lib/Target/Hexagon/HexagonMachineScheduler.cpp
180 LLVM_DEBUG(dbgs() << Packet[i]->NodeNum << ")\t"); 509 dbgstr << "SU(" << std::setw(3) << (*I)->NodeNum << ")"; 798 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) 798 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) 799 || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { 799 || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { 859 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) 859 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) 860 || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { 860 || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) {lib/Target/Hexagon/HexagonSubtarget.cpp
513 if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) { 513 if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) { 516 if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum) 516 if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)lib/Target/SystemZ/SystemZHazardRecognizer.cpp
168 OS << "SU(" << SU->NodeNum << "):";
lib/Target/SystemZ/SystemZMachineScheduler.cpp235 if (SU->NodeNum < other.SU->NodeNum) 235 if (SU->NodeNum < other.SU->NodeNum) 242 LLVM_DEBUG(dbgs() << "** Scheduling SU(" << SU->NodeNum << ") ";lib/Target/SystemZ/SystemZMachineScheduler.h
85 return (lhs->NodeNum < rhs->NodeNum); 85 return (lhs->NodeNum < rhs->NodeNum);