|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc78720 if (Src0 == Src1)
include/llvm/ADT/SmallSet.h 240 if (*I == V)
include/llvm/CodeGen/SelectionDAGNodes.h 148 return !operator==(O);
232 return LHS == RHS;
295 return Val == V;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1709 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1711 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
2174 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2178 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2183 N0.getOperand(0) == N1.getOperand(1))
2189 N0.getOperand(1) == N1.getOperand(0))
2195 N0 == N1.getOperand(1).getOperand(0))
2201 N0 == N1.getOperand(1).getOperand(1))
2208 N0 == N1.getOperand(0).getOperand(1))
2781 if (Carry0.getOperand(0) == Carry1.getValue(0)) {
2792 if (Carry1.getOperand(0) == Carry0.getValue(0)) {
2796 if (Carry1.getOperand(1) == Carry0.getValue(0)) {
2871 if (N0 == N1)
2930 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
2934 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
2938 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
2987 N0.getOperand(1).getOperand(0) == N1)
2993 N0.getOperand(1).getOperand(1) == N1)
2999 N0.getOperand(1).getOperand(1) == N1)
3101 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3101 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3101 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3101 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3182 if (N0 == N1)
3211 if (N0 == N1)
3242 if (N0 == N1)
3555 User->getOperand(0) == Op0 &&
3556 User->getOperand(1) == Op1) {
3608 if (N0 == N1)
4320 N0.getOperand(1) == N1.getOperand(1)) {
4388 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4401 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4439 if (LR == RR && CC0 == CC1 && IsInteger) {
4484 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
4515 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
4538 if (LL == RR && LR == RL) {
4538 if (LL == RR && LR == RL) {
4545 if (LL == RL && LR == RR) {
4545 if (LL == RL && LR == RR) {
5040 if (N0 == N1)
5644 N0.getOperand(0) == N1.getOperand(0) &&
5661 if (isBitwiseNot(N0.getOperand(1)) && N0.getOperand(1).getOperand(0) == N1)
5665 if (isBitwiseNot(N0.getOperand(0)) && N0.getOperand(0).getOperand(0) == N1)
5678 if (N0 == N1)
5909 ExtractFrom.getOperand(0) == ExtractFrom.getOperand(1) &&
5910 ExtractFrom.getOperand(0) == OppShiftLHS &&
6080 if (Pos == NegOp1)
6092 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
6810 if (Other == Xor0)
6968 if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) {
7004 if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0)) {
7004 if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0)) {
7004 if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0)) {
7004 if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0)) {
7014 if (N0 == N1)
7491 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
7564 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
7649 N0.getOperand(0).getOperand(1) == N1 && N0.getOperand(0).hasOneUse()) {
7805 if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
8001 if (N0 == N1 && hasOperation(RotOpc, VT))
8135 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
8135 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
8135 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
8135 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
8149 unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
8153 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
8164 unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
8168 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
8337 if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1)))
8357 if (VT == VT0 && VT == MVT::i1 && (N0 == N2 || isNullConstant(N2)))
8408 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
8427 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
8470 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) {
8705 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
8705 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
8708 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
8708 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
8802 if (N2 == N3)
8996 if (UseOp == N0)
9043 if (SOp == OrigLoad)
11992 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
11996 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
12022 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
12030 N1.getOperand(0) == N1.getOperand(1) &&
12031 N0.getOperand(0) == N1.getOperand(0)) {
12043 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
12051 N0.getOperand(0) == N0.getOperand(1) &&
12052 N1.getOperand(0) == N0.getOperand(0)) {
12062 if (!CFP00 && N0.getOperand(0) == N0.getOperand(1) &&
12063 (N0.getOperand(0) == N1)) {
12072 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
12073 N1.getOperand(0) == N0) {
12081 N0.getOperand(0) == N0.getOperand(1) &&
12082 N1.getOperand(0) == N1.getOperand(1) &&
12083 N0.getOperand(0) == N1.getOperand(0)) {
12128 if (N0 == N1) {
12153 if (N0 == N1->getOperand(0))
12156 if (N0 == N1->getOperand(1))
12244 N0.getOperand(0) == N0.getOperand(1)) {
12283 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X &&
12373 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) &&
12420 if (N1CFP && N0 == N2) {
12428 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
12480 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
13573 if (Val == BasePtr)
13577 if (Val == Ptr || Ptr->isPredecessorOf(Val.getNode()))
14880 Chain == SDValue(N0.getNode(), 1)) {
15043 if (Use->getOperand(0) == ConstNode)
16223 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
16237 if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
16237 if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
16516 if (InsertVal.getOperand(0) == X) {
16518 } else if (InsertVal.getOperand(0) == Y) {
16602 InVec == InVal.getOperand(0) && EltNo == InVal.getOperand(1))
16602 InVec == InVal.getOperand(0) && EltNo == InVal.getOperand(1))
16808 Index == VecOp.getOperand(2)) {
16938 Use->getOperand(0) == VecOp &&
17590 Op0.getOperand(0).getOperand(0) == Op.getOperand(0).getOperand(0))
17669 (Op0.getOperand(0) == Op.getOperand(0)))
17824 if (SV0.isUndef() || SV0 == ExtVec) {
17828 } else if (SV1.isUndef() || SV1 == ExtVec) {
18021 V.getOperand(1).getValueType() == SubVT && V.getOperand(2) == Index) {
18521 IsSplat = (Splat0 == BV1->getSplatValue());
18860 if (N0 == N1) {
19077 bool HasSameOp0 = N0 == SV0;
19079 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
19144 if (!SV0.getNode() || SV0 == CurrentVec) {
19255 N1.getOperand(1) == N2 && N1.getOperand(0).getValueType() == VT)
19264 N1.getOperand(0).getOperand(1) == N2 &&
19295 N0.getOperand(2) == N2)
19609 (LHS.hasOneUse() || RHS.hasOneUse() || LHS == RHS)) {
19624 LHS.getOperand(2) == RHS.getOperand(2) &&
19742 Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT ||
19923 if (!(isAllOnesConstant(N1) || (isNullConstant(N1) && N0 == N2)))
19928 if (!(isNullConstant(N1) || (isOneConstant(N1) && N0 == N2)))
20033 if (N2 == N3) return N2;
20159 N0 == Count.getOperand(0) &&
20166 N0 == Count.getOperand(0) &&
20516 if (MUC0.BasePtr.getNode() && MUC0.BasePtr == MUC1.BasePtr &&
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1985 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 3653 if (RHSLo == RHSHi) {
3738 if (LHSHi == RHSHi) {
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1591 if (N1 == N2) {
2010 if (N1 == N2)
4132 if (A == B) return true;
4221 assert((!IdentitySrc || IdentitySrc == Op.getOperand(0)) &&
5062 if (N1 == N2) return N1;
5354 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) &&
5550 N2.getOperand(1) == N3 && N2.getOperand(0).getValueType() == VT)
7125 if (T == F)
7452 if (Op == N->getOperand(0)) return N;
7477 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
7477 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
8031 if (From == To || FromNode == ToNode)
8201 if (FromN == getRoot())
8316 if (From == To) return;
8372 if (From == getRoot())
8630 if (OldChain == NewChain || !OldLoad->hasAnyUseOfValue(1))
8947 return any_of(N->op_values(), [this](SDValue Op) { return *this == Op; });
8967 if (*this == Dest) return true;
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 33 if ((Other.Index == Index) && (Other.IsIndexSignExt == IsIndexSignExt)) {
35 if (Other.Base == Base)
137 if ((BasePtr0.getIndex() == BasePtr1.getIndex() || (IsFI0 != IsFI1) ||
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 1063 if (PendingExports[i].getNode()->getOperand(0) == Root)
6244 if (X == Y && isPowerOf2_32(VT.getScalarSizeInBits())) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2468 return N == RecordedNodes[RecNo].first;
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2794 if (N0.getOperand(0) == N1) {
2797 } else if (N0.getOperand(1) == N1) {
3023 if (X == N1)
3113 (N0 == CTPOP ||
3401 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3755 if (N0 == N1) {
3782 if (N0.getOperand(0) == N1.getOperand(0))
3784 if (N0.getOperand(1) == N1.getOperand(1))
3788 if (N0.getOperand(0) == N1.getOperand(1))
3791 if (N0.getOperand(1) == N1.getOperand(0))
4887 return Value == *SplatValue || Predicate(Value);
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1997 if (Op.getOperand(1) == Orig) {
2003 if (Op.getOperand(0) == Orig)
2015 if (Op.getOperand(1) == Orig) {
2021 if (Op.getOperand(0) == Orig)
lib/Target/AArch64/AArch64ISelLowering.cpp 6280 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
9303 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
9304 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
10017 if (N0 == N1 && VT.getVectorNumElements() == 2) {
10918 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
11091 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
11542 if (TestSrc == NewTestSrc)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2494 if (Lo == Hi && !isInlineImmediate(Lo.getNode())) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1264 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1264 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1264 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1264 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1285 if (LHS == True)
1304 if (LHS == True)
1310 if (LHS == True)
1322 if (LHS == True)
3443 RHS.getOperand(0) == CmpLHS &&
3452 LHS.getOperand(0) == CmpLHS &&
lib/Target/AMDGPU/R600ISelLowering.cpp 1725 if (NewBldVec[i] == NewBldVec[j]) {
lib/Target/AMDGPU/SIISelLowering.cpp 8340 (RHS.getOperand(0) == LHS.getOperand(0) &&
8341 LHS.getOperand(0) == LHS.getOperand(1))) {
9623 if (A == LHS.getOperand(1)) {
9635 if (A == RHS.getOperand(1)) {
9667 if (A == LHS.getOperand(1)) {
9682 if (A == RHS.getOperand(1)) {
9751 Idx1 == Idx2)
9754 if (Vec1 == Vec2 || Vec3 == Vec4)
9754 if (Vec1 == Vec2 || Vec3 == Vec4)
9760 if ((Vec1 == Vec3 && Vec2 == Vec4) ||
9760 if ((Vec1 == Vec3 && Vec2 == Vec4) ||
9761 (Vec1 == Vec4 && Vec2 == Vec3)) {
9761 (Vec1 == Vec4 && Vec2 == Vec3)) {
10321 (Src0 == Src1 || Src0 == Src2))
10321 (Src0 == Src1 || Src0 == Src2))
lib/Target/AMDGPU/SIInstrInfo.cpp 125 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
lib/Target/ARM/ARMISelDAGToDAG.cpp 2798 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2798 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2948 Ptr.getOperand(0) == ST->getChain()) {
lib/Target/ARM/ARMISelLowering.cpp 4704 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4704 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4704 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4704 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4706 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4706 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4706 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4706 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4714 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4714 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4714 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4714 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4716 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4716 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4716 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4716 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4763 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4764 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4765 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4777 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4853 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4854 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
7059 return U.get().isUndef() || U.get() == FirstOp;
7230 if (Op.getOperand(I) == Value)
7355 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
10964 N0 == N1)
11002 N00 == N10)
11291 if (MULOp == SDValue())
11295 if (MULOp == SDValue())
11319 if (AddcSubcOp0 == MULOp.getValue(0)) {
11323 if (AddcSubcOp1 == MULOp.getValue(0)) {
11810 if (N0 == N1)
12539 if (CombineBFI == SDValue())
12548 assert(From1 == From2);
12978 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
14186 if (Target == OtherTarget)
14281 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
14284 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
14384 FalseVal.getOperand(0) == LHS && FalseVal.getOperand(1) == RHS) ||
14384 FalseVal.getOperand(0) == LHS && FalseVal.getOperand(1) == RHS) ||
14385 (FalseVal == LHS && isNullConstant(RHS))) &&
15365 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 968 if (LDBasePtr == STBasePtr)
lib/Target/Hexagon/HexagonISelLowering.cpp 2169 if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2231 if (Elem[i] == Elem[First] || isUndef(Elem[i]))
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 642 assert(Values[I+B].isUndef() || Values[I+B] == F);
lib/Target/Mips/MipsSEISelLowering.cpp 582 return N->getOperand(1) == OfNode;
585 return N->getOperand(0) == OfNode;
905 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 4558 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4559 U->getOperand(1) == Den) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 1310 if (LHSBits[i].hasValue() && LHSBits[i].getValue() == LastVal &&
1313 else if (RHSBits[i].hasValue() && RHSBits[i].getValue() == LastVal &&
1487 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1515 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1603 if (&BG != &BG2 && BG.V == BG2.V &&
1633 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1659 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1659 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1838 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1871 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
2279 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
4283 if (LHS == InnerRHS && RHS == InnerLHS)
4283 if (LHS == InnerRHS && RHS == InnerLHS)
4949 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
5298 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
5401 } else if ((LHS == ORHS && RHS == OLHS) ||
5401 } else if ((LHS == ORHS && RHS == OLHS) ||
5402 (RHS == ORHS && LHS == OLHS)) {
5402 (RHS == ORHS && LHS == OLHS)) {
5669 Op.getOperand(0) == Op.getOperand(1))
5696 Op.getOperand(0) == Op.getOperand(1))
5707 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5740 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5779 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5812 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5886 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5926 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5962 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
lib/Target/PowerPC/PPCISelLowering.cpp 2594 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
7243 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) {
7243 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) {
9546 if (UI->getOperand(0) == Op.getOperand(0) &&
9547 UI->getOperand(1) == Op.getOperand(1))
11744 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
12180 if (User->getOperand(0) == Inputs[i])
12183 if (User->getOperand(0) == Inputs[i] ||
12184 User->getOperand(1) == Inputs[i])
12204 if (User->getOperand(0) == PromOps[i])
12207 if (User->getOperand(0) == PromOps[i] ||
12208 User->getOperand(1) == PromOps[i])
12390 if (User->getOperand(0) == Inputs[i])
12394 if (User->getOperand(0) == Inputs[i])
12397 if (User->getOperand(1) == Inputs[i])
12415 if (User->getOperand(0) == PromOps[i])
12419 if (User->getOperand(0) == PromOps[i])
12422 if (User->getOperand(1) == PromOps[i])
13835 V1.getOperand(1) == V2) {
13841 V2.getOperand(1) == V1) {
13846 V1.getOperand(0) == V2.getOperand(1) &&
13847 V1.getOperand(1) == V2.getOperand(0)) {
13935 UI->getOperand(1) == N->getOperand(1) &&
13936 UI->getOperand(2) == N->getOperand(2) &&
13937 UI->getOperand(0) == N->getOperand(0)) {
13956 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
15560 if (TrueOpnd.getOperand(0) == CmpOpnd1 &&
15561 TrueOpnd.getOperand(1) == CmpOpnd2 &&
15562 FalseOpnd.getOperand(0) == CmpOpnd2 &&
15563 FalseOpnd.getOperand(1) == CmpOpnd1) {
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 709 Index.getOperand(1) == Elem) {
1278 if (Chain == Load.getValue(1)) {
1288 if (Op == Load.getValue(1)) {
lib/Target/SystemZ/SystemZISelLowering.cpp 2149 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
2149 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
2150 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
2150 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
2772 Neg.getOperand(1) == Pos &&
2773 (Pos == CmpOp ||
2775 Pos.getOperand(0) == CmpOp)));
4365 if (Ops[OpNo] == Op)
4644 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
5496 if (Op1 == N->getOperand(0))
5729 if (N->getOperand(0) == N->getOperand(1))
5760 U->getOperand(0) == Vec &&
5765 OtherRound.getOperand(0) == SDValue(U, 0) &&
5811 U->getOperand(0) == Vec &&
5816 OtherExtend.getOperand(0) == SDValue(U, 0) &&
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 1433 return Lane == SplatValue;
lib/Target/X86/X86ISelDAGToDAG.cpp 1178 N->getOperand(0) == N->getOperand(1) &&
1225 N->getOperand(0) == N->getOperand(1) &&
2448 assert (T == AM.Segment);
2884 if (Chain == Load.getValue(1)) {
2890 if (Op == Load.getValue(1)) {
4334 if (N0.getOperand(0) == A)
4336 else if (N0.getOperand(1) == A)
lib/Target/X86/X86ISelLowering.cpp 5126 return N->getOperand(1) == N->getOperand(0).getOperand(1);
6434 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6442 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6449 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6469 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6476 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6482 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6488 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6494 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6503 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6610 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6618 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6638 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6655 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
6679 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(2);
7138 bool IsUnary = (N0 == N1);
7537 Op.getOperand(0) == Op.getOperand(2) &&
7538 Op.getOperand(1) == Op.getOperand(3) &&
7621 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
7633 CanFold = (SrcVector == V1) && (Current.getConstantOperandAPInt(1) == i);
8016 Match &= (RepeatedLoads[i % SubElems] == Elt);
8123 if (Op->getOperand(i) == ExtValue) {
8462 if (ExtractedFromVec == VecIn1)
8464 else if (ExtractedFromVec == VecIn2)
8636 Op0.getOperand(0) == Op1.getOperand(0) &&
8663 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
8667 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
9115 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) &&
9116 ((InVec1.isUndef() || InVec3.isUndef()) || InVec1 == InVec3))
9122 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) &&
9123 ((InVec1.isUndef() || InVec3.isUndef()) || InVec1 == InVec3))
10316 MaskBV->getOperand(Mask[i] % Size) ==
11247 if (M < NumElts && (Op.isUndef() || Op == V1))
11249 else if (NumElts <= M && (Op.isUndef() || Op == V2))
11830 if (Idx < 0 || (Src == V && Idx == (M - i))) {
11894 } else if ((!Base || (Base == V1)) &&
11897 } else if ((!Base || (Base == V2)) &&
20760 Op0.getOperand(1) == Op1 && Op0.hasOneUse()) {
21373 (Op2.getOperand(0) == Op1 || Op2.getOperand(1) == Op1)) {
21373 (Op2.getOperand(0) == Op1 || Op2.getOperand(1) == Op1)) {
21375 Op2.getOperand(0) == Op1 ? Op2.getOperand(1) : Op2.getOperand(0);
22054 if (Cmp == Cond.getOperand(1).getOperand(1) &&
22069 if (Cmp == Cond.getOperand(1).getOperand(1) &&
25845 if (!Amt1 || Amt1 == A) {
25850 if (!Amt2 || Amt2 == A) {
33071 if (InputBC == peekThroughBitcasts(Ops[i]))
33595 if (N10 == N0 ||
33596 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) {
33930 bool IsSubAdd = Op0Even ? Op0 == FMAdd : Op1 == FMAdd;
33930 bool IsSubAdd = Op0Even ? Op0 == FMAdd : Op1 == FMAdd;
34824 if (Op0.getOpcode() == X86ISD::VSHLI && Op1 == Op0.getOperand(1)) {
35133 (ShuffleOps.size() > 1 && ShuffleOps[0] == ShuffleOps[1]) ? 2 : 1;
36420 InputVector.getOperand(2) == EltIdx) {
37109 Other->getOperand(0) == Cond.getOperand(0)) {
37117 Other->getOpcode() == ISD::SUB && OpRHS == CondRHS)
37192 if (CC == ISD::SETULE && Other == CondRHS &&
37193 (OpLHS == CondLHS || OpRHS == CondLHS))
37193 (OpLHS == CondLHS || OpRHS == CondLHS))
37197 CondLHS == OpLHS) {
37588 if (TrueOp == FalseOp)
37775 if (Const == Cond.getOperand(0))
37783 Add.getOperand(0).getOperand(0) == Cond.getOperand(0)) {
39356 if (N0.getOperand(0) == Mask)
39358 else if (N0.getOperand(1) == Mask)
39398 return N->getOpcode() == ISD::SUB && N->getOperand(1) == V &&
39423 if (V == Y)
39734 ShAmt1Op1 == ShAmt0)
39749 (ShAmt1Op0 == ShAmt0 || ShAmt1Op0 == ShMsk0)) {
39749 (ShAmt1Op0 == ShAmt0 || ShAmt1Op0 == ShMsk0)) {
39757 Op1.getOperand(0) == Op1.getOperand(1)) {
40864 if (!(A == C && B == D))
40864 if (!(A == C && B == D))
40904 if (!shouldUseHorizontalOp(LHS == RHS && NumShuffles < 2, DAG, Subtarget))
40991 (Op0 == Op1 || IsFreeTruncation(Op0) || IsFreeTruncation(Op1)))
41008 (Op0 == Op1 || IsFreeTruncation(Op0) || IsFreeTruncation(Op1)))
41018 (Op0 == Op1 || (IsFreeTruncation(Op0) && IsFreeTruncation(Op1))))
44143 if (MaxLHS == Op1)
44145 else if (MaxRHS == Op1)
44153 if (MinLHS == Op0)
44155 else if (MinRHS == Op0)
44255 if (N->getOperand(0) == N->getOperand(1)) {
44299 if (llvm::all_of(Ops, [Op0](SDValue Op) { return Op == Op0; })) {
44322 bool IsSplat = llvm::all_of(Ops, [&Op0](SDValue Op) { return Op == Op0; });
44336 Subtarget.hasInt256() && Op0.getOperand(1) == Ops[1].getOperand(1)) {
44348 Subtarget.hasAVX() && Op0.getOperand(1) == Ops[1].getOperand(1)) {
45121 return Ld->getBasePtr() == St->getBasePtr();
45134 return Ld->getBasePtr() == St->getBasePtr();
lib/Target/X86/X86InstrInfo.cpp 5921 return Load1->getOperand(I) == Load2->getOperand(I);
lib/Target/XCore/XCoreISelDAGToDAG.cpp 218 if (Chain == Old)
225 if (Chain->getOperand(i) == Old) {
usr/include/c++/7.4.0/bits/predefined_ops.h 241 { return *__it == _M_value; }
usr/include/c++/7.4.0/bits/stl_algobase.h 800 if (!(*__first1 == *__first2))
usr/include/c++/7.4.0/bits/stl_pair.h 449 { return __x.first == __y.first && __x.second == __y.second; }
449 { return __x.first == __y.first && __x.second == __y.second; }