reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/AsmPrinter/DwarfExpression.cpp

  137   unsigned RegSize = TRI.getRegSizeInBits(*RC);

lib/CodeGen/GlobalISel/InstructionSelect.cpp

  208     if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {

lib/CodeGen/GlobalISel/RegisterBank.cpp

   52       assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

  498     return TRI.getRegSizeInBits(*RC);

lib/CodeGen/TargetRegisterInfo.cpp

  299   if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
  299   if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
  307   unsigned MinSize = getRegSizeInBits(*RCA);
  315       if (!RC || getRegSizeInBits(*RC) < MinSize)
  324       if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
  324       if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
  333       if (getRegSizeInBits(*BestRC) == MinSize)
  491   return getRegSizeInBits(*RC);

lib/Target/AArch64/AArch64InstrInfo.cpp

 3251       assert(TRI.getRegSizeInBits(*getRegClass(DstReg)) ==
 3252                  TRI.getRegSizeInBits(*getRegClass(SrcReg)) &&
 3337         assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
 3338                    TRI.getRegSizeInBits(*FillRC) &&

lib/Target/AArch64/AArch64InstructionSelector.cpp

  371   switch (TRI.getRegSizeInBits(*RC)) {
  692     unsigned SrcSize = TRI.getRegSizeInBits(*SrcRC);
  693     unsigned DstSize = TRI.getRegSizeInBits(*DstRC);

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 1420     Size = TRI.getRegSizeInBits(*RC);

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  281   unsigned Size = TRI->getRegSizeInBits(*RC);
  308   unsigned Size = TRI->getRegSizeInBits(*RC) / 32;
  445   unsigned Size = TRI->getRegSizeInBits(*RC);

lib/Target/AMDGPU/GCNRegPressure.cpp

   91     (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
   93       (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
   94       (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);

lib/Target/AMDGPU/SIAddIMGInit.cpp

  127               RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;

lib/Target/AMDGPU/SIISelLowering.cpp

 3321   int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
 3464   switch (TRI.getRegSizeInBits(*VecRC)) {

lib/Target/AMDGPU/SIInsertWaitcnts.cpp

  495   unsigned Size = TRI->getRegSizeInBits(*RC);

lib/Target/AMDGPU/SIInstrInfo.cpp

  299         EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
  303         EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
  484   return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold;
  685     if (!(RI.getRegSizeInBits(*RC) % 64)) {
  788     if (RI.getRegSizeInBits(*RegClass) > 32) {
  970   if (RI.getRegSizeInBits(*DstRC) == 32) {
  972   } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
  974   } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
 2169   unsigned DstSize = RI.getRegSizeInBits(*DstRC);
 3416         uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
 3670         VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
 3833   unsigned Size = TRI->getRegSizeInBits(*RC);
 4216   unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;

lib/Target/AMDGPU/SIInstrInfo.h

  812     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
  821         assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
  828     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1285   unsigned Size = getRegSizeInBits(*RC);
 1312   unsigned Size = getRegSizeInBits(*RC);
 1338   switch (getRegSizeInBits(*SRC)) {
 1364   switch (getRegSizeInBits(*SRC)) {
 1382   switch (getRegSizeInBits(*VRC)) {
 1719   unsigned SrcSize = getRegSizeInBits(*SrcRC);
 1720   unsigned DstSize = getRegSizeInBits(*DstRC);
 1721   unsigned NewSize = getRegSizeInBits(*NewRC);

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  851   if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
  851   if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
  852       getRegSizeInBits(*SrcRC) < 256)

lib/Target/AVR/AVRAsmPrinter.cpp

  112       unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;

lib/Target/AVR/AVRFrameLowering.cpp

  254     assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
  292     assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&

lib/Target/Hexagon/BitTracker.cpp

  340     return TRI.getRegSizeInBits(VC);
  717   return TRI.getRegSizeInBits(PC);

lib/Target/Hexagon/HexagonAsmPrinter.cpp

  271   unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;

lib/Target/Hexagon/HexagonBitSimplify.cpp

  409     Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC);
  418       Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2;
 1261     uint16_t Width = HRI.getRegSizeInBits(*RC);

lib/Target/Hexagon/HexagonBitTracker.cpp

  122         return TRI.getRegSizeInBits(RC);
  126     return TRI.getRegSizeInBits(*RC);

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  594     switch (TRI->getRegSizeInBits(*RC)) {

lib/Target/Hexagon/HexagonVExtract.cpp

  138     unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;

lib/Target/Mips/MipsAsmPrinter.cpp

  334   unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
  335   unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
  336   unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;

lib/Target/Mips/MipsSEFrameLowering.cpp

  263   unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;

lib/Target/Mips/MipsSEInstrInfo.cpp

  706   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
  707   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));

lib/Target/NVPTX/NVPTXInstrInfo.cpp

   40   if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
   40   if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))

lib/Target/RISCV/RISCVInstrInfo.cpp

  122     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
  149     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?

lib/Target/SystemZ/SystemZInstrInfo.cpp

 1039            TRI->getRegSizeInBits(*MF.getRegInfo()

lib/Target/SystemZ/SystemZRegisterInfo.cpp

  347         (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
  347         (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
  354   unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  567   return TRI->getRegSizeInBits(*TRC) / 8;

lib/Target/X86/X86FastISel.cpp

 2134   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC)/8);

lib/Target/X86/X86FlagsCopyLowering.cpp

  922     int OrigRegSize = TRI->getRegSizeInBits(OrigRC) / 8;
  923     int TargetRegSize = TRI->getRegSizeInBits(SetBRC) / 8;

lib/Target/X86/X86InstrInfo.cpp

  765   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
 2874   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
 4745       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
 4769       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
 4788       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
 4902       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
 5078   unsigned RegSize = TRI.getRegSizeInBits(*RC);

lib/Target/X86/X86RegisterInfo.cpp

  135           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  135           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  142           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  142           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  149           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  149           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  156           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  156           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  170       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
  170       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  750             int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8;
 1176     int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8;
 1939           .addImm(TRI->getRegSizeInBits(*PS->RC) - 1);
 2239   int RegBytes = TRI->getRegSizeInBits(*RC) / 8;
 2287   int Bytes = TRI->getRegSizeInBits(*RC) / 8;
 2557   int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8;