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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6847 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
6848 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
6849 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
6850 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
6851 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
6852 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
6853 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
6854 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
6855 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
6856 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
6857 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
6858 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
6859 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
6860 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
6861 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
6862 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
6863 { 16, 2, 1, 0, 43, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
6864 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
6865 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
6866 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
6867 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
6868 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
6869 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
6870 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
6871 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
6872 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
6873 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
6874 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
6875 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
6876 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
6877 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
6878 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
6879 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
6880 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
6881 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
6882 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
6883 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
6884 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
6885 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
6886 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
6887 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
6888 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
6889 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
6890 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
6891 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
6892 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
6893 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
6894 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
6895 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
6896 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
6897 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
6898 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
6899 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
6900 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
6901 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
6902 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
6903 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
6904 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
6905 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
6906 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
6907 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
6908 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
6909 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
6910 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
6911 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
6912 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
6913 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
6914 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
6915 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
6916 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
6917 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
6918 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
6919 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
6920 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
6921 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
6922 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
6923 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
6924 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
6925 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
6926 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
6927 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
6928 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
6929 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
6930 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
6931 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
6932 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
6933 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
6934 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
6935 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
6936 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
6937 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
6938 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
6939 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
6940 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
6941 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
6942 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
6943 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
6944 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
6945 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
6946 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
6947 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
6948 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
6949 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
6950 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
6951 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
6952 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
6953 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
6954 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
6955 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
6956 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
6957 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
6958 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
6959 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
6960 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
6961 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
6962 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
6963 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
6964 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
6965 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
6966 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
6967 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
6968 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
6969 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
6970 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
6971 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
6972 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
6973 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
6974 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
6975 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
6976 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
6977 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
6978 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
6979 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
6980 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
6981 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
6982 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
6983 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
6984 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
6985 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
6986 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
6987 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
6988 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
6989 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
6990 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
6991 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
6992 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
6993 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
6994 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
6995 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
6996 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
6997 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
6998 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
6999 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
7000 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
7001 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
7002 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
7003 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
7004 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
7005 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
7006 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
7007 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
7008 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
7009 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
7010 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
7011 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
7012 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
7013 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
7014 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
7015 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
7016 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
7017 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
7018 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
7019 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
7020 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
7021 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = CATCHRET
7022 { 175, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #175 = CLEANUPRET
7023 { 176, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #176 = SEH_AddFP
7024 { 177, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #177 = SEH_EpilogEnd
7025 { 178, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #178 = SEH_EpilogStart
7026 { 179, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #179 = SEH_Nop
7027 { 180, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #180 = SEH_PrologEnd
7028 { 181, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #181 = SEH_SaveFPLR
7029 { 182, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #182 = SEH_SaveFPLR_X
7030 { 183, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #183 = SEH_SaveFReg
7031 { 184, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #184 = SEH_SaveFRegP
7032 { 185, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #185 = SEH_SaveFRegP_X
7033 { 186, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #186 = SEH_SaveFReg_X
7034 { 187, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #187 = SEH_SaveReg
7035 { 188, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #188 = SEH_SaveRegP
7036 { 189, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #189 = SEH_SaveRegP_X
7037 { 190, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #190 = SEH_SaveReg_X
7038 { 191, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #191 = SEH_SetFP
7039 { 192, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #192 = SEH_StackAlloc
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16062 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
16063 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
16064 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
16065 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
16066 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
16067 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
16068 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
16069 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
16070 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
16071 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
16072 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
16073 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
16074 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
16075 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
16076 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
16077 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
16078 { 16, 2, 1, 0, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
16079 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
16080 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
16081 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
16082 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
16083 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
16084 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
16085 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
16086 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
16087 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
16088 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
16089 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
16090 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
16091 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
16092 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
16093 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
16094 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
16095 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
16096 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
16097 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
16098 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
16099 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
16100 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
16101 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
16102 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
16103 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
16104 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
16105 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
16106 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
16107 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
16108 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
16109 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
16110 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
16111 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
16112 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
16113 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
16114 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
16115 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
16116 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
16117 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
16118 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
16119 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
16120 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
16121 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
16122 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
16123 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
16124 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
16125 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
16126 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
16127 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
16128 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
16129 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
16130 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
16131 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
16132 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
16133 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
16134 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
16135 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
16136 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
16137 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
16138 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
16139 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
16140 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
16141 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
16142 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
16143 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
16144 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
16145 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
16146 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
16147 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
16148 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
16149 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
16150 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
16151 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
16152 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
16153 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
16154 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
16155 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
16156 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
16157 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
16158 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
16159 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
16160 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
16161 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
16162 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
16163 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
16164 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
16165 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
16166 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
16167 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
16168 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
16169 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
16170 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
16171 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
16172 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
16173 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
16174 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
16175 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
16176 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
16177 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
16178 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
16179 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
16180 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
16181 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
16182 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
16183 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
16184 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
16185 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
16186 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
16187 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
16188 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
16189 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
16190 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
16191 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
16192 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
16193 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
16194 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
16195 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
16196 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
16197 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
16198 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
16199 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
16200 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
16201 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
16202 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
16203 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
16204 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
16205 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
16206 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
16207 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
16208 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
16209 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
16210 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
16211 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
16212 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
16213 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
16214 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
16215 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
16216 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
16217 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
16218 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
16219 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
16220 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
16221 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
16222 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
16223 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
16224 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
16225 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
16226 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
16227 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
16228 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
16229 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
16230 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
16231 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
16232 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
16233 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
16234 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
16235 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
16236 { 174, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
16237 { 175, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000001ULL, nullptr, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
16238 { 176, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x80000000001ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #176 = ATOMIC_FENCE
16239 { 177, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #177 = BUFFER_ATOMIC_ADD_ADDR64
16240 { 178, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = BUFFER_ATOMIC_ADD_ADDR64_RTN
16241 { 179, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #179 = BUFFER_ATOMIC_ADD_BOTHEN
16242 { 180, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #180 = BUFFER_ATOMIC_ADD_BOTHEN_RTN
16243 { 181, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #181 = BUFFER_ATOMIC_ADD_F32_ADDR64
16244 { 182, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #182 = BUFFER_ATOMIC_ADD_F32_BOTHEN
16245 { 183, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #183 = BUFFER_ATOMIC_ADD_F32_IDXEN
16246 { 184, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #184 = BUFFER_ATOMIC_ADD_F32_OFFEN
16247 { 185, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #185 = BUFFER_ATOMIC_ADD_F32_OFFSET
16248 { 186, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #186 = BUFFER_ATOMIC_ADD_IDXEN
16249 { 187, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #187 = BUFFER_ATOMIC_ADD_IDXEN_RTN
16250 { 188, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #188 = BUFFER_ATOMIC_ADD_OFFEN
16251 { 189, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #189 = BUFFER_ATOMIC_ADD_OFFEN_RTN
16252 { 190, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #190 = BUFFER_ATOMIC_ADD_OFFSET
16253 { 191, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #191 = BUFFER_ATOMIC_ADD_OFFSET_RTN
16254 { 192, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #192 = BUFFER_ATOMIC_ADD_X2_ADDR64
16255 { 193, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #193 = BUFFER_ATOMIC_ADD_X2_ADDR64_RTN
16256 { 194, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #194 = BUFFER_ATOMIC_ADD_X2_BOTHEN
16257 { 195, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #195 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN
16258 { 196, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #196 = BUFFER_ATOMIC_ADD_X2_IDXEN
16259 { 197, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #197 = BUFFER_ATOMIC_ADD_X2_IDXEN_RTN
16260 { 198, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #198 = BUFFER_ATOMIC_ADD_X2_OFFEN
16261 { 199, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #199 = BUFFER_ATOMIC_ADD_X2_OFFEN_RTN
16262 { 200, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #200 = BUFFER_ATOMIC_ADD_X2_OFFSET
16263 { 201, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #201 = BUFFER_ATOMIC_ADD_X2_OFFSET_RTN
16264 { 202, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #202 = BUFFER_ATOMIC_AND_ADDR64
16265 { 203, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #203 = BUFFER_ATOMIC_AND_ADDR64_RTN
16266 { 204, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #204 = BUFFER_ATOMIC_AND_BOTHEN
16267 { 205, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #205 = BUFFER_ATOMIC_AND_BOTHEN_RTN
16268 { 206, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #206 = BUFFER_ATOMIC_AND_IDXEN
16269 { 207, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #207 = BUFFER_ATOMIC_AND_IDXEN_RTN
16270 { 208, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #208 = BUFFER_ATOMIC_AND_OFFEN
16271 { 209, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #209 = BUFFER_ATOMIC_AND_OFFEN_RTN
16272 { 210, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #210 = BUFFER_ATOMIC_AND_OFFSET
16273 { 211, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #211 = BUFFER_ATOMIC_AND_OFFSET_RTN
16274 { 212, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #212 = BUFFER_ATOMIC_AND_X2_ADDR64
16275 { 213, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #213 = BUFFER_ATOMIC_AND_X2_ADDR64_RTN
16276 { 214, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #214 = BUFFER_ATOMIC_AND_X2_BOTHEN
16277 { 215, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #215 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN
16278 { 216, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #216 = BUFFER_ATOMIC_AND_X2_IDXEN
16279 { 217, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #217 = BUFFER_ATOMIC_AND_X2_IDXEN_RTN
16280 { 218, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #218 = BUFFER_ATOMIC_AND_X2_OFFEN
16281 { 219, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #219 = BUFFER_ATOMIC_AND_X2_OFFEN_RTN
16282 { 220, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #220 = BUFFER_ATOMIC_AND_X2_OFFSET
16283 { 221, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #221 = BUFFER_ATOMIC_AND_X2_OFFSET_RTN
16284 { 222, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #222 = BUFFER_ATOMIC_CMPSWAP_ADDR64
16285 { 223, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #223 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN
16286 { 224, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #224 = BUFFER_ATOMIC_CMPSWAP_BOTHEN
16287 { 225, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #225 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN
16288 { 226, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #226 = BUFFER_ATOMIC_CMPSWAP_IDXEN
16289 { 227, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #227 = BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN
16290 { 228, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #228 = BUFFER_ATOMIC_CMPSWAP_OFFEN
16291 { 229, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #229 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN
16292 { 230, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #230 = BUFFER_ATOMIC_CMPSWAP_OFFSET
16293 { 231, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #231 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN
16294 { 232, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #232 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64
16295 { 233, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #233 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN
16296 { 234, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #234 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN
16297 { 235, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #235 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN
16298 { 236, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #236 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN
16299 { 237, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #237 = BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN
16300 { 238, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #238 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN
16301 { 239, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #239 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN
16302 { 240, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #240 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET
16303 { 241, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #241 = BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN
16304 { 242, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #242 = BUFFER_ATOMIC_DEC_ADDR64
16305 { 243, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #243 = BUFFER_ATOMIC_DEC_ADDR64_RTN
16306 { 244, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #244 = BUFFER_ATOMIC_DEC_BOTHEN
16307 { 245, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #245 = BUFFER_ATOMIC_DEC_BOTHEN_RTN
16308 { 246, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #246 = BUFFER_ATOMIC_DEC_IDXEN
16309 { 247, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #247 = BUFFER_ATOMIC_DEC_IDXEN_RTN
16310 { 248, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #248 = BUFFER_ATOMIC_DEC_OFFEN
16311 { 249, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #249 = BUFFER_ATOMIC_DEC_OFFEN_RTN
16312 { 250, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #250 = BUFFER_ATOMIC_DEC_OFFSET
16313 { 251, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #251 = BUFFER_ATOMIC_DEC_OFFSET_RTN
16314 { 252, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #252 = BUFFER_ATOMIC_DEC_X2_ADDR64
16315 { 253, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #253 = BUFFER_ATOMIC_DEC_X2_ADDR64_RTN
16316 { 254, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #254 = BUFFER_ATOMIC_DEC_X2_BOTHEN
16317 { 255, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #255 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN
16318 { 256, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #256 = BUFFER_ATOMIC_DEC_X2_IDXEN
16319 { 257, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #257 = BUFFER_ATOMIC_DEC_X2_IDXEN_RTN
16320 { 258, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #258 = BUFFER_ATOMIC_DEC_X2_OFFEN
16321 { 259, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #259 = BUFFER_ATOMIC_DEC_X2_OFFEN_RTN
16322 { 260, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #260 = BUFFER_ATOMIC_DEC_X2_OFFSET
16323 { 261, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #261 = BUFFER_ATOMIC_DEC_X2_OFFSET_RTN
16324 { 262, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #262 = BUFFER_ATOMIC_FCMPSWAP_ADDR64
16325 { 263, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #263 = BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN
16326 { 264, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #264 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN
16327 { 265, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #265 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN
16328 { 266, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #266 = BUFFER_ATOMIC_FCMPSWAP_IDXEN
16329 { 267, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #267 = BUFFER_ATOMIC_FCMPSWAP_IDXEN_RTN
16330 { 268, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #268 = BUFFER_ATOMIC_FCMPSWAP_OFFEN
16331 { 269, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #269 = BUFFER_ATOMIC_FCMPSWAP_OFFEN_RTN
16332 { 270, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #270 = BUFFER_ATOMIC_FCMPSWAP_OFFSET
16333 { 271, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #271 = BUFFER_ATOMIC_FCMPSWAP_OFFSET_RTN
16334 { 272, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #272 = BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64
16335 { 273, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #273 = BUFFER_ATOMIC_FCMPSWAP_X2_ADDR64_RTN
16336 { 274, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #274 = BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN
16337 { 275, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #275 = BUFFER_ATOMIC_FCMPSWAP_X2_BOTHEN_RTN
16338 { 276, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #276 = BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN
16339 { 277, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #277 = BUFFER_ATOMIC_FCMPSWAP_X2_IDXEN_RTN
16340 { 278, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #278 = BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN
16341 { 279, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #279 = BUFFER_ATOMIC_FCMPSWAP_X2_OFFEN_RTN
16342 { 280, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #280 = BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET
16343 { 281, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #281 = BUFFER_ATOMIC_FCMPSWAP_X2_OFFSET_RTN
16344 { 282, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #282 = BUFFER_ATOMIC_FMAX_ADDR64
16345 { 283, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #283 = BUFFER_ATOMIC_FMAX_ADDR64_RTN
16346 { 284, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #284 = BUFFER_ATOMIC_FMAX_BOTHEN
16347 { 285, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #285 = BUFFER_ATOMIC_FMAX_BOTHEN_RTN
16348 { 286, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #286 = BUFFER_ATOMIC_FMAX_IDXEN
16349 { 287, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #287 = BUFFER_ATOMIC_FMAX_IDXEN_RTN
16350 { 288, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #288 = BUFFER_ATOMIC_FMAX_OFFEN
16351 { 289, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #289 = BUFFER_ATOMIC_FMAX_OFFEN_RTN
16352 { 290, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #290 = BUFFER_ATOMIC_FMAX_OFFSET
16353 { 291, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #291 = BUFFER_ATOMIC_FMAX_OFFSET_RTN
16354 { 292, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #292 = BUFFER_ATOMIC_FMAX_X2_ADDR64
16355 { 293, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #293 = BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN
16356 { 294, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #294 = BUFFER_ATOMIC_FMAX_X2_BOTHEN
16357 { 295, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #295 = BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN
16358 { 296, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #296 = BUFFER_ATOMIC_FMAX_X2_IDXEN
16359 { 297, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #297 = BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN
16360 { 298, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #298 = BUFFER_ATOMIC_FMAX_X2_OFFEN
16361 { 299, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #299 = BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN
16362 { 300, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #300 = BUFFER_ATOMIC_FMAX_X2_OFFSET
16363 { 301, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #301 = BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN
16364 { 302, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #302 = BUFFER_ATOMIC_FMIN_ADDR64
16365 { 303, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #303 = BUFFER_ATOMIC_FMIN_ADDR64_RTN
16366 { 304, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #304 = BUFFER_ATOMIC_FMIN_BOTHEN
16367 { 305, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #305 = BUFFER_ATOMIC_FMIN_BOTHEN_RTN
16368 { 306, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #306 = BUFFER_ATOMIC_FMIN_IDXEN
16369 { 307, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #307 = BUFFER_ATOMIC_FMIN_IDXEN_RTN
16370 { 308, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #308 = BUFFER_ATOMIC_FMIN_OFFEN
16371 { 309, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #309 = BUFFER_ATOMIC_FMIN_OFFEN_RTN
16372 { 310, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #310 = BUFFER_ATOMIC_FMIN_OFFSET
16373 { 311, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #311 = BUFFER_ATOMIC_FMIN_OFFSET_RTN
16374 { 312, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #312 = BUFFER_ATOMIC_FMIN_X2_ADDR64
16375 { 313, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #313 = BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN
16376 { 314, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #314 = BUFFER_ATOMIC_FMIN_X2_BOTHEN
16377 { 315, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #315 = BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN
16378 { 316, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #316 = BUFFER_ATOMIC_FMIN_X2_IDXEN
16379 { 317, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #317 = BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN
16380 { 318, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #318 = BUFFER_ATOMIC_FMIN_X2_OFFEN
16381 { 319, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #319 = BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN
16382 { 320, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #320 = BUFFER_ATOMIC_FMIN_X2_OFFSET
16383 { 321, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #321 = BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN
16384 { 322, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #322 = BUFFER_ATOMIC_INC_ADDR64
16385 { 323, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #323 = BUFFER_ATOMIC_INC_ADDR64_RTN
16386 { 324, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #324 = BUFFER_ATOMIC_INC_BOTHEN
16387 { 325, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #325 = BUFFER_ATOMIC_INC_BOTHEN_RTN
16388 { 326, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #326 = BUFFER_ATOMIC_INC_IDXEN
16389 { 327, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #327 = BUFFER_ATOMIC_INC_IDXEN_RTN
16390 { 328, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #328 = BUFFER_ATOMIC_INC_OFFEN
16391 { 329, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #329 = BUFFER_ATOMIC_INC_OFFEN_RTN
16392 { 330, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #330 = BUFFER_ATOMIC_INC_OFFSET
16393 { 331, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #331 = BUFFER_ATOMIC_INC_OFFSET_RTN
16394 { 332, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #332 = BUFFER_ATOMIC_INC_X2_ADDR64
16395 { 333, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #333 = BUFFER_ATOMIC_INC_X2_ADDR64_RTN
16396 { 334, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #334 = BUFFER_ATOMIC_INC_X2_BOTHEN
16397 { 335, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #335 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN
16398 { 336, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #336 = BUFFER_ATOMIC_INC_X2_IDXEN
16399 { 337, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #337 = BUFFER_ATOMIC_INC_X2_IDXEN_RTN
16400 { 338, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #338 = BUFFER_ATOMIC_INC_X2_OFFEN
16401 { 339, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #339 = BUFFER_ATOMIC_INC_X2_OFFEN_RTN
16402 { 340, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #340 = BUFFER_ATOMIC_INC_X2_OFFSET
16403 { 341, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #341 = BUFFER_ATOMIC_INC_X2_OFFSET_RTN
16404 { 342, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #342 = BUFFER_ATOMIC_OR_ADDR64
16405 { 343, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #343 = BUFFER_ATOMIC_OR_ADDR64_RTN
16406 { 344, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #344 = BUFFER_ATOMIC_OR_BOTHEN
16407 { 345, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #345 = BUFFER_ATOMIC_OR_BOTHEN_RTN
16408 { 346, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #346 = BUFFER_ATOMIC_OR_IDXEN
16409 { 347, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #347 = BUFFER_ATOMIC_OR_IDXEN_RTN
16410 { 348, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #348 = BUFFER_ATOMIC_OR_OFFEN
16411 { 349, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #349 = BUFFER_ATOMIC_OR_OFFEN_RTN
16412 { 350, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #350 = BUFFER_ATOMIC_OR_OFFSET
16413 { 351, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #351 = BUFFER_ATOMIC_OR_OFFSET_RTN
16414 { 352, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #352 = BUFFER_ATOMIC_OR_X2_ADDR64
16415 { 353, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #353 = BUFFER_ATOMIC_OR_X2_ADDR64_RTN
16416 { 354, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #354 = BUFFER_ATOMIC_OR_X2_BOTHEN
16417 { 355, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #355 = BUFFER_ATOMIC_OR_X2_BOTHEN_RTN
16418 { 356, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #356 = BUFFER_ATOMIC_OR_X2_IDXEN
16419 { 357, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #357 = BUFFER_ATOMIC_OR_X2_IDXEN_RTN
16420 { 358, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #358 = BUFFER_ATOMIC_OR_X2_OFFEN
16421 { 359, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #359 = BUFFER_ATOMIC_OR_X2_OFFEN_RTN
16422 { 360, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #360 = BUFFER_ATOMIC_OR_X2_OFFSET
16423 { 361, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #361 = BUFFER_ATOMIC_OR_X2_OFFSET_RTN
16424 { 362, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #362 = BUFFER_ATOMIC_PK_ADD_F16_ADDR64
16425 { 363, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #363 = BUFFER_ATOMIC_PK_ADD_F16_BOTHEN
16426 { 364, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #364 = BUFFER_ATOMIC_PK_ADD_F16_IDXEN
16427 { 365, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #365 = BUFFER_ATOMIC_PK_ADD_F16_OFFEN
16428 { 366, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #366 = BUFFER_ATOMIC_PK_ADD_F16_OFFSET
16429 { 367, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #367 = BUFFER_ATOMIC_SMAX_ADDR64
16430 { 368, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #368 = BUFFER_ATOMIC_SMAX_ADDR64_RTN
16431 { 369, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #369 = BUFFER_ATOMIC_SMAX_BOTHEN
16432 { 370, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #370 = BUFFER_ATOMIC_SMAX_BOTHEN_RTN
16433 { 371, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #371 = BUFFER_ATOMIC_SMAX_IDXEN
16434 { 372, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #372 = BUFFER_ATOMIC_SMAX_IDXEN_RTN
16435 { 373, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #373 = BUFFER_ATOMIC_SMAX_OFFEN
16436 { 374, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #374 = BUFFER_ATOMIC_SMAX_OFFEN_RTN
16437 { 375, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #375 = BUFFER_ATOMIC_SMAX_OFFSET
16438 { 376, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #376 = BUFFER_ATOMIC_SMAX_OFFSET_RTN
16439 { 377, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #377 = BUFFER_ATOMIC_SMAX_X2_ADDR64
16440 { 378, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #378 = BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN
16441 { 379, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #379 = BUFFER_ATOMIC_SMAX_X2_BOTHEN
16442 { 380, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #380 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN
16443 { 381, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #381 = BUFFER_ATOMIC_SMAX_X2_IDXEN
16444 { 382, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #382 = BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN
16445 { 383, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #383 = BUFFER_ATOMIC_SMAX_X2_OFFEN
16446 { 384, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #384 = BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN
16447 { 385, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #385 = BUFFER_ATOMIC_SMAX_X2_OFFSET
16448 { 386, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #386 = BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN
16449 { 387, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #387 = BUFFER_ATOMIC_SMIN_ADDR64
16450 { 388, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #388 = BUFFER_ATOMIC_SMIN_ADDR64_RTN
16451 { 389, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #389 = BUFFER_ATOMIC_SMIN_BOTHEN
16452 { 390, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #390 = BUFFER_ATOMIC_SMIN_BOTHEN_RTN
16453 { 391, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #391 = BUFFER_ATOMIC_SMIN_IDXEN
16454 { 392, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #392 = BUFFER_ATOMIC_SMIN_IDXEN_RTN
16455 { 393, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #393 = BUFFER_ATOMIC_SMIN_OFFEN
16456 { 394, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #394 = BUFFER_ATOMIC_SMIN_OFFEN_RTN
16457 { 395, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #395 = BUFFER_ATOMIC_SMIN_OFFSET
16458 { 396, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #396 = BUFFER_ATOMIC_SMIN_OFFSET_RTN
16459 { 397, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #397 = BUFFER_ATOMIC_SMIN_X2_ADDR64
16460 { 398, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #398 = BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN
16461 { 399, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #399 = BUFFER_ATOMIC_SMIN_X2_BOTHEN
16462 { 400, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #400 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN
16463 { 401, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #401 = BUFFER_ATOMIC_SMIN_X2_IDXEN
16464 { 402, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #402 = BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN
16465 { 403, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #403 = BUFFER_ATOMIC_SMIN_X2_OFFEN
16466 { 404, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #404 = BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN
16467 { 405, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #405 = BUFFER_ATOMIC_SMIN_X2_OFFSET
16468 { 406, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #406 = BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN
16469 { 407, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #407 = BUFFER_ATOMIC_SUB_ADDR64
16470 { 408, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #408 = BUFFER_ATOMIC_SUB_ADDR64_RTN
16471 { 409, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #409 = BUFFER_ATOMIC_SUB_BOTHEN
16472 { 410, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #410 = BUFFER_ATOMIC_SUB_BOTHEN_RTN
16473 { 411, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #411 = BUFFER_ATOMIC_SUB_IDXEN
16474 { 412, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #412 = BUFFER_ATOMIC_SUB_IDXEN_RTN
16475 { 413, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #413 = BUFFER_ATOMIC_SUB_OFFEN
16476 { 414, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #414 = BUFFER_ATOMIC_SUB_OFFEN_RTN
16477 { 415, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #415 = BUFFER_ATOMIC_SUB_OFFSET
16478 { 416, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #416 = BUFFER_ATOMIC_SUB_OFFSET_RTN
16479 { 417, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #417 = BUFFER_ATOMIC_SUB_X2_ADDR64
16480 { 418, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #418 = BUFFER_ATOMIC_SUB_X2_ADDR64_RTN
16481 { 419, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #419 = BUFFER_ATOMIC_SUB_X2_BOTHEN
16482 { 420, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #420 = BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN
16483 { 421, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #421 = BUFFER_ATOMIC_SUB_X2_IDXEN
16484 { 422, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #422 = BUFFER_ATOMIC_SUB_X2_IDXEN_RTN
16485 { 423, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #423 = BUFFER_ATOMIC_SUB_X2_OFFEN
16486 { 424, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #424 = BUFFER_ATOMIC_SUB_X2_OFFEN_RTN
16487 { 425, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #425 = BUFFER_ATOMIC_SUB_X2_OFFSET
16488 { 426, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #426 = BUFFER_ATOMIC_SUB_X2_OFFSET_RTN
16489 { 427, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #427 = BUFFER_ATOMIC_SWAP_ADDR64
16490 { 428, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #428 = BUFFER_ATOMIC_SWAP_ADDR64_RTN
16491 { 429, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #429 = BUFFER_ATOMIC_SWAP_BOTHEN
16492 { 430, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #430 = BUFFER_ATOMIC_SWAP_BOTHEN_RTN
16493 { 431, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #431 = BUFFER_ATOMIC_SWAP_IDXEN
16494 { 432, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #432 = BUFFER_ATOMIC_SWAP_IDXEN_RTN
16495 { 433, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #433 = BUFFER_ATOMIC_SWAP_OFFEN
16496 { 434, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #434 = BUFFER_ATOMIC_SWAP_OFFEN_RTN
16497 { 435, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #435 = BUFFER_ATOMIC_SWAP_OFFSET
16498 { 436, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #436 = BUFFER_ATOMIC_SWAP_OFFSET_RTN
16499 { 437, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #437 = BUFFER_ATOMIC_SWAP_X2_ADDR64
16500 { 438, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #438 = BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN
16501 { 439, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #439 = BUFFER_ATOMIC_SWAP_X2_BOTHEN
16502 { 440, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #440 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN
16503 { 441, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #441 = BUFFER_ATOMIC_SWAP_X2_IDXEN
16504 { 442, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #442 = BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN
16505 { 443, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #443 = BUFFER_ATOMIC_SWAP_X2_OFFEN
16506 { 444, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #444 = BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN
16507 { 445, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #445 = BUFFER_ATOMIC_SWAP_X2_OFFSET
16508 { 446, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #446 = BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN
16509 { 447, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #447 = BUFFER_ATOMIC_UMAX_ADDR64
16510 { 448, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #448 = BUFFER_ATOMIC_UMAX_ADDR64_RTN
16511 { 449, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #449 = BUFFER_ATOMIC_UMAX_BOTHEN
16512 { 450, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #450 = BUFFER_ATOMIC_UMAX_BOTHEN_RTN
16513 { 451, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #451 = BUFFER_ATOMIC_UMAX_IDXEN
16514 { 452, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #452 = BUFFER_ATOMIC_UMAX_IDXEN_RTN
16515 { 453, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #453 = BUFFER_ATOMIC_UMAX_OFFEN
16516 { 454, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #454 = BUFFER_ATOMIC_UMAX_OFFEN_RTN
16517 { 455, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #455 = BUFFER_ATOMIC_UMAX_OFFSET
16518 { 456, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #456 = BUFFER_ATOMIC_UMAX_OFFSET_RTN
16519 { 457, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #457 = BUFFER_ATOMIC_UMAX_X2_ADDR64
16520 { 458, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #458 = BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN
16521 { 459, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #459 = BUFFER_ATOMIC_UMAX_X2_BOTHEN
16522 { 460, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #460 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN
16523 { 461, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #461 = BUFFER_ATOMIC_UMAX_X2_IDXEN
16524 { 462, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #462 = BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN
16525 { 463, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #463 = BUFFER_ATOMIC_UMAX_X2_OFFEN
16526 { 464, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #464 = BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN
16527 { 465, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #465 = BUFFER_ATOMIC_UMAX_X2_OFFSET
16528 { 466, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #466 = BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN
16529 { 467, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #467 = BUFFER_ATOMIC_UMIN_ADDR64
16530 { 468, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #468 = BUFFER_ATOMIC_UMIN_ADDR64_RTN
16531 { 469, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #469 = BUFFER_ATOMIC_UMIN_BOTHEN
16532 { 470, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #470 = BUFFER_ATOMIC_UMIN_BOTHEN_RTN
16533 { 471, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #471 = BUFFER_ATOMIC_UMIN_IDXEN
16534 { 472, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #472 = BUFFER_ATOMIC_UMIN_IDXEN_RTN
16535 { 473, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #473 = BUFFER_ATOMIC_UMIN_OFFEN
16536 { 474, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #474 = BUFFER_ATOMIC_UMIN_OFFEN_RTN
16537 { 475, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #475 = BUFFER_ATOMIC_UMIN_OFFSET
16538 { 476, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #476 = BUFFER_ATOMIC_UMIN_OFFSET_RTN
16539 { 477, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #477 = BUFFER_ATOMIC_UMIN_X2_ADDR64
16540 { 478, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #478 = BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN
16541 { 479, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #479 = BUFFER_ATOMIC_UMIN_X2_BOTHEN
16542 { 480, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #480 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN
16543 { 481, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #481 = BUFFER_ATOMIC_UMIN_X2_IDXEN
16544 { 482, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #482 = BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN
16545 { 483, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #483 = BUFFER_ATOMIC_UMIN_X2_OFFEN
16546 { 484, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #484 = BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN
16547 { 485, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #485 = BUFFER_ATOMIC_UMIN_X2_OFFSET
16548 { 486, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #486 = BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN
16549 { 487, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #487 = BUFFER_ATOMIC_XOR_ADDR64
16550 { 488, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #488 = BUFFER_ATOMIC_XOR_ADDR64_RTN
16551 { 489, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #489 = BUFFER_ATOMIC_XOR_BOTHEN
16552 { 490, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #490 = BUFFER_ATOMIC_XOR_BOTHEN_RTN
16553 { 491, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #491 = BUFFER_ATOMIC_XOR_IDXEN
16554 { 492, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #492 = BUFFER_ATOMIC_XOR_IDXEN_RTN
16555 { 493, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #493 = BUFFER_ATOMIC_XOR_OFFEN
16556 { 494, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #494 = BUFFER_ATOMIC_XOR_OFFEN_RTN
16557 { 495, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #495 = BUFFER_ATOMIC_XOR_OFFSET
16558 { 496, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #496 = BUFFER_ATOMIC_XOR_OFFSET_RTN
16559 { 497, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #497 = BUFFER_ATOMIC_XOR_X2_ADDR64
16560 { 498, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #498 = BUFFER_ATOMIC_XOR_X2_ADDR64_RTN
16561 { 499, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #499 = BUFFER_ATOMIC_XOR_X2_BOTHEN
16562 { 500, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #500 = BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN
16563 { 501, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #501 = BUFFER_ATOMIC_XOR_X2_IDXEN
16564 { 502, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #502 = BUFFER_ATOMIC_XOR_X2_IDXEN_RTN
16565 { 503, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #503 = BUFFER_ATOMIC_XOR_X2_OFFEN
16566 { 504, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #504 = BUFFER_ATOMIC_XOR_X2_OFFEN_RTN
16567 { 505, 5, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #505 = BUFFER_ATOMIC_XOR_X2_OFFSET
16568 { 506, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #506 = BUFFER_ATOMIC_XOR_X2_OFFSET_RTN
16569 { 507, 0, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x300010000ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #507 = BUFFER_GL0_INV
16570 { 508, 0, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x300010000ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #508 = BUFFER_GL1_INV
16571 { 509, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #509 = BUFFER_LOAD_DWORDX2_ADDR64
16572 { 510, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #510 = BUFFER_LOAD_DWORDX2_BOTHEN
16573 { 511, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #511 = BUFFER_LOAD_DWORDX2_BOTHEN_exact
16574 { 512, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #512 = BUFFER_LOAD_DWORDX2_IDXEN
16575 { 513, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #513 = BUFFER_LOAD_DWORDX2_IDXEN_exact
16576 { 514, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #514 = BUFFER_LOAD_DWORDX2_LDS_ADDR64
16577 { 515, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #515 = BUFFER_LOAD_DWORDX2_LDS_BOTHEN
16578 { 516, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #516 = BUFFER_LOAD_DWORDX2_LDS_BOTHEN_exact
16579 { 517, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #517 = BUFFER_LOAD_DWORDX2_LDS_IDXEN
16580 { 518, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #518 = BUFFER_LOAD_DWORDX2_LDS_IDXEN_exact
16581 { 519, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #519 = BUFFER_LOAD_DWORDX2_LDS_OFFEN
16582 { 520, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #520 = BUFFER_LOAD_DWORDX2_LDS_OFFEN_exact
16583 { 521, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #521 = BUFFER_LOAD_DWORDX2_LDS_OFFSET
16584 { 522, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #522 = BUFFER_LOAD_DWORDX2_LDS_OFFSET_exact
16585 { 523, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #523 = BUFFER_LOAD_DWORDX2_OFFEN
16586 { 524, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #524 = BUFFER_LOAD_DWORDX2_OFFEN_exact
16587 { 525, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #525 = BUFFER_LOAD_DWORDX2_OFFSET
16588 { 526, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #526 = BUFFER_LOAD_DWORDX2_OFFSET_exact
16589 { 527, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #527 = BUFFER_LOAD_DWORDX3_ADDR64
16590 { 528, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #528 = BUFFER_LOAD_DWORDX3_BOTHEN
16591 { 529, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #529 = BUFFER_LOAD_DWORDX3_BOTHEN_exact
16592 { 530, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #530 = BUFFER_LOAD_DWORDX3_IDXEN
16593 { 531, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #531 = BUFFER_LOAD_DWORDX3_IDXEN_exact
16594 { 532, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #532 = BUFFER_LOAD_DWORDX3_LDS_ADDR64
16595 { 533, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #533 = BUFFER_LOAD_DWORDX3_LDS_BOTHEN
16596 { 534, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #534 = BUFFER_LOAD_DWORDX3_LDS_BOTHEN_exact
16597 { 535, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #535 = BUFFER_LOAD_DWORDX3_LDS_IDXEN
16598 { 536, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #536 = BUFFER_LOAD_DWORDX3_LDS_IDXEN_exact
16599 { 537, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #537 = BUFFER_LOAD_DWORDX3_LDS_OFFEN
16600 { 538, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #538 = BUFFER_LOAD_DWORDX3_LDS_OFFEN_exact
16601 { 539, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #539 = BUFFER_LOAD_DWORDX3_LDS_OFFSET
16602 { 540, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #540 = BUFFER_LOAD_DWORDX3_LDS_OFFSET_exact
16603 { 541, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #541 = BUFFER_LOAD_DWORDX3_OFFEN
16604 { 542, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #542 = BUFFER_LOAD_DWORDX3_OFFEN_exact
16605 { 543, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #543 = BUFFER_LOAD_DWORDX3_OFFSET
16606 { 544, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #544 = BUFFER_LOAD_DWORDX3_OFFSET_exact
16607 { 545, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #545 = BUFFER_LOAD_DWORDX4_ADDR64
16608 { 546, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #546 = BUFFER_LOAD_DWORDX4_BOTHEN
16609 { 547, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #547 = BUFFER_LOAD_DWORDX4_BOTHEN_exact
16610 { 548, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #548 = BUFFER_LOAD_DWORDX4_IDXEN
16611 { 549, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #549 = BUFFER_LOAD_DWORDX4_IDXEN_exact
16612 { 550, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #550 = BUFFER_LOAD_DWORDX4_LDS_ADDR64
16613 { 551, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #551 = BUFFER_LOAD_DWORDX4_LDS_BOTHEN
16614 { 552, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #552 = BUFFER_LOAD_DWORDX4_LDS_BOTHEN_exact
16615 { 553, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #553 = BUFFER_LOAD_DWORDX4_LDS_IDXEN
16616 { 554, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #554 = BUFFER_LOAD_DWORDX4_LDS_IDXEN_exact
16617 { 555, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #555 = BUFFER_LOAD_DWORDX4_LDS_OFFEN
16618 { 556, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #556 = BUFFER_LOAD_DWORDX4_LDS_OFFEN_exact
16619 { 557, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #557 = BUFFER_LOAD_DWORDX4_LDS_OFFSET
16620 { 558, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #558 = BUFFER_LOAD_DWORDX4_LDS_OFFSET_exact
16621 { 559, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #559 = BUFFER_LOAD_DWORDX4_OFFEN
16622 { 560, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #560 = BUFFER_LOAD_DWORDX4_OFFEN_exact
16623 { 561, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #561 = BUFFER_LOAD_DWORDX4_OFFSET
16624 { 562, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #562 = BUFFER_LOAD_DWORDX4_OFFSET_exact
16625 { 563, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #563 = BUFFER_LOAD_DWORD_ADDR64
16626 { 564, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #564 = BUFFER_LOAD_DWORD_BOTHEN
16627 { 565, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #565 = BUFFER_LOAD_DWORD_BOTHEN_exact
16628 { 566, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #566 = BUFFER_LOAD_DWORD_IDXEN
16629 { 567, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #567 = BUFFER_LOAD_DWORD_IDXEN_exact
16630 { 568, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #568 = BUFFER_LOAD_DWORD_LDS_ADDR64
16631 { 569, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #569 = BUFFER_LOAD_DWORD_LDS_BOTHEN
16632 { 570, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #570 = BUFFER_LOAD_DWORD_LDS_BOTHEN_exact
16633 { 571, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #571 = BUFFER_LOAD_DWORD_LDS_IDXEN
16634 { 572, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #572 = BUFFER_LOAD_DWORD_LDS_IDXEN_exact
16635 { 573, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #573 = BUFFER_LOAD_DWORD_LDS_OFFEN
16636 { 574, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #574 = BUFFER_LOAD_DWORD_LDS_OFFEN_exact
16637 { 575, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #575 = BUFFER_LOAD_DWORD_LDS_OFFSET
16638 { 576, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #576 = BUFFER_LOAD_DWORD_LDS_OFFSET_exact
16639 { 577, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #577 = BUFFER_LOAD_DWORD_OFFEN
16640 { 578, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #578 = BUFFER_LOAD_DWORD_OFFEN_exact
16641 { 579, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #579 = BUFFER_LOAD_DWORD_OFFSET
16642 { 580, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #580 = BUFFER_LOAD_DWORD_OFFSET_exact
16643 { 581, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #581 = BUFFER_LOAD_FORMAT_D16_HI_X_ADDR64
16644 { 582, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #582 = BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN
16645 { 583, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #583 = BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_exact
16646 { 584, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #584 = BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN
16647 { 585, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #585 = BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_exact
16648 { 586, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #586 = BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN
16649 { 587, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #587 = BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_exact
16650 { 588, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #588 = BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET
16651 { 589, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #589 = BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_exact
16652 { 590, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #590 = BUFFER_LOAD_FORMAT_D16_XYZW_ADDR64
16653 { 591, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #591 = BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN
16654 { 592, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #592 = BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_exact
16655 { 593, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #593 = BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN
16656 { 594, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #594 = BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_exact
16657 { 595, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #595 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN
16658 { 596, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #596 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_exact
16659 { 597, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #597 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET
16660 { 598, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #598 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_exact
16661 { 599, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #599 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_ADDR64
16662 { 600, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #600 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN
16663 { 601, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #601 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_exact
16664 { 602, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #602 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN
16665 { 603, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #603 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_exact
16666 { 604, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #604 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN
16667 { 605, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #605 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_exact
16668 { 606, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #606 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET
16669 { 607, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #607 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact
16670 { 608, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #608 = BUFFER_LOAD_FORMAT_D16_XYZ_ADDR64
16671 { 609, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #609 = BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN
16672 { 610, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #610 = BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_exact
16673 { 611, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #611 = BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN
16674 { 612, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #612 = BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_exact
16675 { 613, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #613 = BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN
16676 { 614, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #614 = BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_exact
16677 { 615, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #615 = BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET
16678 { 616, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #616 = BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_exact
16679 { 617, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #617 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_ADDR64
16680 { 618, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #618 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN
16681 { 619, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #619 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_exact
16682 { 620, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #620 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN
16683 { 621, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #621 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_exact
16684 { 622, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #622 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN
16685 { 623, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #623 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_exact
16686 { 624, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #624 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET
16687 { 625, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #625 = BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact
16688 { 626, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #626 = BUFFER_LOAD_FORMAT_D16_XY_ADDR64
16689 { 627, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #627 = BUFFER_LOAD_FORMAT_D16_XY_BOTHEN
16690 { 628, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #628 = BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact
16691 { 629, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #629 = BUFFER_LOAD_FORMAT_D16_XY_IDXEN
16692 { 630, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #630 = BUFFER_LOAD_FORMAT_D16_XY_IDXEN_exact
16693 { 631, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #631 = BUFFER_LOAD_FORMAT_D16_XY_OFFEN
16694 { 632, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #632 = BUFFER_LOAD_FORMAT_D16_XY_OFFEN_exact
16695 { 633, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #633 = BUFFER_LOAD_FORMAT_D16_XY_OFFSET
16696 { 634, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #634 = BUFFER_LOAD_FORMAT_D16_XY_OFFSET_exact
16697 { 635, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #635 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_ADDR64
16698 { 636, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #636 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN
16699 { 637, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #637 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_exact
16700 { 638, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #638 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN
16701 { 639, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #639 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_exact
16702 { 640, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #640 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN
16703 { 641, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #641 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_exact
16704 { 642, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #642 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET
16705 { 643, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #643 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_exact
16706 { 644, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #644 = BUFFER_LOAD_FORMAT_D16_X_ADDR64
16707 { 645, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #645 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN
16708 { 646, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #646 = BUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact
16709 { 647, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #647 = BUFFER_LOAD_FORMAT_D16_X_IDXEN
16710 { 648, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #648 = BUFFER_LOAD_FORMAT_D16_X_IDXEN_exact
16711 { 649, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #649 = BUFFER_LOAD_FORMAT_D16_X_OFFEN
16712 { 650, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #650 = BUFFER_LOAD_FORMAT_D16_X_OFFEN_exact
16713 { 651, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #651 = BUFFER_LOAD_FORMAT_D16_X_OFFSET
16714 { 652, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #652 = BUFFER_LOAD_FORMAT_D16_X_OFFSET_exact
16715 { 653, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #653 = BUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64
16716 { 654, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #654 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN
16717 { 655, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #655 = BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact
16718 { 656, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #656 = BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN
16719 { 657, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #657 = BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_exact
16720 { 658, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #658 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN
16721 { 659, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #659 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_exact
16722 { 660, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #660 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET
16723 { 661, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #661 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_exact
16724 { 662, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #662 = BUFFER_LOAD_FORMAT_XYZW_ADDR64
16725 { 663, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #663 = BUFFER_LOAD_FORMAT_XYZW_BOTHEN
16726 { 664, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #664 = BUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact
16727 { 665, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #665 = BUFFER_LOAD_FORMAT_XYZW_IDXEN
16728 { 666, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #666 = BUFFER_LOAD_FORMAT_XYZW_IDXEN_exact
16729 { 667, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #667 = BUFFER_LOAD_FORMAT_XYZW_OFFEN
16730 { 668, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #668 = BUFFER_LOAD_FORMAT_XYZW_OFFEN_exact
16731 { 669, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #669 = BUFFER_LOAD_FORMAT_XYZW_OFFSET
16732 { 670, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #670 = BUFFER_LOAD_FORMAT_XYZW_OFFSET_exact
16733 { 671, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #671 = BUFFER_LOAD_FORMAT_XYZ_ADDR64
16734 { 672, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #672 = BUFFER_LOAD_FORMAT_XYZ_BOTHEN
16735 { 673, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #673 = BUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact
16736 { 674, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #674 = BUFFER_LOAD_FORMAT_XYZ_IDXEN
16737 { 675, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #675 = BUFFER_LOAD_FORMAT_XYZ_IDXEN_exact
16738 { 676, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #676 = BUFFER_LOAD_FORMAT_XYZ_OFFEN
16739 { 677, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #677 = BUFFER_LOAD_FORMAT_XYZ_OFFEN_exact
16740 { 678, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #678 = BUFFER_LOAD_FORMAT_XYZ_OFFSET
16741 { 679, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #679 = BUFFER_LOAD_FORMAT_XYZ_OFFSET_exact
16742 { 680, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #680 = BUFFER_LOAD_FORMAT_XY_ADDR64
16743 { 681, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #681 = BUFFER_LOAD_FORMAT_XY_BOTHEN
16744 { 682, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #682 = BUFFER_LOAD_FORMAT_XY_BOTHEN_exact
16745 { 683, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #683 = BUFFER_LOAD_FORMAT_XY_IDXEN
16746 { 684, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #684 = BUFFER_LOAD_FORMAT_XY_IDXEN_exact
16747 { 685, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #685 = BUFFER_LOAD_FORMAT_XY_OFFEN
16748 { 686, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #686 = BUFFER_LOAD_FORMAT_XY_OFFEN_exact
16749 { 687, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #687 = BUFFER_LOAD_FORMAT_XY_OFFSET
16750 { 688, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #688 = BUFFER_LOAD_FORMAT_XY_OFFSET_exact
16751 { 689, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #689 = BUFFER_LOAD_FORMAT_X_ADDR64
16752 { 690, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #690 = BUFFER_LOAD_FORMAT_X_BOTHEN
16753 { 691, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #691 = BUFFER_LOAD_FORMAT_X_BOTHEN_exact
16754 { 692, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #692 = BUFFER_LOAD_FORMAT_X_IDXEN
16755 { 693, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #693 = BUFFER_LOAD_FORMAT_X_IDXEN_exact
16756 { 694, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #694 = BUFFER_LOAD_FORMAT_X_LDS_ADDR64
16757 { 695, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #695 = BUFFER_LOAD_FORMAT_X_LDS_BOTHEN
16758 { 696, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #696 = BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_exact
16759 { 697, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #697 = BUFFER_LOAD_FORMAT_X_LDS_IDXEN
16760 { 698, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #698 = BUFFER_LOAD_FORMAT_X_LDS_IDXEN_exact
16761 { 699, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #699 = BUFFER_LOAD_FORMAT_X_LDS_OFFEN
16762 { 700, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #700 = BUFFER_LOAD_FORMAT_X_LDS_OFFEN_exact
16763 { 701, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #701 = BUFFER_LOAD_FORMAT_X_LDS_OFFSET
16764 { 702, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #702 = BUFFER_LOAD_FORMAT_X_LDS_OFFSET_exact
16765 { 703, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #703 = BUFFER_LOAD_FORMAT_X_OFFEN
16766 { 704, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #704 = BUFFER_LOAD_FORMAT_X_OFFEN_exact
16767 { 705, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #705 = BUFFER_LOAD_FORMAT_X_OFFSET
16768 { 706, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #706 = BUFFER_LOAD_FORMAT_X_OFFSET_exact
16769 { 707, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #707 = BUFFER_LOAD_SBYTE_ADDR64
16770 { 708, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #708 = BUFFER_LOAD_SBYTE_BOTHEN
16771 { 709, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #709 = BUFFER_LOAD_SBYTE_BOTHEN_exact
16772 { 710, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #710 = BUFFER_LOAD_SBYTE_D16_ADDR64
16773 { 711, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #711 = BUFFER_LOAD_SBYTE_D16_BOTHEN
16774 { 712, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #712 = BUFFER_LOAD_SBYTE_D16_BOTHEN_exact
16775 { 713, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #713 = BUFFER_LOAD_SBYTE_D16_HI_ADDR64
16776 { 714, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #714 = BUFFER_LOAD_SBYTE_D16_HI_BOTHEN
16777 { 715, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #715 = BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_exact
16778 { 716, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #716 = BUFFER_LOAD_SBYTE_D16_HI_IDXEN
16779 { 717, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #717 = BUFFER_LOAD_SBYTE_D16_HI_IDXEN_exact
16780 { 718, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #718 = BUFFER_LOAD_SBYTE_D16_HI_OFFEN
16781 { 719, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #719 = BUFFER_LOAD_SBYTE_D16_HI_OFFEN_exact
16782 { 720, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #720 = BUFFER_LOAD_SBYTE_D16_HI_OFFSET
16783 { 721, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #721 = BUFFER_LOAD_SBYTE_D16_HI_OFFSET_exact
16784 { 722, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #722 = BUFFER_LOAD_SBYTE_D16_IDXEN
16785 { 723, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #723 = BUFFER_LOAD_SBYTE_D16_IDXEN_exact
16786 { 724, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #724 = BUFFER_LOAD_SBYTE_D16_OFFEN
16787 { 725, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #725 = BUFFER_LOAD_SBYTE_D16_OFFEN_exact
16788 { 726, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #726 = BUFFER_LOAD_SBYTE_D16_OFFSET
16789 { 727, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #727 = BUFFER_LOAD_SBYTE_D16_OFFSET_exact
16790 { 728, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #728 = BUFFER_LOAD_SBYTE_IDXEN
16791 { 729, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #729 = BUFFER_LOAD_SBYTE_IDXEN_exact
16792 { 730, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #730 = BUFFER_LOAD_SBYTE_LDS_ADDR64
16793 { 731, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #731 = BUFFER_LOAD_SBYTE_LDS_BOTHEN
16794 { 732, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #732 = BUFFER_LOAD_SBYTE_LDS_BOTHEN_exact
16795 { 733, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #733 = BUFFER_LOAD_SBYTE_LDS_IDXEN
16796 { 734, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #734 = BUFFER_LOAD_SBYTE_LDS_IDXEN_exact
16797 { 735, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #735 = BUFFER_LOAD_SBYTE_LDS_OFFEN
16798 { 736, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #736 = BUFFER_LOAD_SBYTE_LDS_OFFEN_exact
16799 { 737, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #737 = BUFFER_LOAD_SBYTE_LDS_OFFSET
16800 { 738, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #738 = BUFFER_LOAD_SBYTE_LDS_OFFSET_exact
16801 { 739, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #739 = BUFFER_LOAD_SBYTE_OFFEN
16802 { 740, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #740 = BUFFER_LOAD_SBYTE_OFFEN_exact
16803 { 741, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #741 = BUFFER_LOAD_SBYTE_OFFSET
16804 { 742, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #742 = BUFFER_LOAD_SBYTE_OFFSET_exact
16805 { 743, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #743 = BUFFER_LOAD_SHORT_D16_ADDR64
16806 { 744, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #744 = BUFFER_LOAD_SHORT_D16_BOTHEN
16807 { 745, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #745 = BUFFER_LOAD_SHORT_D16_BOTHEN_exact
16808 { 746, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #746 = BUFFER_LOAD_SHORT_D16_HI_ADDR64
16809 { 747, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #747 = BUFFER_LOAD_SHORT_D16_HI_BOTHEN
16810 { 748, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #748 = BUFFER_LOAD_SHORT_D16_HI_BOTHEN_exact
16811 { 749, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #749 = BUFFER_LOAD_SHORT_D16_HI_IDXEN
16812 { 750, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #750 = BUFFER_LOAD_SHORT_D16_HI_IDXEN_exact
16813 { 751, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #751 = BUFFER_LOAD_SHORT_D16_HI_OFFEN
16814 { 752, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #752 = BUFFER_LOAD_SHORT_D16_HI_OFFEN_exact
16815 { 753, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #753 = BUFFER_LOAD_SHORT_D16_HI_OFFSET
16816 { 754, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #754 = BUFFER_LOAD_SHORT_D16_HI_OFFSET_exact
16817 { 755, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #755 = BUFFER_LOAD_SHORT_D16_IDXEN
16818 { 756, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #756 = BUFFER_LOAD_SHORT_D16_IDXEN_exact
16819 { 757, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #757 = BUFFER_LOAD_SHORT_D16_OFFEN
16820 { 758, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #758 = BUFFER_LOAD_SHORT_D16_OFFEN_exact
16821 { 759, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #759 = BUFFER_LOAD_SHORT_D16_OFFSET
16822 { 760, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #760 = BUFFER_LOAD_SHORT_D16_OFFSET_exact
16823 { 761, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #761 = BUFFER_LOAD_SSHORT_ADDR64
16824 { 762, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #762 = BUFFER_LOAD_SSHORT_BOTHEN
16825 { 763, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #763 = BUFFER_LOAD_SSHORT_BOTHEN_exact
16826 { 764, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #764 = BUFFER_LOAD_SSHORT_IDXEN
16827 { 765, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #765 = BUFFER_LOAD_SSHORT_IDXEN_exact
16828 { 766, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #766 = BUFFER_LOAD_SSHORT_LDS_ADDR64
16829 { 767, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #767 = BUFFER_LOAD_SSHORT_LDS_BOTHEN
16830 { 768, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #768 = BUFFER_LOAD_SSHORT_LDS_BOTHEN_exact
16831 { 769, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #769 = BUFFER_LOAD_SSHORT_LDS_IDXEN
16832 { 770, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #770 = BUFFER_LOAD_SSHORT_LDS_IDXEN_exact
16833 { 771, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #771 = BUFFER_LOAD_SSHORT_LDS_OFFEN
16834 { 772, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #772 = BUFFER_LOAD_SSHORT_LDS_OFFEN_exact
16835 { 773, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #773 = BUFFER_LOAD_SSHORT_LDS_OFFSET
16836 { 774, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #774 = BUFFER_LOAD_SSHORT_LDS_OFFSET_exact
16837 { 775, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #775 = BUFFER_LOAD_SSHORT_OFFEN
16838 { 776, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #776 = BUFFER_LOAD_SSHORT_OFFEN_exact
16839 { 777, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #777 = BUFFER_LOAD_SSHORT_OFFSET
16840 { 778, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #778 = BUFFER_LOAD_SSHORT_OFFSET_exact
16841 { 779, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #779 = BUFFER_LOAD_UBYTE_ADDR64
16842 { 780, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #780 = BUFFER_LOAD_UBYTE_BOTHEN
16843 { 781, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #781 = BUFFER_LOAD_UBYTE_BOTHEN_exact
16844 { 782, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #782 = BUFFER_LOAD_UBYTE_D16_ADDR64
16845 { 783, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #783 = BUFFER_LOAD_UBYTE_D16_BOTHEN
16846 { 784, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #784 = BUFFER_LOAD_UBYTE_D16_BOTHEN_exact
16847 { 785, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #785 = BUFFER_LOAD_UBYTE_D16_HI_ADDR64
16848 { 786, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #786 = BUFFER_LOAD_UBYTE_D16_HI_BOTHEN
16849 { 787, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #787 = BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_exact
16850 { 788, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #788 = BUFFER_LOAD_UBYTE_D16_HI_IDXEN
16851 { 789, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #789 = BUFFER_LOAD_UBYTE_D16_HI_IDXEN_exact
16852 { 790, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #790 = BUFFER_LOAD_UBYTE_D16_HI_OFFEN
16853 { 791, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #791 = BUFFER_LOAD_UBYTE_D16_HI_OFFEN_exact
16854 { 792, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #792 = BUFFER_LOAD_UBYTE_D16_HI_OFFSET
16855 { 793, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #793 = BUFFER_LOAD_UBYTE_D16_HI_OFFSET_exact
16856 { 794, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #794 = BUFFER_LOAD_UBYTE_D16_IDXEN
16857 { 795, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #795 = BUFFER_LOAD_UBYTE_D16_IDXEN_exact
16858 { 796, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #796 = BUFFER_LOAD_UBYTE_D16_OFFEN
16859 { 797, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #797 = BUFFER_LOAD_UBYTE_D16_OFFEN_exact
16860 { 798, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #798 = BUFFER_LOAD_UBYTE_D16_OFFSET
16861 { 799, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #799 = BUFFER_LOAD_UBYTE_D16_OFFSET_exact
16862 { 800, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #800 = BUFFER_LOAD_UBYTE_IDXEN
16863 { 801, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #801 = BUFFER_LOAD_UBYTE_IDXEN_exact
16864 { 802, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #802 = BUFFER_LOAD_UBYTE_LDS_ADDR64
16865 { 803, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #803 = BUFFER_LOAD_UBYTE_LDS_BOTHEN
16866 { 804, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #804 = BUFFER_LOAD_UBYTE_LDS_BOTHEN_exact
16867 { 805, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #805 = BUFFER_LOAD_UBYTE_LDS_IDXEN
16868 { 806, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #806 = BUFFER_LOAD_UBYTE_LDS_IDXEN_exact
16869 { 807, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #807 = BUFFER_LOAD_UBYTE_LDS_OFFEN
16870 { 808, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #808 = BUFFER_LOAD_UBYTE_LDS_OFFEN_exact
16871 { 809, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #809 = BUFFER_LOAD_UBYTE_LDS_OFFSET
16872 { 810, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #810 = BUFFER_LOAD_UBYTE_LDS_OFFSET_exact
16873 { 811, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #811 = BUFFER_LOAD_UBYTE_OFFEN
16874 { 812, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #812 = BUFFER_LOAD_UBYTE_OFFEN_exact
16875 { 813, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #813 = BUFFER_LOAD_UBYTE_OFFSET
16876 { 814, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #814 = BUFFER_LOAD_UBYTE_OFFSET_exact
16877 { 815, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #815 = BUFFER_LOAD_USHORT_ADDR64
16878 { 816, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #816 = BUFFER_LOAD_USHORT_BOTHEN
16879 { 817, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #817 = BUFFER_LOAD_USHORT_BOTHEN_exact
16880 { 818, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #818 = BUFFER_LOAD_USHORT_IDXEN
16881 { 819, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #819 = BUFFER_LOAD_USHORT_IDXEN_exact
16882 { 820, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #820 = BUFFER_LOAD_USHORT_LDS_ADDR64
16883 { 821, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #821 = BUFFER_LOAD_USHORT_LDS_BOTHEN
16884 { 822, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #822 = BUFFER_LOAD_USHORT_LDS_BOTHEN_exact
16885 { 823, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #823 = BUFFER_LOAD_USHORT_LDS_IDXEN
16886 { 824, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #824 = BUFFER_LOAD_USHORT_LDS_IDXEN_exact
16887 { 825, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #825 = BUFFER_LOAD_USHORT_LDS_OFFEN
16888 { 826, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #826 = BUFFER_LOAD_USHORT_LDS_OFFEN_exact
16889 { 827, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #827 = BUFFER_LOAD_USHORT_LDS_OFFSET
16890 { 828, 8, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList3, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #828 = BUFFER_LOAD_USHORT_LDS_OFFSET_exact
16891 { 829, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #829 = BUFFER_LOAD_USHORT_OFFEN
16892 { 830, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #830 = BUFFER_LOAD_USHORT_OFFEN_exact
16893 { 831, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #831 = BUFFER_LOAD_USHORT_OFFSET
16894 { 832, 9, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #832 = BUFFER_LOAD_USHORT_OFFSET_exact
16895 { 833, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #833 = BUFFER_STORE_BYTE_ADDR64
16896 { 834, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #834 = BUFFER_STORE_BYTE_BOTHEN
16897 { 835, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #835 = BUFFER_STORE_BYTE_BOTHEN_exact
16898 { 836, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #836 = BUFFER_STORE_BYTE_D16_HI_ADDR64
16899 { 837, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #837 = BUFFER_STORE_BYTE_D16_HI_BOTHEN
16900 { 838, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #838 = BUFFER_STORE_BYTE_D16_HI_BOTHEN_exact
16901 { 839, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #839 = BUFFER_STORE_BYTE_D16_HI_IDXEN
16902 { 840, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #840 = BUFFER_STORE_BYTE_D16_HI_IDXEN_exact
16903 { 841, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #841 = BUFFER_STORE_BYTE_D16_HI_OFFEN
16904 { 842, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #842 = BUFFER_STORE_BYTE_D16_HI_OFFEN_exact
16905 { 843, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #843 = BUFFER_STORE_BYTE_D16_HI_OFFSET
16906 { 844, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #844 = BUFFER_STORE_BYTE_D16_HI_OFFSET_exact
16907 { 845, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #845 = BUFFER_STORE_BYTE_IDXEN
16908 { 846, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #846 = BUFFER_STORE_BYTE_IDXEN_exact
16909 { 847, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #847 = BUFFER_STORE_BYTE_OFFEN
16910 { 848, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #848 = BUFFER_STORE_BYTE_OFFEN_exact
16911 { 849, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #849 = BUFFER_STORE_BYTE_OFFSET
16912 { 850, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #850 = BUFFER_STORE_BYTE_OFFSET_exact
16913 { 851, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #851 = BUFFER_STORE_DWORDX2_ADDR64
16914 { 852, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #852 = BUFFER_STORE_DWORDX2_BOTHEN
16915 { 853, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #853 = BUFFER_STORE_DWORDX2_BOTHEN_exact
16916 { 854, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #854 = BUFFER_STORE_DWORDX2_IDXEN
16917 { 855, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #855 = BUFFER_STORE_DWORDX2_IDXEN_exact
16918 { 856, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #856 = BUFFER_STORE_DWORDX2_OFFEN
16919 { 857, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #857 = BUFFER_STORE_DWORDX2_OFFEN_exact
16920 { 858, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #858 = BUFFER_STORE_DWORDX2_OFFSET
16921 { 859, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #859 = BUFFER_STORE_DWORDX2_OFFSET_exact
16922 { 860, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #860 = BUFFER_STORE_DWORDX3_ADDR64
16923 { 861, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #861 = BUFFER_STORE_DWORDX3_BOTHEN
16924 { 862, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #862 = BUFFER_STORE_DWORDX3_BOTHEN_exact
16925 { 863, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #863 = BUFFER_STORE_DWORDX3_IDXEN
16926 { 864, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #864 = BUFFER_STORE_DWORDX3_IDXEN_exact
16927 { 865, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #865 = BUFFER_STORE_DWORDX3_OFFEN
16928 { 866, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #866 = BUFFER_STORE_DWORDX3_OFFEN_exact
16929 { 867, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #867 = BUFFER_STORE_DWORDX3_OFFSET
16930 { 868, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #868 = BUFFER_STORE_DWORDX3_OFFSET_exact
16931 { 869, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #869 = BUFFER_STORE_DWORDX4_ADDR64
16932 { 870, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #870 = BUFFER_STORE_DWORDX4_BOTHEN
16933 { 871, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #871 = BUFFER_STORE_DWORDX4_BOTHEN_exact
16934 { 872, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #872 = BUFFER_STORE_DWORDX4_IDXEN
16935 { 873, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #873 = BUFFER_STORE_DWORDX4_IDXEN_exact
16936 { 874, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #874 = BUFFER_STORE_DWORDX4_OFFEN
16937 { 875, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #875 = BUFFER_STORE_DWORDX4_OFFEN_exact
16938 { 876, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #876 = BUFFER_STORE_DWORDX4_OFFSET
16939 { 877, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #877 = BUFFER_STORE_DWORDX4_OFFSET_exact
16940 { 878, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #878 = BUFFER_STORE_DWORD_ADDR64
16941 { 879, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #879 = BUFFER_STORE_DWORD_BOTHEN
16942 { 880, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #880 = BUFFER_STORE_DWORD_BOTHEN_exact
16943 { 881, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #881 = BUFFER_STORE_DWORD_IDXEN
16944 { 882, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #882 = BUFFER_STORE_DWORD_IDXEN_exact
16945 { 883, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #883 = BUFFER_STORE_DWORD_OFFEN
16946 { 884, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #884 = BUFFER_STORE_DWORD_OFFEN_exact
16947 { 885, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #885 = BUFFER_STORE_DWORD_OFFSET
16948 { 886, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #886 = BUFFER_STORE_DWORD_OFFSET_exact
16949 { 887, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #887 = BUFFER_STORE_FORMAT_D16_HI_X_ADDR64
16950 { 888, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #888 = BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN
16951 { 889, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #889 = BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_exact
16952 { 890, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #890 = BUFFER_STORE_FORMAT_D16_HI_X_IDXEN
16953 { 891, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #891 = BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_exact
16954 { 892, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #892 = BUFFER_STORE_FORMAT_D16_HI_X_OFFEN
16955 { 893, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #893 = BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_exact
16956 { 894, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #894 = BUFFER_STORE_FORMAT_D16_HI_X_OFFSET
16957 { 895, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #895 = BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_exact
16958 { 896, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #896 = BUFFER_STORE_FORMAT_D16_XYZW_ADDR64
16959 { 897, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #897 = BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN
16960 { 898, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #898 = BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact
16961 { 899, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #899 = BUFFER_STORE_FORMAT_D16_XYZW_IDXEN
16962 { 900, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #900 = BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact
16963 { 901, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #901 = BUFFER_STORE_FORMAT_D16_XYZW_OFFEN
16964 { 902, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #902 = BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact
16965 { 903, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #903 = BUFFER_STORE_FORMAT_D16_XYZW_OFFSET
16966 { 904, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #904 = BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact
16967 { 905, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #905 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_ADDR64
16968 { 906, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #906 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN
16969 { 907, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #907 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact
16970 { 908, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #908 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN
16971 { 909, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #909 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact
16972 { 910, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #910 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN
16973 { 911, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #911 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact
16974 { 912, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #912 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET
16975 { 913, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #913 = BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact
16976 { 914, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #914 = BUFFER_STORE_FORMAT_D16_XYZ_ADDR64
16977 { 915, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #915 = BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN
16978 { 916, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #916 = BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact
16979 { 917, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #917 = BUFFER_STORE_FORMAT_D16_XYZ_IDXEN
16980 { 918, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #918 = BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_exact
16981 { 919, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #919 = BUFFER_STORE_FORMAT_D16_XYZ_OFFEN
16982 { 920, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #920 = BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact
16983 { 921, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #921 = BUFFER_STORE_FORMAT_D16_XYZ_OFFSET
16984 { 922, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #922 = BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_exact
16985 { 923, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #923 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_ADDR64
16986 { 924, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #924 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN
16987 { 925, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #925 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact
16988 { 926, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #926 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN
16989 { 927, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #927 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact
16990 { 928, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #928 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN
16991 { 929, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #929 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact
16992 { 930, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #930 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET
16993 { 931, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #931 = BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact
16994 { 932, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #932 = BUFFER_STORE_FORMAT_D16_XY_ADDR64
16995 { 933, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #933 = BUFFER_STORE_FORMAT_D16_XY_BOTHEN
16996 { 934, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #934 = BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact
16997 { 935, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #935 = BUFFER_STORE_FORMAT_D16_XY_IDXEN
16998 { 936, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #936 = BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact
16999 { 937, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #937 = BUFFER_STORE_FORMAT_D16_XY_OFFEN
17000 { 938, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #938 = BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact
17001 { 939, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #939 = BUFFER_STORE_FORMAT_D16_XY_OFFSET
17002 { 940, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #940 = BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact
17003 { 941, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #941 = BUFFER_STORE_FORMAT_D16_XY_gfx80_ADDR64
17004 { 942, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #942 = BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN
17005 { 943, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #943 = BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact
17006 { 944, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #944 = BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN
17007 { 945, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #945 = BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact
17008 { 946, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #946 = BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN
17009 { 947, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #947 = BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact
17010 { 948, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #948 = BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET
17011 { 949, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #949 = BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact
17012 { 950, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #950 = BUFFER_STORE_FORMAT_D16_X_ADDR64
17013 { 951, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #951 = BUFFER_STORE_FORMAT_D16_X_BOTHEN
17014 { 952, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #952 = BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact
17015 { 953, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #953 = BUFFER_STORE_FORMAT_D16_X_IDXEN
17016 { 954, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #954 = BUFFER_STORE_FORMAT_D16_X_IDXEN_exact
17017 { 955, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #955 = BUFFER_STORE_FORMAT_D16_X_OFFEN
17018 { 956, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #956 = BUFFER_STORE_FORMAT_D16_X_OFFEN_exact
17019 { 957, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #957 = BUFFER_STORE_FORMAT_D16_X_OFFSET
17020 { 958, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #958 = BUFFER_STORE_FORMAT_D16_X_OFFSET_exact
17021 { 959, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #959 = BUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64
17022 { 960, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #960 = BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN
17023 { 961, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #961 = BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact
17024 { 962, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #962 = BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN
17025 { 963, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #963 = BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact
17026 { 964, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #964 = BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN
17027 { 965, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #965 = BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact
17028 { 966, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4080300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #966 = BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET
17029 { 967, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4081300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #967 = BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact
17030 { 968, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #968 = BUFFER_STORE_FORMAT_XYZW_ADDR64
17031 { 969, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #969 = BUFFER_STORE_FORMAT_XYZW_BOTHEN
17032 { 970, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #970 = BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact
17033 { 971, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #971 = BUFFER_STORE_FORMAT_XYZW_IDXEN
17034 { 972, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #972 = BUFFER_STORE_FORMAT_XYZW_IDXEN_exact
17035 { 973, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #973 = BUFFER_STORE_FORMAT_XYZW_OFFEN
17036 { 974, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #974 = BUFFER_STORE_FORMAT_XYZW_OFFEN_exact
17037 { 975, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #975 = BUFFER_STORE_FORMAT_XYZW_OFFSET
17038 { 976, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #976 = BUFFER_STORE_FORMAT_XYZW_OFFSET_exact
17039 { 977, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #977 = BUFFER_STORE_FORMAT_XYZ_ADDR64
17040 { 978, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #978 = BUFFER_STORE_FORMAT_XYZ_BOTHEN
17041 { 979, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #979 = BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact
17042 { 980, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #980 = BUFFER_STORE_FORMAT_XYZ_IDXEN
17043 { 981, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #981 = BUFFER_STORE_FORMAT_XYZ_IDXEN_exact
17044 { 982, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #982 = BUFFER_STORE_FORMAT_XYZ_OFFEN
17045 { 983, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #983 = BUFFER_STORE_FORMAT_XYZ_OFFEN_exact
17046 { 984, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #984 = BUFFER_STORE_FORMAT_XYZ_OFFSET
17047 { 985, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #985 = BUFFER_STORE_FORMAT_XYZ_OFFSET_exact
17048 { 986, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #986 = BUFFER_STORE_FORMAT_XY_ADDR64
17049 { 987, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #987 = BUFFER_STORE_FORMAT_XY_BOTHEN
17050 { 988, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #988 = BUFFER_STORE_FORMAT_XY_BOTHEN_exact
17051 { 989, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #989 = BUFFER_STORE_FORMAT_XY_IDXEN
17052 { 990, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #990 = BUFFER_STORE_FORMAT_XY_IDXEN_exact
17053 { 991, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #991 = BUFFER_STORE_FORMAT_XY_OFFEN
17054 { 992, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #992 = BUFFER_STORE_FORMAT_XY_OFFEN_exact
17055 { 993, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #993 = BUFFER_STORE_FORMAT_XY_OFFSET
17056 { 994, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #994 = BUFFER_STORE_FORMAT_XY_OFFSET_exact
17057 { 995, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #995 = BUFFER_STORE_FORMAT_X_ADDR64
17058 { 996, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #996 = BUFFER_STORE_FORMAT_X_BOTHEN
17059 { 997, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #997 = BUFFER_STORE_FORMAT_X_BOTHEN_exact
17060 { 998, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #998 = BUFFER_STORE_FORMAT_X_IDXEN
17061 { 999, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #999 = BUFFER_STORE_FORMAT_X_IDXEN_exact
17062 { 1000, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1000 = BUFFER_STORE_FORMAT_X_OFFEN
17063 { 1001, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1001 = BUFFER_STORE_FORMAT_X_OFFEN_exact
17064 { 1002, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1002 = BUFFER_STORE_FORMAT_X_OFFSET
17065 { 1003, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1003 = BUFFER_STORE_FORMAT_X_OFFSET_exact
17066 { 1004, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList3, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1004 = BUFFER_STORE_LDS_DWORD
17067 { 1005, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1005 = BUFFER_STORE_SHORT_ADDR64
17068 { 1006, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1006 = BUFFER_STORE_SHORT_BOTHEN
17069 { 1007, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1007 = BUFFER_STORE_SHORT_BOTHEN_exact
17070 { 1008, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1008 = BUFFER_STORE_SHORT_D16_HI_ADDR64
17071 { 1009, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1009 = BUFFER_STORE_SHORT_D16_HI_BOTHEN
17072 { 1010, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1010 = BUFFER_STORE_SHORT_D16_HI_BOTHEN_exact
17073 { 1011, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1011 = BUFFER_STORE_SHORT_D16_HI_IDXEN
17074 { 1012, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1012 = BUFFER_STORE_SHORT_D16_HI_IDXEN_exact
17075 { 1013, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1013 = BUFFER_STORE_SHORT_D16_HI_OFFEN
17076 { 1014, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1014 = BUFFER_STORE_SHORT_D16_HI_OFFEN_exact
17077 { 1015, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1015 = BUFFER_STORE_SHORT_D16_HI_OFFSET
17078 { 1016, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1016 = BUFFER_STORE_SHORT_D16_HI_OFFSET_exact
17079 { 1017, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1017 = BUFFER_STORE_SHORT_IDXEN
17080 { 1018, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1018 = BUFFER_STORE_SHORT_IDXEN_exact
17081 { 1019, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1019 = BUFFER_STORE_SHORT_OFFEN
17082 { 1020, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1020 = BUFFER_STORE_SHORT_OFFEN_exact
17083 { 1021, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1021 = BUFFER_STORE_SHORT_OFFSET
17084 { 1022, 9, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1022 = BUFFER_STORE_SHORT_OFFSET_exact
17085 { 1023, 0, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x300010000ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #1023 = BUFFER_WBINVL1
17086 { 1024, 0, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x300010000ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #1024 = BUFFER_WBINVL1_SC
17087 { 1025, 0, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x300010000ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #1025 = BUFFER_WBINVL1_VOL
17088 { 1026, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1026 = DS_ADD_F32
17089 { 1027, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1027 = DS_ADD_F32_gfx9
17090 { 1028, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1028 = DS_ADD_RTN_F32
17091 { 1029, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1029 = DS_ADD_RTN_F32_gfx9
17092 { 1030, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1030 = DS_ADD_RTN_U32
17093 { 1031, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1031 = DS_ADD_RTN_U32_gfx9
17094 { 1032, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1032 = DS_ADD_RTN_U64
17095 { 1033, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1033 = DS_ADD_RTN_U64_gfx9
17096 { 1034, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1034 = DS_ADD_SRC2_F32
17097 { 1035, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1035 = DS_ADD_SRC2_U32
17098 { 1036, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1036 = DS_ADD_SRC2_U64
17099 { 1037, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1037 = DS_ADD_U32
17100 { 1038, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1038 = DS_ADD_U32_gfx9
17101 { 1039, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1039 = DS_ADD_U64
17102 { 1040, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1040 = DS_ADD_U64_gfx9
17103 { 1041, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1041 = DS_AND_B32
17104 { 1042, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1042 = DS_AND_B32_gfx9
17105 { 1043, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1043 = DS_AND_B64
17106 { 1044, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1044 = DS_AND_B64_gfx9
17107 { 1045, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1045 = DS_AND_RTN_B32
17108 { 1046, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1046 = DS_AND_RTN_B32_gfx9
17109 { 1047, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1047 = DS_AND_RTN_B64
17110 { 1048, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1048 = DS_AND_RTN_B64_gfx9
17111 { 1049, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1049 = DS_AND_SRC2_B32
17112 { 1050, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1050 = DS_AND_SRC2_B64
17113 { 1051, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1051 = DS_APPEND
17114 { 1052, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1052 = DS_BPERMUTE_B32
17115 { 1053, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1053 = DS_CMPST_B32
17116 { 1054, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1054 = DS_CMPST_B32_gfx9
17117 { 1055, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1055 = DS_CMPST_B64
17118 { 1056, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1056 = DS_CMPST_B64_gfx9
17119 { 1057, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1057 = DS_CMPST_F32
17120 { 1058, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1058 = DS_CMPST_F32_gfx9
17121 { 1059, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1059 = DS_CMPST_F64
17122 { 1060, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1060 = DS_CMPST_F64_gfx9
17123 { 1061, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1061 = DS_CMPST_RTN_B32
17124 { 1062, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1062 = DS_CMPST_RTN_B32_gfx9
17125 { 1063, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1063 = DS_CMPST_RTN_B64
17126 { 1064, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1064 = DS_CMPST_RTN_B64_gfx9
17127 { 1065, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1065 = DS_CMPST_RTN_F32
17128 { 1066, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1066 = DS_CMPST_RTN_F32_gfx9
17129 { 1067, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1067 = DS_CMPST_RTN_F64
17130 { 1068, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1068 = DS_CMPST_RTN_F64_gfx9
17131 { 1069, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1069 = DS_CONDXCHG32_RTN_B64
17132 { 1070, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1070 = DS_CONDXCHG32_RTN_B64_gfx9
17133 { 1071, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1071 = DS_CONSUME
17134 { 1072, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1072 = DS_DEC_RTN_U32
17135 { 1073, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1073 = DS_DEC_RTN_U32_gfx9
17136 { 1074, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1074 = DS_DEC_RTN_U64
17137 { 1075, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1075 = DS_DEC_RTN_U64_gfx9
17138 { 1076, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1076 = DS_DEC_SRC2_U32
17139 { 1077, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1077 = DS_DEC_SRC2_U64
17140 { 1078, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1078 = DS_DEC_U32
17141 { 1079, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1079 = DS_DEC_U32_gfx9
17142 { 1080, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1080 = DS_DEC_U64
17143 { 1081, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1081 = DS_DEC_U64_gfx9
17144 { 1082, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1082 = DS_GWS_BARRIER
17145 { 1083, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1083 = DS_GWS_INIT
17146 { 1084, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1084 = DS_GWS_SEMA_BR
17147 { 1085, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1085 = DS_GWS_SEMA_P
17148 { 1086, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1086 = DS_GWS_SEMA_RELEASE_ALL
17149 { 1087, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1087 = DS_GWS_SEMA_V
17150 { 1088, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1088 = DS_INC_RTN_U32
17151 { 1089, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1089 = DS_INC_RTN_U32_gfx9
17152 { 1090, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1090 = DS_INC_RTN_U64
17153 { 1091, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1091 = DS_INC_RTN_U64_gfx9
17154 { 1092, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1092 = DS_INC_SRC2_U32
17155 { 1093, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1093 = DS_INC_SRC2_U64
17156 { 1094, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1094 = DS_INC_U32
17157 { 1095, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1095 = DS_INC_U32_gfx9
17158 { 1096, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1096 = DS_INC_U64
17159 { 1097, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1097 = DS_INC_U64_gfx9
17160 { 1098, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1098 = DS_MAX_F32
17161 { 1099, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1099 = DS_MAX_F32_gfx9
17162 { 1100, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1100 = DS_MAX_F64
17163 { 1101, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1101 = DS_MAX_F64_gfx9
17164 { 1102, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1102 = DS_MAX_I32
17165 { 1103, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1103 = DS_MAX_I32_gfx9
17166 { 1104, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1104 = DS_MAX_I64
17167 { 1105, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1105 = DS_MAX_I64_gfx9
17168 { 1106, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1106 = DS_MAX_RTN_F32
17169 { 1107, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1107 = DS_MAX_RTN_F32_gfx9
17170 { 1108, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1108 = DS_MAX_RTN_F64
17171 { 1109, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1109 = DS_MAX_RTN_F64_gfx9
17172 { 1110, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1110 = DS_MAX_RTN_I32
17173 { 1111, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1111 = DS_MAX_RTN_I32_gfx9
17174 { 1112, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1112 = DS_MAX_RTN_I64
17175 { 1113, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1113 = DS_MAX_RTN_I64_gfx9
17176 { 1114, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1114 = DS_MAX_RTN_U32
17177 { 1115, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1115 = DS_MAX_RTN_U32_gfx9
17178 { 1116, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1116 = DS_MAX_RTN_U64
17179 { 1117, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1117 = DS_MAX_RTN_U64_gfx9
17180 { 1118, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1118 = DS_MAX_SRC2_F32
17181 { 1119, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1119 = DS_MAX_SRC2_F64
17182 { 1120, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1120 = DS_MAX_SRC2_I32
17183 { 1121, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1121 = DS_MAX_SRC2_I64
17184 { 1122, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1122 = DS_MAX_SRC2_U32
17185 { 1123, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1123 = DS_MAX_SRC2_U64
17186 { 1124, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1124 = DS_MAX_U32
17187 { 1125, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1125 = DS_MAX_U32_gfx9
17188 { 1126, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1126 = DS_MAX_U64
17189 { 1127, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1127 = DS_MAX_U64_gfx9
17190 { 1128, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1128 = DS_MIN_F32
17191 { 1129, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1129 = DS_MIN_F32_gfx9
17192 { 1130, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1130 = DS_MIN_F64
17193 { 1131, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1131 = DS_MIN_F64_gfx9
17194 { 1132, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1132 = DS_MIN_I32
17195 { 1133, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1133 = DS_MIN_I32_gfx9
17196 { 1134, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1134 = DS_MIN_I64
17197 { 1135, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1135 = DS_MIN_I64_gfx9
17198 { 1136, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1136 = DS_MIN_RTN_F32
17199 { 1137, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1137 = DS_MIN_RTN_F32_gfx9
17200 { 1138, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1138 = DS_MIN_RTN_F64
17201 { 1139, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1139 = DS_MIN_RTN_F64_gfx9
17202 { 1140, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1140 = DS_MIN_RTN_I32
17203 { 1141, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1141 = DS_MIN_RTN_I32_gfx9
17204 { 1142, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1142 = DS_MIN_RTN_I64
17205 { 1143, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1143 = DS_MIN_RTN_I64_gfx9
17206 { 1144, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1144 = DS_MIN_RTN_U32
17207 { 1145, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1145 = DS_MIN_RTN_U32_gfx9
17208 { 1146, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1146 = DS_MIN_RTN_U64
17209 { 1147, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1147 = DS_MIN_RTN_U64_gfx9
17210 { 1148, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1148 = DS_MIN_SRC2_F32
17211 { 1149, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1149 = DS_MIN_SRC2_F64
17212 { 1150, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1150 = DS_MIN_SRC2_I32
17213 { 1151, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1151 = DS_MIN_SRC2_I64
17214 { 1152, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1152 = DS_MIN_SRC2_U32
17215 { 1153, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1153 = DS_MIN_SRC2_U64
17216 { 1154, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1154 = DS_MIN_U32
17217 { 1155, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1155 = DS_MIN_U32_gfx9
17218 { 1156, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1156 = DS_MIN_U64
17219 { 1157, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1157 = DS_MIN_U64_gfx9
17220 { 1158, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1158 = DS_MSKOR_B32
17221 { 1159, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1159 = DS_MSKOR_B32_gfx9
17222 { 1160, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1160 = DS_MSKOR_B64
17223 { 1161, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1161 = DS_MSKOR_B64_gfx9
17224 { 1162, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1162 = DS_MSKOR_RTN_B32
17225 { 1163, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1163 = DS_MSKOR_RTN_B32_gfx9
17226 { 1164, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1164 = DS_MSKOR_RTN_B64
17227 { 1165, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #1165 = DS_MSKOR_RTN_B64_gfx9
17228 { 1166, 0, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x80400400000ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr }, // Inst #1166 = DS_NOP
17229 { 1167, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1167 = DS_ORDERED_COUNT
17230 { 1168, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1168 = DS_OR_B32
17231 { 1169, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1169 = DS_OR_B32_gfx9
17232 { 1170, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1170 = DS_OR_B64
17233 { 1171, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1171 = DS_OR_B64_gfx9
17234 { 1172, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1172 = DS_OR_RTN_B32
17235 { 1173, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1173 = DS_OR_RTN_B32_gfx9
17236 { 1174, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1174 = DS_OR_RTN_B64
17237 { 1175, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1175 = DS_OR_RTN_B64_gfx9
17238 { 1176, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1176 = DS_OR_SRC2_B32
17239 { 1177, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1177 = DS_OR_SRC2_B64
17240 { 1178, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1178 = DS_PERMUTE_B32
17241 { 1179, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #1179 = DS_READ2ST64_B32
17242 { 1180, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #1180 = DS_READ2ST64_B32_gfx9
17243 { 1181, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1181 = DS_READ2ST64_B64
17244 { 1182, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1182 = DS_READ2ST64_B64_gfx9
17245 { 1183, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #1183 = DS_READ2_B32
17246 { 1184, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #1184 = DS_READ2_B32_gfx9
17247 { 1185, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1185 = DS_READ2_B64
17248 { 1186, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1186 = DS_READ2_B64_gfx9
17249 { 1187, 3, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1187 = DS_READ_ADDTID_B32
17250 { 1188, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1188 = DS_READ_B128
17251 { 1189, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1189 = DS_READ_B128_gfx9
17252 { 1190, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1190 = DS_READ_B32
17253 { 1191, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1191 = DS_READ_B32_gfx9
17254 { 1192, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1192 = DS_READ_B64
17255 { 1193, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1193 = DS_READ_B64_gfx9
17256 { 1194, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #1194 = DS_READ_B96
17257 { 1195, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #1195 = DS_READ_B96_gfx9
17258 { 1196, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1196 = DS_READ_I16
17259 { 1197, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1197 = DS_READ_I16_gfx9
17260 { 1198, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1198 = DS_READ_I8
17261 { 1199, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #1199 = DS_READ_I8_D16
17262 { 1200, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #1200 = DS_READ_I8_D16_HI
17263 { 1201, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1201 = DS_READ_I8_gfx9
17264 { 1202, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1202 = DS_READ_U16
17265 { 1203, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #1203 = DS_READ_U16_D16
17266 { 1204, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #1204 = DS_READ_U16_D16_HI
17267 { 1205, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1205 = DS_READ_U16_gfx9
17268 { 1206, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1206 = DS_READ_U8
17269 { 1207, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #1207 = DS_READ_U8_D16
17270 { 1208, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #1208 = DS_READ_U8_D16_HI
17271 { 1209, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1209 = DS_READ_U8_gfx9
17272 { 1210, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1210 = DS_RSUB_RTN_U32
17273 { 1211, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1211 = DS_RSUB_RTN_U32_gfx9
17274 { 1212, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1212 = DS_RSUB_RTN_U64
17275 { 1213, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1213 = DS_RSUB_RTN_U64_gfx9
17276 { 1214, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1214 = DS_RSUB_SRC2_U32
17277 { 1215, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1215 = DS_RSUB_SRC2_U64
17278 { 1216, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1216 = DS_RSUB_U32
17279 { 1217, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1217 = DS_RSUB_U32_gfx9
17280 { 1218, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1218 = DS_RSUB_U64
17281 { 1219, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1219 = DS_RSUB_U64_gfx9
17282 { 1220, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1220 = DS_SUB_RTN_U32
17283 { 1221, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1221 = DS_SUB_RTN_U32_gfx9
17284 { 1222, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1222 = DS_SUB_RTN_U64
17285 { 1223, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1223 = DS_SUB_RTN_U64_gfx9
17286 { 1224, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1224 = DS_SUB_SRC2_U32
17287 { 1225, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1225 = DS_SUB_SRC2_U64
17288 { 1226, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1226 = DS_SUB_U32
17289 { 1227, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1227 = DS_SUB_U32_gfx9
17290 { 1228, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1228 = DS_SUB_U64
17291 { 1229, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1229 = DS_SUB_U64_gfx9
17292 { 1230, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1230 = DS_SWIZZLE_B32
17293 { 1231, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1231 = DS_WRAP_RTN_B32
17294 { 1232, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1232 = DS_WRAP_RTN_B32_gfx9
17295 { 1233, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #1233 = DS_WRITE2ST64_B32
17296 { 1234, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #1234 = DS_WRITE2ST64_B32_gfx9
17297 { 1235, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #1235 = DS_WRITE2ST64_B64
17298 { 1236, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #1236 = DS_WRITE2ST64_B64_gfx9
17299 { 1237, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #1237 = DS_WRITE2_B32
17300 { 1238, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #1238 = DS_WRITE2_B32_gfx9
17301 { 1239, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #1239 = DS_WRITE2_B64
17302 { 1240, 6, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #1240 = DS_WRITE2_B64_gfx9
17303 { 1241, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1241 = DS_WRITE_ADDTID_B32
17304 { 1242, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1242 = DS_WRITE_B128
17305 { 1243, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1243 = DS_WRITE_B128_gfx9
17306 { 1244, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1244 = DS_WRITE_B16
17307 { 1245, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1245 = DS_WRITE_B16_D16_HI
17308 { 1246, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1246 = DS_WRITE_B16_gfx9
17309 { 1247, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1247 = DS_WRITE_B32
17310 { 1248, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1248 = DS_WRITE_B32_gfx9
17311 { 1249, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1249 = DS_WRITE_B64
17312 { 1250, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1250 = DS_WRITE_B64_gfx9
17313 { 1251, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1251 = DS_WRITE_B8
17314 { 1252, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1252 = DS_WRITE_B8_D16_HI
17315 { 1253, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1253 = DS_WRITE_B8_gfx9
17316 { 1254, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1254 = DS_WRITE_B96
17317 { 1255, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1255 = DS_WRITE_B96_gfx9
17318 { 1256, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1256 = DS_WRITE_SRC2_B32
17319 { 1257, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1257 = DS_WRITE_SRC2_B64
17320 { 1258, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1258 = DS_WRXCHG2ST64_RTN_B32
17321 { 1259, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1259 = DS_WRXCHG2ST64_RTN_B32_gfx9
17322 { 1260, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1260 = DS_WRXCHG2ST64_RTN_B64
17323 { 1261, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1261 = DS_WRXCHG2ST64_RTN_B64_gfx9
17324 { 1262, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1262 = DS_WRXCHG2_RTN_B32
17325 { 1263, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1263 = DS_WRXCHG2_RTN_B32_gfx9
17326 { 1264, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1264 = DS_WRXCHG2_RTN_B64
17327 { 1265, 7, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1265 = DS_WRXCHG2_RTN_B64_gfx9
17328 { 1266, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1266 = DS_WRXCHG_RTN_B32
17329 { 1267, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1267 = DS_WRXCHG_RTN_B32_gfx9
17330 { 1268, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1268 = DS_WRXCHG_RTN_B64
17331 { 1269, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1269 = DS_WRXCHG_RTN_B64_gfx9
17332 { 1270, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1270 = DS_XOR_B32
17333 { 1271, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1271 = DS_XOR_B32_gfx9
17334 { 1272, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1272 = DS_XOR_B64
17335 { 1273, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1273 = DS_XOR_B64_gfx9
17336 { 1274, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1274 = DS_XOR_RTN_B32
17337 { 1275, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1275 = DS_XOR_RTN_B32_gfx9
17338 { 1276, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1276 = DS_XOR_RTN_B64
17339 { 1277, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1277 = DS_XOR_RTN_B64_gfx9
17340 { 1278, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1278 = DS_XOR_SRC2_B32
17341 { 1279, 3, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #1279 = DS_XOR_SRC2_B64
17342 { 1280, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x1ULL, nullptr, ImplicitList2, OperandInfo104, -1 ,nullptr }, // Inst #1280 = ENTER_WWM
17343 { 1281, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x1ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1281 = EXIT_WWM
17344 { 1282, 8, 0, 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1200100000ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #1282 = EXP
17345 { 1283, 8, 0, 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1200100000ULL, ImplicitList2, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #1283 = EXP_DONE
17346 { 1284, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1284 = FLAT_ATOMIC_ADD
17347 { 1285, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1285 = FLAT_ATOMIC_ADD_RTN
17348 { 1286, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1286 = FLAT_ATOMIC_ADD_X2
17349 { 1287, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1287 = FLAT_ATOMIC_ADD_X2_RTN
17350 { 1288, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1288 = FLAT_ATOMIC_AND
17351 { 1289, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1289 = FLAT_ATOMIC_AND_RTN
17352 { 1290, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1290 = FLAT_ATOMIC_AND_X2
17353 { 1291, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1291 = FLAT_ATOMIC_AND_X2_RTN
17354 { 1292, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1292 = FLAT_ATOMIC_CMPSWAP
17355 { 1293, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1293 = FLAT_ATOMIC_CMPSWAP_RTN
17356 { 1294, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1294 = FLAT_ATOMIC_CMPSWAP_X2
17357 { 1295, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1295 = FLAT_ATOMIC_CMPSWAP_X2_RTN
17358 { 1296, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1296 = FLAT_ATOMIC_DEC
17359 { 1297, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1297 = FLAT_ATOMIC_DEC_RTN
17360 { 1298, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1298 = FLAT_ATOMIC_DEC_X2
17361 { 1299, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1299 = FLAT_ATOMIC_DEC_X2_RTN
17362 { 1300, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1300 = FLAT_ATOMIC_FCMPSWAP
17363 { 1301, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1301 = FLAT_ATOMIC_FCMPSWAP_RTN
17364 { 1302, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1302 = FLAT_ATOMIC_FCMPSWAP_X2
17365 { 1303, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1303 = FLAT_ATOMIC_FCMPSWAP_X2_RTN
17366 { 1304, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1304 = FLAT_ATOMIC_FMAX
17367 { 1305, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1305 = FLAT_ATOMIC_FMAX_RTN
17368 { 1306, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1306 = FLAT_ATOMIC_FMAX_X2
17369 { 1307, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1307 = FLAT_ATOMIC_FMAX_X2_RTN
17370 { 1308, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1308 = FLAT_ATOMIC_FMIN
17371 { 1309, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1309 = FLAT_ATOMIC_FMIN_RTN
17372 { 1310, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1310 = FLAT_ATOMIC_FMIN_X2
17373 { 1311, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x20080500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1311 = FLAT_ATOMIC_FMIN_X2_RTN
17374 { 1312, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1312 = FLAT_ATOMIC_INC
17375 { 1313, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1313 = FLAT_ATOMIC_INC_RTN
17376 { 1314, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1314 = FLAT_ATOMIC_INC_X2
17377 { 1315, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1315 = FLAT_ATOMIC_INC_X2_RTN
17378 { 1316, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1316 = FLAT_ATOMIC_OR
17379 { 1317, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1317 = FLAT_ATOMIC_OR_RTN
17380 { 1318, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1318 = FLAT_ATOMIC_OR_X2
17381 { 1319, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1319 = FLAT_ATOMIC_OR_X2_RTN
17382 { 1320, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1320 = FLAT_ATOMIC_SMAX
17383 { 1321, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1321 = FLAT_ATOMIC_SMAX_RTN
17384 { 1322, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1322 = FLAT_ATOMIC_SMAX_X2
17385 { 1323, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1323 = FLAT_ATOMIC_SMAX_X2_RTN
17386 { 1324, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1324 = FLAT_ATOMIC_SMIN
17387 { 1325, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1325 = FLAT_ATOMIC_SMIN_RTN
17388 { 1326, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1326 = FLAT_ATOMIC_SMIN_X2
17389 { 1327, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1327 = FLAT_ATOMIC_SMIN_X2_RTN
17390 { 1328, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1328 = FLAT_ATOMIC_SUB
17391 { 1329, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1329 = FLAT_ATOMIC_SUB_RTN
17392 { 1330, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1330 = FLAT_ATOMIC_SUB_X2
17393 { 1331, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1331 = FLAT_ATOMIC_SUB_X2_RTN
17394 { 1332, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1332 = FLAT_ATOMIC_SWAP
17395 { 1333, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1333 = FLAT_ATOMIC_SWAP_RTN
17396 { 1334, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1334 = FLAT_ATOMIC_SWAP_X2
17397 { 1335, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1335 = FLAT_ATOMIC_SWAP_X2_RTN
17398 { 1336, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1336 = FLAT_ATOMIC_UMAX
17399 { 1337, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1337 = FLAT_ATOMIC_UMAX_RTN
17400 { 1338, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1338 = FLAT_ATOMIC_UMAX_X2
17401 { 1339, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1339 = FLAT_ATOMIC_UMAX_X2_RTN
17402 { 1340, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1340 = FLAT_ATOMIC_UMIN
17403 { 1341, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1341 = FLAT_ATOMIC_UMIN_RTN
17404 { 1342, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1342 = FLAT_ATOMIC_UMIN_X2
17405 { 1343, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1343 = FLAT_ATOMIC_UMIN_X2_RTN
17406 { 1344, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1344 = FLAT_ATOMIC_XOR
17407 { 1345, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1345 = FLAT_ATOMIC_XOR_RTN
17408 { 1346, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1346 = FLAT_ATOMIC_XOR_X2
17409 { 1347, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1347 = FLAT_ATOMIC_XOR_X2_RTN
17410 { 1348, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1348 = FLAT_LOAD_DWORD
17411 { 1349, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1349 = FLAT_LOAD_DWORDX2
17412 { 1350, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #1350 = FLAT_LOAD_DWORDX3
17413 { 1351, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1351 = FLAT_LOAD_DWORDX4
17414 { 1352, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1352 = FLAT_LOAD_SBYTE
17415 { 1353, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1353 = FLAT_LOAD_SBYTE_D16
17416 { 1354, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1354 = FLAT_LOAD_SBYTE_D16_HI
17417 { 1355, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1355 = FLAT_LOAD_SHORT_D16
17418 { 1356, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1356 = FLAT_LOAD_SHORT_D16_HI
17419 { 1357, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1357 = FLAT_LOAD_SSHORT
17420 { 1358, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1358 = FLAT_LOAD_UBYTE
17421 { 1359, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1359 = FLAT_LOAD_UBYTE_D16
17422 { 1360, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1360 = FLAT_LOAD_UBYTE_D16_HI
17423 { 1361, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1361 = FLAT_LOAD_USHORT
17424 { 1362, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1362 = FLAT_STORE_BYTE
17425 { 1363, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1363 = FLAT_STORE_BYTE_D16_HI
17426 { 1364, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1364 = FLAT_STORE_DWORD
17427 { 1365, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1365 = FLAT_STORE_DWORDX2
17428 { 1366, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1366 = FLAT_STORE_DWORDX3
17429 { 1367, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #1367 = FLAT_STORE_DWORDX4
17430 { 1368, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1368 = FLAT_STORE_SHORT
17431 { 1369, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80500200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1369 = FLAT_STORE_SHORT_D16_HI
17432 { 1370, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x1ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #1370 = GET_GROUPSTATICSIZE
17433 { 1371, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1371 = GLOBAL_ATOMIC_ADD
17434 { 1372, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1372 = GLOBAL_ATOMIC_ADD_F32
17435 { 1373, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1373 = GLOBAL_ATOMIC_ADD_F32_SADDR
17436 { 1374, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1374 = GLOBAL_ATOMIC_ADD_RTN
17437 { 1375, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1375 = GLOBAL_ATOMIC_ADD_SADDR
17438 { 1376, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1376 = GLOBAL_ATOMIC_ADD_SADDR_RTN
17439 { 1377, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1377 = GLOBAL_ATOMIC_ADD_X2
17440 { 1378, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1378 = GLOBAL_ATOMIC_ADD_X2_RTN
17441 { 1379, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1379 = GLOBAL_ATOMIC_ADD_X2_SADDR
17442 { 1380, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1380 = GLOBAL_ATOMIC_ADD_X2_SADDR_RTN
17443 { 1381, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1381 = GLOBAL_ATOMIC_AND
17444 { 1382, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1382 = GLOBAL_ATOMIC_AND_RTN
17445 { 1383, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1383 = GLOBAL_ATOMIC_AND_SADDR
17446 { 1384, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1384 = GLOBAL_ATOMIC_AND_SADDR_RTN
17447 { 1385, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1385 = GLOBAL_ATOMIC_AND_X2
17448 { 1386, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1386 = GLOBAL_ATOMIC_AND_X2_RTN
17449 { 1387, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1387 = GLOBAL_ATOMIC_AND_X2_SADDR
17450 { 1388, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1388 = GLOBAL_ATOMIC_AND_X2_SADDR_RTN
17451 { 1389, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1389 = GLOBAL_ATOMIC_CMPSWAP
17452 { 1390, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1390 = GLOBAL_ATOMIC_CMPSWAP_RTN
17453 { 1391, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1391 = GLOBAL_ATOMIC_CMPSWAP_SADDR
17454 { 1392, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1392 = GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN
17455 { 1393, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1393 = GLOBAL_ATOMIC_CMPSWAP_X2
17456 { 1394, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1394 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN
17457 { 1395, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1395 = GLOBAL_ATOMIC_CMPSWAP_X2_SADDR
17458 { 1396, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1396 = GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN
17459 { 1397, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1397 = GLOBAL_ATOMIC_DEC
17460 { 1398, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1398 = GLOBAL_ATOMIC_DEC_RTN
17461 { 1399, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1399 = GLOBAL_ATOMIC_DEC_SADDR
17462 { 1400, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1400 = GLOBAL_ATOMIC_DEC_SADDR_RTN
17463 { 1401, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1401 = GLOBAL_ATOMIC_DEC_X2
17464 { 1402, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1402 = GLOBAL_ATOMIC_DEC_X2_RTN
17465 { 1403, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1403 = GLOBAL_ATOMIC_DEC_X2_SADDR
17466 { 1404, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1404 = GLOBAL_ATOMIC_DEC_X2_SADDR_RTN
17467 { 1405, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1405 = GLOBAL_ATOMIC_FCMPSWAP
17468 { 1406, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1406 = GLOBAL_ATOMIC_FCMPSWAP_RTN
17469 { 1407, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1407 = GLOBAL_ATOMIC_FCMPSWAP_SADDR
17470 { 1408, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1408 = GLOBAL_ATOMIC_FCMPSWAP_SADDR_RTN
17471 { 1409, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1409 = GLOBAL_ATOMIC_FCMPSWAP_X2
17472 { 1410, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1410 = GLOBAL_ATOMIC_FCMPSWAP_X2_RTN
17473 { 1411, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1411 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR
17474 { 1412, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1412 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN
17475 { 1413, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1413 = GLOBAL_ATOMIC_FMAX
17476 { 1414, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1414 = GLOBAL_ATOMIC_FMAX_RTN
17477 { 1415, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1415 = GLOBAL_ATOMIC_FMAX_SADDR
17478 { 1416, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1416 = GLOBAL_ATOMIC_FMAX_SADDR_RTN
17479 { 1417, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1417 = GLOBAL_ATOMIC_FMAX_X2
17480 { 1418, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1418 = GLOBAL_ATOMIC_FMAX_X2_RTN
17481 { 1419, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1419 = GLOBAL_ATOMIC_FMAX_X2_SADDR
17482 { 1420, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1420 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN
17483 { 1421, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1421 = GLOBAL_ATOMIC_FMIN
17484 { 1422, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1422 = GLOBAL_ATOMIC_FMIN_RTN
17485 { 1423, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1423 = GLOBAL_ATOMIC_FMIN_SADDR
17486 { 1424, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1424 = GLOBAL_ATOMIC_FMIN_SADDR_RTN
17487 { 1425, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1425 = GLOBAL_ATOMIC_FMIN_X2
17488 { 1426, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1426 = GLOBAL_ATOMIC_FMIN_X2_RTN
17489 { 1427, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1427 = GLOBAL_ATOMIC_FMIN_X2_SADDR
17490 { 1428, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1428 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN
17491 { 1429, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1429 = GLOBAL_ATOMIC_INC
17492 { 1430, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1430 = GLOBAL_ATOMIC_INC_RTN
17493 { 1431, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1431 = GLOBAL_ATOMIC_INC_SADDR
17494 { 1432, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1432 = GLOBAL_ATOMIC_INC_SADDR_RTN
17495 { 1433, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1433 = GLOBAL_ATOMIC_INC_X2
17496 { 1434, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1434 = GLOBAL_ATOMIC_INC_X2_RTN
17497 { 1435, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1435 = GLOBAL_ATOMIC_INC_X2_SADDR
17498 { 1436, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1436 = GLOBAL_ATOMIC_INC_X2_SADDR_RTN
17499 { 1437, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1437 = GLOBAL_ATOMIC_OR
17500 { 1438, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1438 = GLOBAL_ATOMIC_OR_RTN
17501 { 1439, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1439 = GLOBAL_ATOMIC_OR_SADDR
17502 { 1440, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1440 = GLOBAL_ATOMIC_OR_SADDR_RTN
17503 { 1441, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1441 = GLOBAL_ATOMIC_OR_X2
17504 { 1442, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1442 = GLOBAL_ATOMIC_OR_X2_RTN
17505 { 1443, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1443 = GLOBAL_ATOMIC_OR_X2_SADDR
17506 { 1444, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1444 = GLOBAL_ATOMIC_OR_X2_SADDR_RTN
17507 { 1445, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1445 = GLOBAL_ATOMIC_PK_ADD_F16
17508 { 1446, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x28080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1446 = GLOBAL_ATOMIC_PK_ADD_F16_SADDR
17509 { 1447, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1447 = GLOBAL_ATOMIC_SMAX
17510 { 1448, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1448 = GLOBAL_ATOMIC_SMAX_RTN
17511 { 1449, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1449 = GLOBAL_ATOMIC_SMAX_SADDR
17512 { 1450, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1450 = GLOBAL_ATOMIC_SMAX_SADDR_RTN
17513 { 1451, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1451 = GLOBAL_ATOMIC_SMAX_X2
17514 { 1452, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1452 = GLOBAL_ATOMIC_SMAX_X2_RTN
17515 { 1453, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1453 = GLOBAL_ATOMIC_SMAX_X2_SADDR
17516 { 1454, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1454 = GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN
17517 { 1455, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1455 = GLOBAL_ATOMIC_SMIN
17518 { 1456, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1456 = GLOBAL_ATOMIC_SMIN_RTN
17519 { 1457, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1457 = GLOBAL_ATOMIC_SMIN_SADDR
17520 { 1458, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1458 = GLOBAL_ATOMIC_SMIN_SADDR_RTN
17521 { 1459, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1459 = GLOBAL_ATOMIC_SMIN_X2
17522 { 1460, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1460 = GLOBAL_ATOMIC_SMIN_X2_RTN
17523 { 1461, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1461 = GLOBAL_ATOMIC_SMIN_X2_SADDR
17524 { 1462, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1462 = GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN
17525 { 1463, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1463 = GLOBAL_ATOMIC_SUB
17526 { 1464, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1464 = GLOBAL_ATOMIC_SUB_RTN
17527 { 1465, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1465 = GLOBAL_ATOMIC_SUB_SADDR
17528 { 1466, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1466 = GLOBAL_ATOMIC_SUB_SADDR_RTN
17529 { 1467, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1467 = GLOBAL_ATOMIC_SUB_X2
17530 { 1468, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1468 = GLOBAL_ATOMIC_SUB_X2_RTN
17531 { 1469, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1469 = GLOBAL_ATOMIC_SUB_X2_SADDR
17532 { 1470, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1470 = GLOBAL_ATOMIC_SUB_X2_SADDR_RTN
17533 { 1471, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1471 = GLOBAL_ATOMIC_SWAP
17534 { 1472, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1472 = GLOBAL_ATOMIC_SWAP_RTN
17535 { 1473, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1473 = GLOBAL_ATOMIC_SWAP_SADDR
17536 { 1474, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1474 = GLOBAL_ATOMIC_SWAP_SADDR_RTN
17537 { 1475, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1475 = GLOBAL_ATOMIC_SWAP_X2
17538 { 1476, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1476 = GLOBAL_ATOMIC_SWAP_X2_RTN
17539 { 1477, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1477 = GLOBAL_ATOMIC_SWAP_X2_SADDR
17540 { 1478, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1478 = GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN
17541 { 1479, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1479 = GLOBAL_ATOMIC_UMAX
17542 { 1480, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1480 = GLOBAL_ATOMIC_UMAX_RTN
17543 { 1481, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1481 = GLOBAL_ATOMIC_UMAX_SADDR
17544 { 1482, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1482 = GLOBAL_ATOMIC_UMAX_SADDR_RTN
17545 { 1483, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1483 = GLOBAL_ATOMIC_UMAX_X2
17546 { 1484, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1484 = GLOBAL_ATOMIC_UMAX_X2_RTN
17547 { 1485, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1485 = GLOBAL_ATOMIC_UMAX_X2_SADDR
17548 { 1486, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1486 = GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN
17549 { 1487, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1487 = GLOBAL_ATOMIC_UMIN
17550 { 1488, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1488 = GLOBAL_ATOMIC_UMIN_RTN
17551 { 1489, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1489 = GLOBAL_ATOMIC_UMIN_SADDR
17552 { 1490, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1490 = GLOBAL_ATOMIC_UMIN_SADDR_RTN
17553 { 1491, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1491 = GLOBAL_ATOMIC_UMIN_X2
17554 { 1492, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1492 = GLOBAL_ATOMIC_UMIN_X2_RTN
17555 { 1493, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1493 = GLOBAL_ATOMIC_UMIN_X2_SADDR
17556 { 1494, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1494 = GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN
17557 { 1495, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1495 = GLOBAL_ATOMIC_XOR
17558 { 1496, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #1496 = GLOBAL_ATOMIC_XOR_RTN
17559 { 1497, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1497 = GLOBAL_ATOMIC_XOR_SADDR
17560 { 1498, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1498 = GLOBAL_ATOMIC_XOR_SADDR_RTN
17561 { 1499, 4, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1499 = GLOBAL_ATOMIC_XOR_X2
17562 { 1500, 5, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1500 = GLOBAL_ATOMIC_XOR_X2_RTN
17563 { 1501, 5, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1501 = GLOBAL_ATOMIC_XOR_X2_SADDR
17564 { 1502, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1502 = GLOBAL_ATOMIC_XOR_X2_SADDR_RTN
17565 { 1503, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1503 = GLOBAL_LOAD_DWORD
17566 { 1504, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1504 = GLOBAL_LOAD_DWORDX2
17567 { 1505, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1505 = GLOBAL_LOAD_DWORDX2_SADDR
17568 { 1506, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #1506 = GLOBAL_LOAD_DWORDX3
17569 { 1507, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1507 = GLOBAL_LOAD_DWORDX3_SADDR
17570 { 1508, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1508 = GLOBAL_LOAD_DWORDX4
17571 { 1509, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #1509 = GLOBAL_LOAD_DWORDX4_SADDR
17572 { 1510, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1510 = GLOBAL_LOAD_DWORD_SADDR
17573 { 1511, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1511 = GLOBAL_LOAD_SBYTE
17574 { 1512, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1512 = GLOBAL_LOAD_SBYTE_D16
17575 { 1513, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1513 = GLOBAL_LOAD_SBYTE_D16_HI
17576 { 1514, 8, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1514 = GLOBAL_LOAD_SBYTE_D16_HI_SADDR
17577 { 1515, 8, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1515 = GLOBAL_LOAD_SBYTE_D16_SADDR
17578 { 1516, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1516 = GLOBAL_LOAD_SBYTE_SADDR
17579 { 1517, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1517 = GLOBAL_LOAD_SHORT_D16
17580 { 1518, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1518 = GLOBAL_LOAD_SHORT_D16_HI
17581 { 1519, 8, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1519 = GLOBAL_LOAD_SHORT_D16_HI_SADDR
17582 { 1520, 8, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1520 = GLOBAL_LOAD_SHORT_D16_SADDR
17583 { 1521, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1521 = GLOBAL_LOAD_SSHORT
17584 { 1522, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1522 = GLOBAL_LOAD_SSHORT_SADDR
17585 { 1523, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1523 = GLOBAL_LOAD_UBYTE
17586 { 1524, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1524 = GLOBAL_LOAD_UBYTE_D16
17587 { 1525, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1525 = GLOBAL_LOAD_UBYTE_D16_HI
17588 { 1526, 8, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1526 = GLOBAL_LOAD_UBYTE_D16_HI_SADDR
17589 { 1527, 8, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1527 = GLOBAL_LOAD_UBYTE_D16_SADDR
17590 { 1528, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1528 = GLOBAL_LOAD_UBYTE_SADDR
17591 { 1529, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1529 = GLOBAL_LOAD_USHORT
17592 { 1530, 7, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1530 = GLOBAL_LOAD_USHORT_SADDR
17593 { 1531, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1531 = GLOBAL_STORE_BYTE
17594 { 1532, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1532 = GLOBAL_STORE_BYTE_D16_HI
17595 { 1533, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1533 = GLOBAL_STORE_BYTE_D16_HI_SADDR
17596 { 1534, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1534 = GLOBAL_STORE_BYTE_SADDR
17597 { 1535, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1535 = GLOBAL_STORE_DWORD
17598 { 1536, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1536 = GLOBAL_STORE_DWORDX2
17599 { 1537, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1537 = GLOBAL_STORE_DWORDX2_SADDR
17600 { 1538, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1538 = GLOBAL_STORE_DWORDX3
17601 { 1539, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1539 = GLOBAL_STORE_DWORDX3_SADDR
17602 { 1540, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #1540 = GLOBAL_STORE_DWORDX4
17603 { 1541, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1541 = GLOBAL_STORE_DWORDX4_SADDR
17604 { 1542, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1542 = GLOBAL_STORE_DWORD_SADDR
17605 { 1543, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1543 = GLOBAL_STORE_SHORT
17606 { 1544, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1544 = GLOBAL_STORE_SHORT_D16_HI
17607 { 1545, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1545 = GLOBAL_STORE_SHORT_D16_HI_SADDR
17608 { 1546, 7, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList2, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1546 = GLOBAL_STORE_SHORT_SADDR
17609 { 1547, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #1547 = G_AMDGPU_ATOMIC_CMPXCHG
17610 { 1548, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #1548 = G_AMDGPU_FFBH_U32
17611 { 1549, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1549 = SCRATCH_LOAD_DWORD
17612 { 1550, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1550 = SCRATCH_LOAD_DWORDX2
17613 { 1551, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1551 = SCRATCH_LOAD_DWORDX2_SADDR
17614 { 1552, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1552 = SCRATCH_LOAD_DWORDX3
17615 { 1553, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1553 = SCRATCH_LOAD_DWORDX3_SADDR
17616 { 1554, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1554 = SCRATCH_LOAD_DWORDX4
17617 { 1555, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1555 = SCRATCH_LOAD_DWORDX4_SADDR
17618 { 1556, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1556 = SCRATCH_LOAD_DWORD_SADDR
17619 { 1557, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1557 = SCRATCH_LOAD_SBYTE
17620 { 1558, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1558 = SCRATCH_LOAD_SBYTE_D16
17621 { 1559, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1559 = SCRATCH_LOAD_SBYTE_D16_HI
17622 { 1560, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1560 = SCRATCH_LOAD_SBYTE_D16_HI_SADDR
17623 { 1561, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1561 = SCRATCH_LOAD_SBYTE_D16_SADDR
17624 { 1562, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1562 = SCRATCH_LOAD_SBYTE_SADDR
17625 { 1563, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1563 = SCRATCH_LOAD_SHORT_D16
17626 { 1564, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1564 = SCRATCH_LOAD_SHORT_D16_HI
17627 { 1565, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1565 = SCRATCH_LOAD_SHORT_D16_HI_SADDR
17628 { 1566, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1566 = SCRATCH_LOAD_SHORT_D16_SADDR
17629 { 1567, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1567 = SCRATCH_LOAD_SSHORT
17630 { 1568, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1568 = SCRATCH_LOAD_SSHORT_SADDR
17631 { 1569, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1569 = SCRATCH_LOAD_UBYTE
17632 { 1570, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1570 = SCRATCH_LOAD_UBYTE_D16
17633 { 1571, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1571 = SCRATCH_LOAD_UBYTE_D16_HI
17634 { 1572, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1572 = SCRATCH_LOAD_UBYTE_D16_HI_SADDR
17635 { 1573, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1573 = SCRATCH_LOAD_UBYTE_D16_SADDR
17636 { 1574, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1574 = SCRATCH_LOAD_UBYTE_SADDR
17637 { 1575, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1575 = SCRATCH_LOAD_USHORT
17638 { 1576, 6, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1576 = SCRATCH_LOAD_USHORT_SADDR
17639 { 1577, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1577 = SCRATCH_STORE_BYTE
17640 { 1578, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1578 = SCRATCH_STORE_BYTE_D16_HI
17641 { 1579, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1579 = SCRATCH_STORE_BYTE_D16_HI_SADDR
17642 { 1580, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1580 = SCRATCH_STORE_BYTE_SADDR
17643 { 1581, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1581 = SCRATCH_STORE_DWORD
17644 { 1582, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1582 = SCRATCH_STORE_DWORDX2
17645 { 1583, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1583 = SCRATCH_STORE_DWORDX2_SADDR
17646 { 1584, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1584 = SCRATCH_STORE_DWORDX3
17647 { 1585, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1585 = SCRATCH_STORE_DWORDX3_SADDR
17648 { 1586, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1586 = SCRATCH_STORE_DWORDX4
17649 { 1587, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1587 = SCRATCH_STORE_DWORDX4_SADDR
17650 { 1588, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1588 = SCRATCH_STORE_DWORD_SADDR
17651 { 1589, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1589 = SCRATCH_STORE_SHORT
17652 { 1590, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1590 = SCRATCH_STORE_SHORT_D16_HI
17653 { 1591, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1591 = SCRATCH_STORE_SHORT_D16_HI_SADDR
17654 { 1592, 6, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8080100200000ULL, ImplicitList5, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1592 = SCRATCH_STORE_SHORT_SADDR
17655 { 1593, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1593 = SI_BR_UNDEF
17656 { 1594, 3, 1, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x1ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1594 = SI_CALL
17657 { 1595, 2, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Convergent), 0x1ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #1595 = SI_CALL_ISEL
17658 { 1596, 4, 1, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo146, -1 ,nullptr }, // Inst #1596 = SI_ELSE
17659 { 1597, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo147, -1 ,nullptr }, // Inst #1597 = SI_END_CF
17660 { 1598, 3, 1, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo148, -1 ,nullptr }, // Inst #1598 = SI_IF
17661 { 1599, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr }, // Inst #1599 = SI_IF_BREAK
17662 { 1600, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList7, OperandInfo7, -1 ,nullptr }, // Inst #1600 = SI_ILLEGAL_COPY
17663 { 1601, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #1601 = SI_INDIRECT_DST_V1
17664 { 1602, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo151, -1 ,nullptr }, // Inst #1602 = SI_INDIRECT_DST_V16
17665 { 1603, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo152, -1 ,nullptr }, // Inst #1603 = SI_INDIRECT_DST_V2
17666 { 1604, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo153, -1 ,nullptr }, // Inst #1604 = SI_INDIRECT_DST_V4
17667 { 1605, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo154, -1 ,nullptr }, // Inst #1605 = SI_INDIRECT_DST_V8
17668 { 1606, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo155, -1 ,nullptr }, // Inst #1606 = SI_INDIRECT_SRC_V1
17669 { 1607, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo156, -1 ,nullptr }, // Inst #1607 = SI_INDIRECT_SRC_V16
17670 { 1608, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo157, -1 ,nullptr }, // Inst #1608 = SI_INDIRECT_SRC_V2
17671 { 1609, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo158, -1 ,nullptr }, // Inst #1609 = SI_INDIRECT_SRC_V4
17672 { 1610, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #1610 = SI_INDIRECT_SRC_V8
17673 { 1611, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList2, OperandInfo3, -1 ,nullptr }, // Inst #1611 = SI_INIT_EXEC
17674 { 1612, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList2, OperandInfo160, -1 ,nullptr }, // Inst #1612 = SI_INIT_EXEC_FROM_INPUT
17675 { 1613, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #1613 = SI_INIT_EXEC_LO
17676 { 1614, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList10, OperandInfo161, -1 ,nullptr }, // Inst #1614 = SI_INIT_M0
17677 { 1615, 3, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, ImplicitList2, ImplicitList11, OperandInfo162, -1 ,nullptr }, // Inst #1615 = SI_KILL_F32_COND_IMM_PSEUDO
17678 { 1616, 3, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList11, OperandInfo162, -1 ,nullptr }, // Inst #1616 = SI_KILL_F32_COND_IMM_TERMINATOR
17679 { 1617, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, ImplicitList2, ImplicitList11, OperandInfo163, -1 ,nullptr }, // Inst #1617 = SI_KILL_I1_PSEUDO
17680 { 1618, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList11, OperandInfo163, -1 ,nullptr }, // Inst #1618 = SI_KILL_I1_TERMINATOR
17681 { 1619, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo164, -1 ,nullptr }, // Inst #1619 = SI_LOOP
17682 { 1620, 0, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1620 = SI_MASKED_UNREACHABLE
17683 { 1621, 1, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000002ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1621 = SI_MASK_BRANCH
17684 { 1622, 2, 0, 12, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo164, -1 ,nullptr }, // Inst #1622 = SI_NON_UNIFORM_BRCOND_PSEUDO
17685 { 1623, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x1ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #1623 = SI_PC_ADD_REL_OFFSET
17686 { 1624, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x1ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1624 = SI_PS_LIVE
17687 { 1625, 0, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1625 = SI_RETURN
17688 { 1626, 0, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x11000000001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1626 = SI_RETURN_TO_EPILOG
17689 { 1627, 6, 2, 252, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1627 = SI_SPILL_A1024_RESTORE
17690 { 1628, 6, 1, 252, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1628 = SI_SPILL_A1024_SAVE
17691 { 1629, 6, 2, 72, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1629 = SI_SPILL_A128_RESTORE
17692 { 1630, 6, 1, 72, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1630 = SI_SPILL_A128_SAVE
17693 { 1631, 6, 2, 24, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1631 = SI_SPILL_A32_RESTORE
17694 { 1632, 6, 1, 24, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1632 = SI_SPILL_A32_SAVE
17695 { 1633, 6, 2, 252, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1633 = SI_SPILL_A512_RESTORE
17696 { 1634, 6, 1, 252, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1634 = SI_SPILL_A512_SAVE
17697 { 1635, 6, 2, 40, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1635 = SI_SPILL_A64_RESTORE
17698 { 1636, 6, 1, 40, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1636 = SI_SPILL_A64_SAVE
17699 { 1637, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1637 = SI_SPILL_S1024_RESTORE
17700 { 1638, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1638 = SI_SPILL_S1024_SAVE
17701 { 1639, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1639 = SI_SPILL_S128_RESTORE
17702 { 1640, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1640 = SI_SPILL_S128_SAVE
17703 { 1641, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1641 = SI_SPILL_S160_RESTORE
17704 { 1642, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1642 = SI_SPILL_S160_SAVE
17705 { 1643, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1643 = SI_SPILL_S256_RESTORE
17706 { 1644, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1644 = SI_SPILL_S256_SAVE
17707 { 1645, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1645 = SI_SPILL_S32_RESTORE
17708 { 1646, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1646 = SI_SPILL_S32_SAVE
17709 { 1647, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1647 = SI_SPILL_S512_RESTORE
17710 { 1648, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1648 = SI_SPILL_S512_SAVE
17711 { 1649, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1649 = SI_SPILL_S64_RESTORE
17712 { 1650, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1650 = SI_SPILL_S64_SAVE
17713 { 1651, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1651 = SI_SPILL_S96_RESTORE
17714 { 1652, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000ULL, ImplicitList2, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1652 = SI_SPILL_S96_SAVE
17715 { 1653, 5, 1, 252, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1653 = SI_SPILL_V1024_RESTORE
17716 { 1654, 5, 0, 252, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1654 = SI_SPILL_V1024_SAVE
17717 { 1655, 5, 1, 40, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1655 = SI_SPILL_V128_RESTORE
17718 { 1656, 5, 0, 40, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1656 = SI_SPILL_V128_SAVE
17719 { 1657, 5, 1, 48, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1657 = SI_SPILL_V160_RESTORE
17720 { 1658, 5, 0, 48, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1658 = SI_SPILL_V160_SAVE
17721 { 1659, 5, 1, 72, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1659 = SI_SPILL_V256_RESTORE
17722 { 1660, 5, 0, 72, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1660 = SI_SPILL_V256_SAVE
17723 { 1661, 5, 1, 16, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1661 = SI_SPILL_V32_RESTORE
17724 { 1662, 5, 0, 16, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1662 = SI_SPILL_V32_SAVE
17725 { 1663, 5, 1, 136, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1663 = SI_SPILL_V512_RESTORE
17726 { 1664, 5, 0, 136, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1664 = SI_SPILL_V512_SAVE
17727 { 1665, 5, 1, 24, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1665 = SI_SPILL_V64_RESTORE
17728 { 1666, 5, 0, 24, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1666 = SI_SPILL_V64_SAVE
17729 { 1667, 5, 1, 32, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1667 = SI_SPILL_V96_RESTORE
17730 { 1668, 5, 0, 32, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x800002ULL, ImplicitList2, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1668 = SI_SPILL_V96_SAVE
17731 { 1669, 3, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Convergent), 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1669 = SI_TCRETURN
17732 { 1670, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #1670 = SOFT_WQM
17733 { 1671, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1671 = S_ABSDIFF_I32
17734 { 1672, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #1672 = S_ABS_I32
17735 { 1673, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1673 = S_ADDC_U32
17736 { 1674, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x21ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #1674 = S_ADDK_I32
17737 { 1675, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1675 = S_ADD_I32
17738 { 1676, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1676 = S_ADD_U32
17739 { 1677, 4, 2, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #1677 = S_ADD_U64_CO_PSEUDO
17740 { 1678, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1678 = S_ADD_U64_PSEUDO
17741 { 1679, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1679 = S_ANDN1_SAVEEXEC_B32
17742 { 1680, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1680 = S_ANDN1_SAVEEXEC_B64
17743 { 1681, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1681 = S_ANDN1_WREXEC_B32
17744 { 1682, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1682 = S_ANDN1_WREXEC_B64
17745 { 1683, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1683 = S_ANDN2_B32
17746 { 1684, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1684 = S_ANDN2_B32_term
17747 { 1685, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1685 = S_ANDN2_B64
17748 { 1686, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1686 = S_ANDN2_B64_term
17749 { 1687, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1687 = S_ANDN2_SAVEEXEC_B32
17750 { 1688, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1688 = S_ANDN2_SAVEEXEC_B64
17751 { 1689, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1689 = S_ANDN2_WREXEC_B32
17752 { 1690, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1690 = S_ANDN2_WREXEC_B64
17753 { 1691, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1691 = S_AND_B32
17754 { 1692, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #1692 = S_AND_B64
17755 { 1693, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #1693 = S_AND_SAVEEXEC_B32
17756 { 1694, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #1694 = S_AND_SAVEEXEC_B64
17757 { 1695, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1695 = S_ASHR_I32
17758 { 1696, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1696 = S_ASHR_I64
17759 { 1697, 3, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x40000ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1697 = S_ATC_PROBE_BUFFER_IMM
17760 { 1698, 3, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x40000ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1698 = S_ATC_PROBE_BUFFER_SGPR
17761 { 1699, 3, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x40000ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1699 = S_ATC_PROBE_IMM
17762 { 1700, 3, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x40000ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1700 = S_ATC_PROBE_SGPR
17763 { 1701, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1701 = S_ATOMIC_ADD_IMM
17764 { 1702, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1702 = S_ATOMIC_ADD_IMM_RTN
17765 { 1703, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1703 = S_ATOMIC_ADD_SGPR
17766 { 1704, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1704 = S_ATOMIC_ADD_SGPR_RTN
17767 { 1705, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1705 = S_ATOMIC_ADD_X2_IMM
17768 { 1706, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1706 = S_ATOMIC_ADD_X2_IMM_RTN
17769 { 1707, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1707 = S_ATOMIC_ADD_X2_SGPR
17770 { 1708, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1708 = S_ATOMIC_ADD_X2_SGPR_RTN
17771 { 1709, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1709 = S_ATOMIC_AND_IMM
17772 { 1710, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1710 = S_ATOMIC_AND_IMM_RTN
17773 { 1711, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1711 = S_ATOMIC_AND_SGPR
17774 { 1712, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1712 = S_ATOMIC_AND_SGPR_RTN
17775 { 1713, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1713 = S_ATOMIC_AND_X2_IMM
17776 { 1714, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1714 = S_ATOMIC_AND_X2_IMM_RTN
17777 { 1715, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1715 = S_ATOMIC_AND_X2_SGPR
17778 { 1716, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1716 = S_ATOMIC_AND_X2_SGPR_RTN
17779 { 1717, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1717 = S_ATOMIC_CMPSWAP_IMM
17780 { 1718, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1718 = S_ATOMIC_CMPSWAP_IMM_RTN
17781 { 1719, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1719 = S_ATOMIC_CMPSWAP_SGPR
17782 { 1720, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1720 = S_ATOMIC_CMPSWAP_SGPR_RTN
17783 { 1721, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1721 = S_ATOMIC_CMPSWAP_X2_IMM
17784 { 1722, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1722 = S_ATOMIC_CMPSWAP_X2_IMM_RTN
17785 { 1723, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1723 = S_ATOMIC_CMPSWAP_X2_SGPR
17786 { 1724, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1724 = S_ATOMIC_CMPSWAP_X2_SGPR_RTN
17787 { 1725, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1725 = S_ATOMIC_DEC_IMM
17788 { 1726, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1726 = S_ATOMIC_DEC_IMM_RTN
17789 { 1727, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1727 = S_ATOMIC_DEC_SGPR
17790 { 1728, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1728 = S_ATOMIC_DEC_SGPR_RTN
17791 { 1729, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1729 = S_ATOMIC_DEC_X2_IMM
17792 { 1730, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1730 = S_ATOMIC_DEC_X2_IMM_RTN
17793 { 1731, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1731 = S_ATOMIC_DEC_X2_SGPR
17794 { 1732, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1732 = S_ATOMIC_DEC_X2_SGPR_RTN
17795 { 1733, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1733 = S_ATOMIC_INC_IMM
17796 { 1734, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1734 = S_ATOMIC_INC_IMM_RTN
17797 { 1735, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1735 = S_ATOMIC_INC_SGPR
17798 { 1736, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1736 = S_ATOMIC_INC_SGPR_RTN
17799 { 1737, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1737 = S_ATOMIC_INC_X2_IMM
17800 { 1738, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1738 = S_ATOMIC_INC_X2_IMM_RTN
17801 { 1739, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1739 = S_ATOMIC_INC_X2_SGPR
17802 { 1740, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1740 = S_ATOMIC_INC_X2_SGPR_RTN
17803 { 1741, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1741 = S_ATOMIC_OR_IMM
17804 { 1742, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1742 = S_ATOMIC_OR_IMM_RTN
17805 { 1743, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1743 = S_ATOMIC_OR_SGPR
17806 { 1744, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1744 = S_ATOMIC_OR_SGPR_RTN
17807 { 1745, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1745 = S_ATOMIC_OR_X2_IMM
17808 { 1746, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1746 = S_ATOMIC_OR_X2_IMM_RTN
17809 { 1747, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1747 = S_ATOMIC_OR_X2_SGPR
17810 { 1748, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1748 = S_ATOMIC_OR_X2_SGPR_RTN
17811 { 1749, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1749 = S_ATOMIC_SMAX_IMM
17812 { 1750, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1750 = S_ATOMIC_SMAX_IMM_RTN
17813 { 1751, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1751 = S_ATOMIC_SMAX_SGPR
17814 { 1752, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1752 = S_ATOMIC_SMAX_SGPR_RTN
17815 { 1753, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1753 = S_ATOMIC_SMAX_X2_IMM
17816 { 1754, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1754 = S_ATOMIC_SMAX_X2_IMM_RTN
17817 { 1755, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1755 = S_ATOMIC_SMAX_X2_SGPR
17818 { 1756, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1756 = S_ATOMIC_SMAX_X2_SGPR_RTN
17819 { 1757, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1757 = S_ATOMIC_SMIN_IMM
17820 { 1758, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1758 = S_ATOMIC_SMIN_IMM_RTN
17821 { 1759, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1759 = S_ATOMIC_SMIN_SGPR
17822 { 1760, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1760 = S_ATOMIC_SMIN_SGPR_RTN
17823 { 1761, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1761 = S_ATOMIC_SMIN_X2_IMM
17824 { 1762, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1762 = S_ATOMIC_SMIN_X2_IMM_RTN
17825 { 1763, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1763 = S_ATOMIC_SMIN_X2_SGPR
17826 { 1764, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1764 = S_ATOMIC_SMIN_X2_SGPR_RTN
17827 { 1765, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1765 = S_ATOMIC_SUB_IMM
17828 { 1766, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1766 = S_ATOMIC_SUB_IMM_RTN
17829 { 1767, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1767 = S_ATOMIC_SUB_SGPR
17830 { 1768, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1768 = S_ATOMIC_SUB_SGPR_RTN
17831 { 1769, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1769 = S_ATOMIC_SUB_X2_IMM
17832 { 1770, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1770 = S_ATOMIC_SUB_X2_IMM_RTN
17833 { 1771, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1771 = S_ATOMIC_SUB_X2_SGPR
17834 { 1772, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1772 = S_ATOMIC_SUB_X2_SGPR_RTN
17835 { 1773, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1773 = S_ATOMIC_SWAP_IMM
17836 { 1774, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1774 = S_ATOMIC_SWAP_IMM_RTN
17837 { 1775, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1775 = S_ATOMIC_SWAP_SGPR
17838 { 1776, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1776 = S_ATOMIC_SWAP_SGPR_RTN
17839 { 1777, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1777 = S_ATOMIC_SWAP_X2_IMM
17840 { 1778, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1778 = S_ATOMIC_SWAP_X2_IMM_RTN
17841 { 1779, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1779 = S_ATOMIC_SWAP_X2_SGPR
17842 { 1780, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1780 = S_ATOMIC_SWAP_X2_SGPR_RTN
17843 { 1781, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1781 = S_ATOMIC_UMAX_IMM
17844 { 1782, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1782 = S_ATOMIC_UMAX_IMM_RTN
17845 { 1783, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1783 = S_ATOMIC_UMAX_SGPR
17846 { 1784, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1784 = S_ATOMIC_UMAX_SGPR_RTN
17847 { 1785, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1785 = S_ATOMIC_UMAX_X2_IMM
17848 { 1786, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1786 = S_ATOMIC_UMAX_X2_IMM_RTN
17849 { 1787, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1787 = S_ATOMIC_UMAX_X2_SGPR
17850 { 1788, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1788 = S_ATOMIC_UMAX_X2_SGPR_RTN
17851 { 1789, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1789 = S_ATOMIC_UMIN_IMM
17852 { 1790, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1790 = S_ATOMIC_UMIN_IMM_RTN
17853 { 1791, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1791 = S_ATOMIC_UMIN_SGPR
17854 { 1792, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1792 = S_ATOMIC_UMIN_SGPR_RTN
17855 { 1793, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1793 = S_ATOMIC_UMIN_X2_IMM
17856 { 1794, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1794 = S_ATOMIC_UMIN_X2_IMM_RTN
17857 { 1795, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1795 = S_ATOMIC_UMIN_X2_SGPR
17858 { 1796, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1796 = S_ATOMIC_UMIN_X2_SGPR_RTN
17859 { 1797, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1797 = S_ATOMIC_XOR_IMM
17860 { 1798, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1798 = S_ATOMIC_XOR_IMM_RTN
17861 { 1799, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1799 = S_ATOMIC_XOR_SGPR
17862 { 1800, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1800 = S_ATOMIC_XOR_SGPR_RTN
17863 { 1801, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1801 = S_ATOMIC_XOR_X2_IMM
17864 { 1802, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1802 = S_ATOMIC_XOR_X2_IMM_RTN
17865 { 1803, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1803 = S_ATOMIC_XOR_X2_SGPR
17866 { 1804, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1804 = S_ATOMIC_XOR_X2_SGPR_RTN
17867 { 1805, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #1805 = S_BCNT0_I32_B32
17868 { 1806, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo216, -1 ,nullptr }, // Inst #1806 = S_BCNT0_I32_B64
17869 { 1807, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #1807 = S_BCNT1_I32_B32
17870 { 1808, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo216, -1 ,nullptr }, // Inst #1808 = S_BCNT1_I32_B64
17871 { 1809, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1809 = S_BFE_I32
17872 { 1810, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1810 = S_BFE_I64
17873 { 1811, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1811 = S_BFE_U32
17874 { 1812, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1812 = S_BFE_U64
17875 { 1813, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1813 = S_BFM_B32
17876 { 1814, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1814 = S_BFM_B64
17877 { 1815, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1815 = S_BITREPLICATE_B64_B32
17878 { 1816, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1816 = S_BITSET0_B32
17879 { 1817, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1817 = S_BITSET0_B64
17880 { 1818, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1818 = S_BITSET1_B32
17881 { 1819, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1819 = S_BITSET1_B64
17882 { 1820, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1820 = S_BREV_B32
17883 { 1821, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1821 = S_BREV_B64
17884 { 1822, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1822 = S_BUFFER_ATOMIC_ADD_IMM
17885 { 1823, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1823 = S_BUFFER_ATOMIC_ADD_IMM_RTN
17886 { 1824, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1824 = S_BUFFER_ATOMIC_ADD_SGPR
17887 { 1825, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1825 = S_BUFFER_ATOMIC_ADD_SGPR_RTN
17888 { 1826, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1826 = S_BUFFER_ATOMIC_ADD_X2_IMM
17889 { 1827, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1827 = S_BUFFER_ATOMIC_ADD_X2_IMM_RTN
17890 { 1828, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1828 = S_BUFFER_ATOMIC_ADD_X2_SGPR
17891 { 1829, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1829 = S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN
17892 { 1830, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1830 = S_BUFFER_ATOMIC_AND_IMM
17893 { 1831, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1831 = S_BUFFER_ATOMIC_AND_IMM_RTN
17894 { 1832, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1832 = S_BUFFER_ATOMIC_AND_SGPR
17895 { 1833, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1833 = S_BUFFER_ATOMIC_AND_SGPR_RTN
17896 { 1834, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1834 = S_BUFFER_ATOMIC_AND_X2_IMM
17897 { 1835, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1835 = S_BUFFER_ATOMIC_AND_X2_IMM_RTN
17898 { 1836, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1836 = S_BUFFER_ATOMIC_AND_X2_SGPR
17899 { 1837, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1837 = S_BUFFER_ATOMIC_AND_X2_SGPR_RTN
17900 { 1838, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1838 = S_BUFFER_ATOMIC_CMPSWAP_IMM
17901 { 1839, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1839 = S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN
17902 { 1840, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1840 = S_BUFFER_ATOMIC_CMPSWAP_SGPR
17903 { 1841, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1841 = S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN
17904 { 1842, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1842 = S_BUFFER_ATOMIC_CMPSWAP_X2_IMM
17905 { 1843, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1843 = S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN
17906 { 1844, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1844 = S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR
17907 { 1845, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1845 = S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN
17908 { 1846, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1846 = S_BUFFER_ATOMIC_DEC_IMM
17909 { 1847, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1847 = S_BUFFER_ATOMIC_DEC_IMM_RTN
17910 { 1848, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1848 = S_BUFFER_ATOMIC_DEC_SGPR
17911 { 1849, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1849 = S_BUFFER_ATOMIC_DEC_SGPR_RTN
17912 { 1850, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1850 = S_BUFFER_ATOMIC_DEC_X2_IMM
17913 { 1851, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1851 = S_BUFFER_ATOMIC_DEC_X2_IMM_RTN
17914 { 1852, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1852 = S_BUFFER_ATOMIC_DEC_X2_SGPR
17915 { 1853, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1853 = S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN
17916 { 1854, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1854 = S_BUFFER_ATOMIC_INC_IMM
17917 { 1855, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1855 = S_BUFFER_ATOMIC_INC_IMM_RTN
17918 { 1856, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1856 = S_BUFFER_ATOMIC_INC_SGPR
17919 { 1857, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1857 = S_BUFFER_ATOMIC_INC_SGPR_RTN
17920 { 1858, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1858 = S_BUFFER_ATOMIC_INC_X2_IMM
17921 { 1859, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1859 = S_BUFFER_ATOMIC_INC_X2_IMM_RTN
17922 { 1860, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1860 = S_BUFFER_ATOMIC_INC_X2_SGPR
17923 { 1861, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1861 = S_BUFFER_ATOMIC_INC_X2_SGPR_RTN
17924 { 1862, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1862 = S_BUFFER_ATOMIC_OR_IMM
17925 { 1863, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1863 = S_BUFFER_ATOMIC_OR_IMM_RTN
17926 { 1864, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1864 = S_BUFFER_ATOMIC_OR_SGPR
17927 { 1865, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1865 = S_BUFFER_ATOMIC_OR_SGPR_RTN
17928 { 1866, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1866 = S_BUFFER_ATOMIC_OR_X2_IMM
17929 { 1867, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1867 = S_BUFFER_ATOMIC_OR_X2_IMM_RTN
17930 { 1868, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1868 = S_BUFFER_ATOMIC_OR_X2_SGPR
17931 { 1869, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1869 = S_BUFFER_ATOMIC_OR_X2_SGPR_RTN
17932 { 1870, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1870 = S_BUFFER_ATOMIC_SMAX_IMM
17933 { 1871, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1871 = S_BUFFER_ATOMIC_SMAX_IMM_RTN
17934 { 1872, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1872 = S_BUFFER_ATOMIC_SMAX_SGPR
17935 { 1873, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1873 = S_BUFFER_ATOMIC_SMAX_SGPR_RTN
17936 { 1874, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1874 = S_BUFFER_ATOMIC_SMAX_X2_IMM
17937 { 1875, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1875 = S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN
17938 { 1876, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1876 = S_BUFFER_ATOMIC_SMAX_X2_SGPR
17939 { 1877, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1877 = S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN
17940 { 1878, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1878 = S_BUFFER_ATOMIC_SMIN_IMM
17941 { 1879, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1879 = S_BUFFER_ATOMIC_SMIN_IMM_RTN
17942 { 1880, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1880 = S_BUFFER_ATOMIC_SMIN_SGPR
17943 { 1881, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1881 = S_BUFFER_ATOMIC_SMIN_SGPR_RTN
17944 { 1882, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1882 = S_BUFFER_ATOMIC_SMIN_X2_IMM
17945 { 1883, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1883 = S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN
17946 { 1884, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1884 = S_BUFFER_ATOMIC_SMIN_X2_SGPR
17947 { 1885, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1885 = S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN
17948 { 1886, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1886 = S_BUFFER_ATOMIC_SUB_IMM
17949 { 1887, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1887 = S_BUFFER_ATOMIC_SUB_IMM_RTN
17950 { 1888, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1888 = S_BUFFER_ATOMIC_SUB_SGPR
17951 { 1889, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1889 = S_BUFFER_ATOMIC_SUB_SGPR_RTN
17952 { 1890, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1890 = S_BUFFER_ATOMIC_SUB_X2_IMM
17953 { 1891, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1891 = S_BUFFER_ATOMIC_SUB_X2_IMM_RTN
17954 { 1892, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1892 = S_BUFFER_ATOMIC_SUB_X2_SGPR
17955 { 1893, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1893 = S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN
17956 { 1894, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1894 = S_BUFFER_ATOMIC_SWAP_IMM
17957 { 1895, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1895 = S_BUFFER_ATOMIC_SWAP_IMM_RTN
17958 { 1896, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1896 = S_BUFFER_ATOMIC_SWAP_SGPR
17959 { 1897, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1897 = S_BUFFER_ATOMIC_SWAP_SGPR_RTN
17960 { 1898, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1898 = S_BUFFER_ATOMIC_SWAP_X2_IMM
17961 { 1899, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1899 = S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN
17962 { 1900, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1900 = S_BUFFER_ATOMIC_SWAP_X2_SGPR
17963 { 1901, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1901 = S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN
17964 { 1902, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1902 = S_BUFFER_ATOMIC_UMAX_IMM
17965 { 1903, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1903 = S_BUFFER_ATOMIC_UMAX_IMM_RTN
17966 { 1904, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1904 = S_BUFFER_ATOMIC_UMAX_SGPR
17967 { 1905, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1905 = S_BUFFER_ATOMIC_UMAX_SGPR_RTN
17968 { 1906, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1906 = S_BUFFER_ATOMIC_UMAX_X2_IMM
17969 { 1907, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1907 = S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN
17970 { 1908, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1908 = S_BUFFER_ATOMIC_UMAX_X2_SGPR
17971 { 1909, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1909 = S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN
17972 { 1910, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1910 = S_BUFFER_ATOMIC_UMIN_IMM
17973 { 1911, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1911 = S_BUFFER_ATOMIC_UMIN_IMM_RTN
17974 { 1912, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1912 = S_BUFFER_ATOMIC_UMIN_SGPR
17975 { 1913, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1913 = S_BUFFER_ATOMIC_UMIN_SGPR_RTN
17976 { 1914, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1914 = S_BUFFER_ATOMIC_UMIN_X2_IMM
17977 { 1915, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1915 = S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN
17978 { 1916, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1916 = S_BUFFER_ATOMIC_UMIN_X2_SGPR
17979 { 1917, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1917 = S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN
17980 { 1918, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1918 = S_BUFFER_ATOMIC_XOR_IMM
17981 { 1919, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1919 = S_BUFFER_ATOMIC_XOR_IMM_RTN
17982 { 1920, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1920 = S_BUFFER_ATOMIC_XOR_SGPR
17983 { 1921, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1921 = S_BUFFER_ATOMIC_XOR_SGPR_RTN
17984 { 1922, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1922 = S_BUFFER_ATOMIC_XOR_X2_IMM
17985 { 1923, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1923 = S_BUFFER_ATOMIC_XOR_X2_IMM_RTN
17986 { 1924, 4, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1924 = S_BUFFER_ATOMIC_XOR_X2_SGPR
17987 { 1925, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x88400040000ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1925 = S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN
17988 { 1926, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1926 = S_BUFFER_LOAD_DWORDX16_IMM
17989 { 1927, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1927 = S_BUFFER_LOAD_DWORDX16_SGPR
17990 { 1928, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1928 = S_BUFFER_LOAD_DWORDX2_IMM
17991 { 1929, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1929 = S_BUFFER_LOAD_DWORDX2_SGPR
17992 { 1930, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1930 = S_BUFFER_LOAD_DWORDX4_IMM
17993 { 1931, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1931 = S_BUFFER_LOAD_DWORDX4_SGPR
17994 { 1932, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1932 = S_BUFFER_LOAD_DWORDX8_IMM
17995 { 1933, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1933 = S_BUFFER_LOAD_DWORDX8_SGPR
17996 { 1934, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1934 = S_BUFFER_LOAD_DWORD_IMM
17997 { 1935, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1935 = S_BUFFER_LOAD_DWORD_SGPR
17998 { 1936, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1936 = S_BUFFER_STORE_DWORDX2_IMM
17999 { 1937, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1937 = S_BUFFER_STORE_DWORDX2_SGPR
18000 { 1938, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1938 = S_BUFFER_STORE_DWORDX4_IMM
18001 { 1939, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1939 = S_BUFFER_STORE_DWORDX4_SGPR
18002 { 1940, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1940 = S_BUFFER_STORE_DWORD_IMM
18003 { 1941, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1941 = S_BUFFER_STORE_DWORD_SGPR
18004 { 1942, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x21ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1942 = S_CALL_B64
18005 { 1943, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1943 = S_CBRANCH_G_FORK
18006 { 1944, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x21ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1944 = S_CBRANCH_I_FORK
18007 { 1945, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #1945 = S_CBRANCH_JOIN
18008 { 1946, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x21ULL, ImplicitList1, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1946 = S_CMOVK_I32
18009 { 1947, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm), 0x5ULL, ImplicitList1, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1947 = S_CMOV_B32
18010 { 1948, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm), 0x5ULL, ImplicitList1, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1948 = S_CMOV_B64
18011 { 1949, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1949 = S_CMPK_EQ_I32
18012 { 1950, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1950 = S_CMPK_EQ_U32
18013 { 1951, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1951 = S_CMPK_GE_I32
18014 { 1952, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1952 = S_CMPK_GE_U32
18015 { 1953, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1953 = S_CMPK_GT_I32
18016 { 1954, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1954 = S_CMPK_GT_U32
18017 { 1955, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1955 = S_CMPK_LE_I32
18018 { 1956, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1956 = S_CMPK_LE_U32
18019 { 1957, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1957 = S_CMPK_LG_I32
18020 { 1958, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1958 = S_CMPK_LG_U32
18021 { 1959, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x21ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1959 = S_CMPK_LT_I32
18022 { 1960, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x4000000021ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #1960 = S_CMPK_LT_U32
18023 { 1961, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1961 = S_CSELECT_B32
18024 { 1962, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1962 = S_CSELECT_B64
18025 { 1963, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1963 = S_DCACHE_DISCARD_IMM
18026 { 1964, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1964 = S_DCACHE_DISCARD_SGPR
18027 { 1965, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1965 = S_DCACHE_DISCARD_X2_IMM
18028 { 1966, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1966 = S_DCACHE_DISCARD_X2_SGPR
18029 { 1967, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1967 = S_DCACHE_INV
18030 { 1968, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1968 = S_DCACHE_INV_VOL
18031 { 1969, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1969 = S_DCACHE_WB
18032 { 1970, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1970 = S_DCACHE_WB_VOL
18033 { 1971, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1971 = S_FF0_I32_B32
18034 { 1972, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1972 = S_FF0_I32_B64
18035 { 1973, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1973 = S_FF1_I32_B32
18036 { 1974, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1974 = S_FF1_I32_B64
18037 { 1975, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1975 = S_FLBIT_I32
18038 { 1976, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1976 = S_FLBIT_I32_B32
18039 { 1977, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1977 = S_FLBIT_I32_B64
18040 { 1978, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1978 = S_FLBIT_I32_I64
18041 { 1979, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1979 = S_GETPC_B64
18042 { 1980, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1980 = S_GETREG_B32
18043 { 1981, 1, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1981 = S_GET_WAVEID_IN_WORKGROUP
18044 { 1982, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1982 = S_GL1_INV
18045 { 1983, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1983 = S_LOAD_DWORDX16_IMM
18046 { 1984, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #1984 = S_LOAD_DWORDX16_SGPR
18047 { 1985, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1985 = S_LOAD_DWORDX2_IMM
18048 { 1986, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1986 = S_LOAD_DWORDX2_SGPR
18049 { 1987, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1987 = S_LOAD_DWORDX4_IMM
18050 { 1988, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1988 = S_LOAD_DWORDX4_SGPR
18051 { 1989, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1989 = S_LOAD_DWORDX8_IMM
18052 { 1990, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1990 = S_LOAD_DWORDX8_SGPR
18053 { 1991, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1991 = S_LOAD_DWORD_IMM
18054 { 1992, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1992 = S_LOAD_DWORD_SGPR
18055 { 1993, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1993 = S_LSHL1_ADD_U32
18056 { 1994, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1994 = S_LSHL2_ADD_U32
18057 { 1995, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1995 = S_LSHL3_ADD_U32
18058 { 1996, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1996 = S_LSHL4_ADD_U32
18059 { 1997, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1997 = S_LSHL_B32
18060 { 1998, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #1998 = S_LSHL_B64
18061 { 1999, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #1999 = S_LSHR_B32
18062 { 2000, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo199, -1 ,nullptr }, // Inst #2000 = S_LSHR_B64
18063 { 2001, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2001 = S_MAX_I32
18064 { 2002, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2002 = S_MAX_U32
18065 { 2003, 1, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2003 = S_MEMREALTIME
18066 { 2004, 1, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400040000ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2004 = S_MEMTIME
18067 { 2005, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2005 = S_MIN_I32
18068 { 2006, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2006 = S_MIN_U32
18069 { 2007, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2007 = S_MOVK_I32
18070 { 2008, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, ImplicitList10, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2008 = S_MOVRELD_B32
18071 { 2009, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, ImplicitList10, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2009 = S_MOVRELD_B64
18072 { 2010, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, ImplicitList10, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2010 = S_MOVRELSD_2_B32
18073 { 2011, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, ImplicitList10, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2011 = S_MOVRELS_B32
18074 { 2012, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, ImplicitList10, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2012 = S_MOVRELS_B64
18075 { 2013, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2013 = S_MOV_B32
18076 { 2014, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2014 = S_MOV_B32_term
18077 { 2015, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2015 = S_MOV_B64
18078 { 2016, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2016 = S_MOV_B64_term
18079 { 2017, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2017 = S_MOV_FED_B32
18080 { 2018, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2018 = S_MOV_REGRD_B32
18081 { 2019, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x21ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #2019 = S_MULK_I32
18082 { 2020, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2020 = S_MUL_HI_I32
18083 { 2021, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2021 = S_MUL_HI_U32
18084 { 2022, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2022 = S_MUL_I32
18085 { 2023, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2023 = S_NAND_B32
18086 { 2024, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2024 = S_NAND_B64
18087 { 2025, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2025 = S_NAND_SAVEEXEC_B32
18088 { 2026, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2026 = S_NAND_SAVEEXEC_B64
18089 { 2027, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2027 = S_NOR_B32
18090 { 2028, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2028 = S_NOR_B64
18091 { 2029, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2029 = S_NOR_SAVEEXEC_B32
18092 { 2030, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2030 = S_NOR_SAVEEXEC_B64
18093 { 2031, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #2031 = S_NOT_B32
18094 { 2032, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo198, -1 ,nullptr }, // Inst #2032 = S_NOT_B64
18095 { 2033, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2033 = S_ORN1_SAVEEXEC_B32
18096 { 2034, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2034 = S_ORN1_SAVEEXEC_B64
18097 { 2035, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2035 = S_ORN2_B32
18098 { 2036, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2036 = S_ORN2_B64
18099 { 2037, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2037 = S_ORN2_SAVEEXEC_B32
18100 { 2038, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2038 = S_ORN2_SAVEEXEC_B64
18101 { 2039, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2039 = S_OR_B32
18102 { 2040, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2040 = S_OR_B32_term
18103 { 2041, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2041 = S_OR_B64
18104 { 2042, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2042 = S_OR_SAVEEXEC_B32
18105 { 2043, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2043 = S_OR_SAVEEXEC_B64
18106 { 2044, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2044 = S_PACK_HH_B32_B16
18107 { 2045, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2045 = S_PACK_LH_B32_B16
18108 { 2046, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2046 = S_PACK_LL_B32_B16
18109 { 2047, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2047 = S_QUADMASK_B32
18110 { 2048, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2048 = S_QUADMASK_B64
18111 { 2049, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2049 = S_RFE_B64
18112 { 2050, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2050 = S_RFE_RESTORE_B64
18113 { 2051, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2051 = S_SCRATCH_LOAD_DWORDX2_IMM
18114 { 2052, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2052 = S_SCRATCH_LOAD_DWORDX2_SGPR
18115 { 2053, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2053 = S_SCRATCH_LOAD_DWORDX4_IMM
18116 { 2054, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2054 = S_SCRATCH_LOAD_DWORDX4_SGPR
18117 { 2055, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2055 = S_SCRATCH_LOAD_DWORD_IMM
18118 { 2056, 5, 1, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x400040000ULL, ImplicitList12, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2056 = S_SCRATCH_LOAD_DWORD_SGPR
18119 { 2057, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2057 = S_SCRATCH_STORE_DWORDX2_IMM
18120 { 2058, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2058 = S_SCRATCH_STORE_DWORDX2_SGPR
18121 { 2059, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2059 = S_SCRATCH_STORE_DWORDX4_IMM
18122 { 2060, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2060 = S_SCRATCH_STORE_DWORDX4_SGPR
18123 { 2061, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2061 = S_SCRATCH_STORE_DWORD_IMM
18124 { 2062, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, ImplicitList12, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2062 = S_SCRATCH_STORE_DWORD_SGPR
18125 { 2063, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2063 = S_SETPC_B64
18126 { 2064, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2064 = S_SETPC_B64_return
18127 { 2065, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2065 = S_SETREG_B32
18128 { 2066, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #2066 = S_SETREG_IMM32_B32
18129 { 2067, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, ImplicitList10, ImplicitList10, OperandInfo161, -1 ,nullptr }, // Inst #2067 = S_SET_GPR_IDX_IDX
18130 { 2068, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2068 = S_SEXT_I32_I16
18131 { 2069, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2069 = S_SEXT_I32_I8
18132 { 2070, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2070 = S_STORE_DWORDX2_IMM
18133 { 2071, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2071 = S_STORE_DWORDX2_SGPR
18134 { 2072, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2072 = S_STORE_DWORDX4_IMM
18135 { 2073, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2073 = S_STORE_DWORDX4_SGPR
18136 { 2074, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2074 = S_STORE_DWORD_IMM
18137 { 2075, 5, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8400040000ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2075 = S_STORE_DWORD_SGPR
18138 { 2076, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, ImplicitList1, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2076 = S_SUBB_U32
18139 { 2077, 2, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL, ImplicitList2, ImplicitList2, OperandInfo261, -1 ,nullptr }, // Inst #2077 = S_SUBVECTOR_LOOP_BEGIN
18140 { 2078, 2, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL, ImplicitList2, ImplicitList2, OperandInfo261, -1 ,nullptr }, // Inst #2078 = S_SUBVECTOR_LOOP_END
18141 { 2079, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2079 = S_SUB_I32
18142 { 2080, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2080 = S_SUB_U32
18143 { 2081, 4, 2, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #2081 = S_SUB_U64_CO_PSEUDO
18144 { 2082, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2082 = S_SUB_U64_PSEUDO
18145 { 2083, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2083 = S_SWAPPC_B64
18146 { 2084, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x21ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2084 = S_VERSION
18147 { 2085, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2085 = S_WAITCNT_EXPCNT
18148 { 2086, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2086 = S_WAITCNT_LGKMCNT
18149 { 2087, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2087 = S_WAITCNT_VMCNT
18150 { 2088, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2088 = S_WAITCNT_VSCNT
18151 { 2089, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #2089 = S_WQM_B32
18152 { 2090, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x5ULL, nullptr, ImplicitList1, OperandInfo198, -1 ,nullptr }, // Inst #2090 = S_WQM_B64
18153 { 2091, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2091 = S_XNOR_B32
18154 { 2092, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2092 = S_XNOR_B64
18155 { 2093, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2093 = S_XNOR_SAVEEXEC_B32
18156 { 2094, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2094 = S_XNOR_SAVEEXEC_B64
18157 { 2095, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2095 = S_XOR_B32
18158 { 2096, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr }, // Inst #2096 = S_XOR_B32_term
18159 { 2097, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x9ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2097 = S_XOR_B64
18160 { 2098, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, ImplicitList1, OperandInfo197, -1 ,nullptr }, // Inst #2098 = S_XOR_B64_term
18161 { 2099, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo194, -1 ,nullptr }, // Inst #2099 = S_XOR_SAVEEXEC_B32
18162 { 2100, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, ImplicitList2, ImplicitList6, OperandInfo198, -1 ,nullptr }, // Inst #2100 = S_XOR_SAVEEXEC_B64
18163 { 2101, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2101 = TBUFFER_LOAD_FORMAT_D16_XYZW_ADDR64
18164 { 2102, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2102 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN
18165 { 2103, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2103 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_exact
18166 { 2104, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2104 = TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN
18167 { 2105, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2105 = TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_exact
18168 { 2106, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2106 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN
18169 { 2107, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2107 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_exact
18170 { 2108, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2108 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET
18171 { 2109, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2109 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_exact
18172 { 2110, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2110 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_ADDR64
18173 { 2111, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2111 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN
18174 { 2112, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2112 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_exact
18175 { 2113, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2113 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN
18176 { 2114, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2114 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_exact
18177 { 2115, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2115 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN
18178 { 2116, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2116 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_exact
18179 { 2117, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2117 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET
18180 { 2118, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2118 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact
18181 { 2119, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2119 = TBUFFER_LOAD_FORMAT_D16_XYZ_ADDR64
18182 { 2120, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2120 = TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN
18183 { 2121, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2121 = TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_exact
18184 { 2122, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2122 = TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN
18185 { 2123, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2123 = TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_exact
18186 { 2124, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2124 = TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN
18187 { 2125, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2125 = TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_exact
18188 { 2126, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2126 = TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET
18189 { 2127, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2127 = TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_exact
18190 { 2128, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2128 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_ADDR64
18191 { 2129, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2129 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN
18192 { 2130, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2130 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_exact
18193 { 2131, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2131 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN
18194 { 2132, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2132 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_exact
18195 { 2133, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2133 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN
18196 { 2134, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2134 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_exact
18197 { 2135, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2135 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET
18198 { 2136, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2136 = TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact
18199 { 2137, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2137 = TBUFFER_LOAD_FORMAT_D16_XY_ADDR64
18200 { 2138, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2138 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN
18201 { 2139, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2139 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact
18202 { 2140, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2140 = TBUFFER_LOAD_FORMAT_D16_XY_IDXEN
18203 { 2141, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2141 = TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_exact
18204 { 2142, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2142 = TBUFFER_LOAD_FORMAT_D16_XY_OFFEN
18205 { 2143, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2143 = TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_exact
18206 { 2144, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2144 = TBUFFER_LOAD_FORMAT_D16_XY_OFFSET
18207 { 2145, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2145 = TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_exact
18208 { 2146, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2146 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_ADDR64
18209 { 2147, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2147 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN
18210 { 2148, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2148 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_exact
18211 { 2149, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2149 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN
18212 { 2150, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2150 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_exact
18213 { 2151, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2151 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN
18214 { 2152, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2152 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_exact
18215 { 2153, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2153 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET
18216 { 2154, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2154 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_exact
18217 { 2155, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2155 = TBUFFER_LOAD_FORMAT_D16_X_ADDR64
18218 { 2156, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2156 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN
18219 { 2157, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2157 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact
18220 { 2158, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2158 = TBUFFER_LOAD_FORMAT_D16_X_IDXEN
18221 { 2159, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2159 = TBUFFER_LOAD_FORMAT_D16_X_IDXEN_exact
18222 { 2160, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2160 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN
18223 { 2161, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2161 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN_exact
18224 { 2162, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2162 = TBUFFER_LOAD_FORMAT_D16_X_OFFSET
18225 { 2163, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2163 = TBUFFER_LOAD_FORMAT_D16_X_OFFSET_exact
18226 { 2164, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2164 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64
18227 { 2165, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2165 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN
18228 { 2166, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2166 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact
18229 { 2167, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2167 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN
18230 { 2168, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2168 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_exact
18231 { 2169, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2169 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN
18232 { 2170, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2170 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_exact
18233 { 2171, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2171 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET
18234 { 2172, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2172 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_exact
18235 { 2173, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2173 = TBUFFER_LOAD_FORMAT_XYZW_ADDR64
18236 { 2174, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2174 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN
18237 { 2175, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2175 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact
18238 { 2176, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2176 = TBUFFER_LOAD_FORMAT_XYZW_IDXEN
18239 { 2177, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2177 = TBUFFER_LOAD_FORMAT_XYZW_IDXEN_exact
18240 { 2178, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2178 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN
18241 { 2179, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2179 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN_exact
18242 { 2180, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2180 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET
18243 { 2181, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2181 = TBUFFER_LOAD_FORMAT_XYZW_OFFSET_exact
18244 { 2182, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2182 = TBUFFER_LOAD_FORMAT_XYZ_ADDR64
18245 { 2183, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2183 = TBUFFER_LOAD_FORMAT_XYZ_BOTHEN
18246 { 2184, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2184 = TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact
18247 { 2185, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2185 = TBUFFER_LOAD_FORMAT_XYZ_IDXEN
18248 { 2186, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2186 = TBUFFER_LOAD_FORMAT_XYZ_IDXEN_exact
18249 { 2187, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2187 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN
18250 { 2188, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2188 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN_exact
18251 { 2189, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2189 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET
18252 { 2190, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2190 = TBUFFER_LOAD_FORMAT_XYZ_OFFSET_exact
18253 { 2191, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2191 = TBUFFER_LOAD_FORMAT_XY_ADDR64
18254 { 2192, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2192 = TBUFFER_LOAD_FORMAT_XY_BOTHEN
18255 { 2193, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2193 = TBUFFER_LOAD_FORMAT_XY_BOTHEN_exact
18256 { 2194, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2194 = TBUFFER_LOAD_FORMAT_XY_IDXEN
18257 { 2195, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2195 = TBUFFER_LOAD_FORMAT_XY_IDXEN_exact
18258 { 2196, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2196 = TBUFFER_LOAD_FORMAT_XY_OFFEN
18259 { 2197, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2197 = TBUFFER_LOAD_FORMAT_XY_OFFEN_exact
18260 { 2198, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2198 = TBUFFER_LOAD_FORMAT_XY_OFFSET
18261 { 2199, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2199 = TBUFFER_LOAD_FORMAT_XY_OFFSET_exact
18262 { 2200, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2200 = TBUFFER_LOAD_FORMAT_X_ADDR64
18263 { 2201, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2201 = TBUFFER_LOAD_FORMAT_X_BOTHEN
18264 { 2202, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2202 = TBUFFER_LOAD_FORMAT_X_BOTHEN_exact
18265 { 2203, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2203 = TBUFFER_LOAD_FORMAT_X_IDXEN
18266 { 2204, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2204 = TBUFFER_LOAD_FORMAT_X_IDXEN_exact
18267 { 2205, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2205 = TBUFFER_LOAD_FORMAT_X_OFFEN
18268 { 2206, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2206 = TBUFFER_LOAD_FORMAT_X_OFFEN_exact
18269 { 2207, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2207 = TBUFFER_LOAD_FORMAT_X_OFFSET
18270 { 2208, 10, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2208 = TBUFFER_LOAD_FORMAT_X_OFFSET_exact
18271 { 2209, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2209 = TBUFFER_STORE_FORMAT_D16_XYZW_ADDR64
18272 { 2210, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2210 = TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN
18273 { 2211, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2211 = TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact
18274 { 2212, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2212 = TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN
18275 { 2213, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2213 = TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact
18276 { 2214, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2214 = TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN
18277 { 2215, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2215 = TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact
18278 { 2216, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2216 = TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET
18279 { 2217, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2217 = TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact
18280 { 2218, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2218 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_ADDR64
18281 { 2219, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2219 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN
18282 { 2220, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2220 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact
18283 { 2221, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2221 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN
18284 { 2222, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2222 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact
18285 { 2223, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2223 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN
18286 { 2224, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2224 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact
18287 { 2225, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2225 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET
18288 { 2226, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2226 = TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact
18289 { 2227, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2227 = TBUFFER_STORE_FORMAT_D16_XYZ_ADDR64
18290 { 2228, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2228 = TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN
18291 { 2229, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2229 = TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact
18292 { 2230, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2230 = TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN
18293 { 2231, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2231 = TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_exact
18294 { 2232, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2232 = TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN
18295 { 2233, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2233 = TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact
18296 { 2234, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2234 = TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET
18297 { 2235, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2235 = TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_exact
18298 { 2236, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2236 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_ADDR64
18299 { 2237, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2237 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN
18300 { 2238, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2238 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact
18301 { 2239, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2239 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN
18302 { 2240, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2240 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact
18303 { 2241, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2241 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN
18304 { 2242, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2242 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact
18305 { 2243, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2243 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET
18306 { 2244, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2244 = TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact
18307 { 2245, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2245 = TBUFFER_STORE_FORMAT_D16_XY_ADDR64
18308 { 2246, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2246 = TBUFFER_STORE_FORMAT_D16_XY_BOTHEN
18309 { 2247, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2247 = TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact
18310 { 2248, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2248 = TBUFFER_STORE_FORMAT_D16_XY_IDXEN
18311 { 2249, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2249 = TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact
18312 { 2250, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2250 = TBUFFER_STORE_FORMAT_D16_XY_OFFEN
18313 { 2251, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2251 = TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact
18314 { 2252, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2252 = TBUFFER_STORE_FORMAT_D16_XY_OFFSET
18315 { 2253, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2253 = TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact
18316 { 2254, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2254 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_ADDR64
18317 { 2255, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2255 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN
18318 { 2256, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2256 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact
18319 { 2257, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2257 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN
18320 { 2258, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2258 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact
18321 { 2259, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2259 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN
18322 { 2260, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2260 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact
18323 { 2261, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2261 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET
18324 { 2262, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2262 = TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact
18325 { 2263, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2263 = TBUFFER_STORE_FORMAT_D16_X_ADDR64
18326 { 2264, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2264 = TBUFFER_STORE_FORMAT_D16_X_BOTHEN
18327 { 2265, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2265 = TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact
18328 { 2266, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2266 = TBUFFER_STORE_FORMAT_D16_X_IDXEN
18329 { 2267, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2267 = TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact
18330 { 2268, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2268 = TBUFFER_STORE_FORMAT_D16_X_OFFEN
18331 { 2269, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2269 = TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact
18332 { 2270, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2270 = TBUFFER_STORE_FORMAT_D16_X_OFFSET
18333 { 2271, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2271 = TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact
18334 { 2272, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2272 = TBUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64
18335 { 2273, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2273 = TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN
18336 { 2274, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2274 = TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact
18337 { 2275, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2275 = TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN
18338 { 2276, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2276 = TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact
18339 { 2277, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2277 = TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN
18340 { 2278, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2278 = TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact
18341 { 2279, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2279 = TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET
18342 { 2280, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4001300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2280 = TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact
18343 { 2281, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2281 = TBUFFER_STORE_FORMAT_XYZW_ADDR64
18344 { 2282, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2282 = TBUFFER_STORE_FORMAT_XYZW_BOTHEN
18345 { 2283, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2283 = TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact
18346 { 2284, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2284 = TBUFFER_STORE_FORMAT_XYZW_IDXEN
18347 { 2285, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2285 = TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact
18348 { 2286, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2286 = TBUFFER_STORE_FORMAT_XYZW_OFFEN
18349 { 2287, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2287 = TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact
18350 { 2288, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2288 = TBUFFER_STORE_FORMAT_XYZW_OFFSET
18351 { 2289, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2289 = TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact
18352 { 2290, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2290 = TBUFFER_STORE_FORMAT_XYZ_ADDR64
18353 { 2291, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2291 = TBUFFER_STORE_FORMAT_XYZ_BOTHEN
18354 { 2292, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2292 = TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact
18355 { 2293, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2293 = TBUFFER_STORE_FORMAT_XYZ_IDXEN
18356 { 2294, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2294 = TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact
18357 { 2295, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2295 = TBUFFER_STORE_FORMAT_XYZ_OFFEN
18358 { 2296, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2296 = TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact
18359 { 2297, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2297 = TBUFFER_STORE_FORMAT_XYZ_OFFSET
18360 { 2298, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2298 = TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact
18361 { 2299, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2299 = TBUFFER_STORE_FORMAT_XY_ADDR64
18362 { 2300, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2300 = TBUFFER_STORE_FORMAT_XY_BOTHEN
18363 { 2301, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2301 = TBUFFER_STORE_FORMAT_XY_BOTHEN_exact
18364 { 2302, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2302 = TBUFFER_STORE_FORMAT_XY_IDXEN
18365 { 2303, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2303 = TBUFFER_STORE_FORMAT_XY_IDXEN_exact
18366 { 2304, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2304 = TBUFFER_STORE_FORMAT_XY_OFFEN
18367 { 2305, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2305 = TBUFFER_STORE_FORMAT_XY_OFFEN_exact
18368 { 2306, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2306 = TBUFFER_STORE_FORMAT_XY_OFFSET
18369 { 2307, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2307 = TBUFFER_STORE_FORMAT_XY_OFFSET_exact
18370 { 2308, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2308 = TBUFFER_STORE_FORMAT_X_ADDR64
18371 { 2309, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2309 = TBUFFER_STORE_FORMAT_X_BOTHEN
18372 { 2310, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2310 = TBUFFER_STORE_FORMAT_X_BOTHEN_exact
18373 { 2311, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2311 = TBUFFER_STORE_FORMAT_X_IDXEN
18374 { 2312, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2312 = TBUFFER_STORE_FORMAT_X_IDXEN_exact
18375 { 2313, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2313 = TBUFFER_STORE_FORMAT_X_OFFEN
18376 { 2314, 11, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2314 = TBUFFER_STORE_FORMAT_X_OFFEN_exact
18377 { 2315, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2315 = TBUFFER_STORE_FORMAT_X_OFFSET
18378 { 2316, 10, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1300020000ULL, ImplicitList2, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2316 = TBUFFER_STORE_FORMAT_X_OFFSET_exact
18379 { 2317, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2317 = V_ACCVGPR_READ_B32
18380 { 2318, 2, 1, 8, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2318 = V_ACCVGPR_WRITE_B32
18381 { 2319, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2319 = V_ADD3_U32
18382 { 2320, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #2320 = V_ADDC_U32_dpp
18383 { 2321, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #2321 = V_ADDC_U32_e32
18384 { 2322, 6, 2, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2322 = V_ADDC_U32_e64
18385 { 2323, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #2323 = V_ADDC_U32_sdwa
18386 { 2324, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2324 = V_ADD_F16_dpp
18387 { 2325, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2325 = V_ADD_F16_e32
18388 { 2326, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2326 = V_ADD_F16_e64
18389 { 2327, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2327 = V_ADD_F16_sdwa
18390 { 2328, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2328 = V_ADD_F32_dpp
18391 { 2329, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2329 = V_ADD_F32_e32
18392 { 2330, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2330 = V_ADD_F32_e64
18393 { 2331, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2331 = V_ADD_F32_sdwa
18394 { 2332, 7, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2332 = V_ADD_F64
18395 { 2333, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2333 = V_ADD_I16
18396 { 2334, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #2334 = V_ADD_I32_dpp
18397 { 2335, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #2335 = V_ADD_I32_e32
18398 { 2336, 5, 2, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2336 = V_ADD_I32_e64
18399 { 2337, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2337 = V_ADD_I32_gfx9
18400 { 2338, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #2338 = V_ADD_I32_sdwa
18401 { 2339, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2339 = V_ADD_LSHL_U32
18402 { 2340, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2340 = V_ADD_U16_dpp
18403 { 2341, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2341 = V_ADD_U16_e32
18404 { 2342, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2342 = V_ADD_U16_e64
18405 { 2343, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2343 = V_ADD_U16_sdwa
18406 { 2344, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2344 = V_ADD_U32_dpp
18407 { 2345, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2345 = V_ADD_U32_e32
18408 { 2346, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2346 = V_ADD_U32_e64
18409 { 2347, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2347 = V_ADD_U32_sdwa
18410 { 2348, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2348 = V_ALIGNBIT_B32
18411 { 2349, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2349 = V_ALIGNBYTE_B32
18412 { 2350, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2350 = V_AND_B32_dpp
18413 { 2351, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2351 = V_AND_B32_e32
18414 { 2352, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2352 = V_AND_B32_e64
18415 { 2353, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2353 = V_AND_B32_sdwa
18416 { 2354, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2354 = V_AND_OR_B32
18417 { 2355, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2355 = V_ASHRREV_I16_dpp
18418 { 2356, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2356 = V_ASHRREV_I16_e32
18419 { 2357, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2357 = V_ASHRREV_I16_e64
18420 { 2358, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2358 = V_ASHRREV_I16_sdwa
18421 { 2359, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2359 = V_ASHRREV_I32_dpp
18422 { 2360, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2360 = V_ASHRREV_I32_e32
18423 { 2361, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2361 = V_ASHRREV_I32_e64
18424 { 2362, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2362 = V_ASHRREV_I32_sdwa
18425 { 2363, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2363 = V_ASHRREV_I64
18426 { 2364, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2364 = V_ASHR_I32_dpp
18427 { 2365, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2365 = V_ASHR_I32_e32
18428 { 2366, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2366 = V_ASHR_I32_e64
18429 { 2367, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2367 = V_ASHR_I32_sdwa
18430 { 2368, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2368 = V_ASHR_I64
18431 { 2369, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2369 = V_BCNT_U32_B32_e32
18432 { 2370, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2370 = V_BCNT_U32_B32_e64
18433 { 2371, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2371 = V_BFE_I32
18434 { 2372, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2372 = V_BFE_U32
18435 { 2373, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2373 = V_BFI_B32
18436 { 2374, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2374 = V_BFM_B32_e32
18437 { 2375, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2375 = V_BFM_B32_e64
18438 { 2376, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2376 = V_BFREV_B32_dpp
18439 { 2377, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2377 = V_BFREV_B32_e32
18440 { 2378, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2378 = V_BFREV_B32_e64
18441 { 2379, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2379 = V_BFREV_B32_sdwa
18442 { 2380, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2380 = V_CEIL_F16_dpp
18443 { 2381, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2381 = V_CEIL_F16_e32
18444 { 2382, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2382 = V_CEIL_F16_e64
18445 { 2383, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2383 = V_CEIL_F16_sdwa
18446 { 2384, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2384 = V_CEIL_F32_dpp
18447 { 2385, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2385 = V_CEIL_F32_e32
18448 { 2386, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2386 = V_CEIL_F32_e64
18449 { 2387, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2387 = V_CEIL_F32_sdwa
18450 { 2388, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2388 = V_CEIL_F64_e32
18451 { 2389, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2389 = V_CEIL_F64_e64
18452 { 2390, 0, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20000000082ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #2390 = V_CLREXCP_e32
18453 { 2391, 0, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20000000402ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #2391 = V_CLREXCP_e64
18454 { 2392, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2392 = V_CMPSX_EQ_F32_e32
18455 { 2393, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2393 = V_CMPSX_EQ_F32_e64
18456 { 2394, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2394 = V_CMPSX_EQ_F32_nosdst_e32
18457 { 2395, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2395 = V_CMPSX_EQ_F32_nosdst_e64
18458 { 2396, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2396 = V_CMPSX_EQ_F32_nosdst_sdwa
18459 { 2397, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2397 = V_CMPSX_EQ_F32_sdwa
18460 { 2398, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2398 = V_CMPSX_EQ_F64_e32
18461 { 2399, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2399 = V_CMPSX_EQ_F64_e64
18462 { 2400, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2400 = V_CMPSX_EQ_F64_nosdst_e32
18463 { 2401, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2401 = V_CMPSX_EQ_F64_nosdst_e64
18464 { 2402, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2402 = V_CMPSX_F_F32_e32
18465 { 2403, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2403 = V_CMPSX_F_F32_e64
18466 { 2404, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2404 = V_CMPSX_F_F32_nosdst_e32
18467 { 2405, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2405 = V_CMPSX_F_F32_nosdst_e64
18468 { 2406, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2406 = V_CMPSX_F_F32_nosdst_sdwa
18469 { 2407, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2407 = V_CMPSX_F_F32_sdwa
18470 { 2408, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2408 = V_CMPSX_F_F64_e32
18471 { 2409, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2409 = V_CMPSX_F_F64_e64
18472 { 2410, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2410 = V_CMPSX_F_F64_nosdst_e32
18473 { 2411, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2411 = V_CMPSX_F_F64_nosdst_e64
18474 { 2412, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2412 = V_CMPSX_GE_F32_e32
18475 { 2413, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2413 = V_CMPSX_GE_F32_e64
18476 { 2414, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2414 = V_CMPSX_GE_F32_nosdst_e32
18477 { 2415, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2415 = V_CMPSX_GE_F32_nosdst_e64
18478 { 2416, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2416 = V_CMPSX_GE_F32_nosdst_sdwa
18479 { 2417, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2417 = V_CMPSX_GE_F32_sdwa
18480 { 2418, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2418 = V_CMPSX_GE_F64_e32
18481 { 2419, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2419 = V_CMPSX_GE_F64_e64
18482 { 2420, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2420 = V_CMPSX_GE_F64_nosdst_e32
18483 { 2421, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2421 = V_CMPSX_GE_F64_nosdst_e64
18484 { 2422, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2422 = V_CMPSX_GT_F32_e32
18485 { 2423, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2423 = V_CMPSX_GT_F32_e64
18486 { 2424, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2424 = V_CMPSX_GT_F32_nosdst_e32
18487 { 2425, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2425 = V_CMPSX_GT_F32_nosdst_e64
18488 { 2426, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2426 = V_CMPSX_GT_F32_nosdst_sdwa
18489 { 2427, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2427 = V_CMPSX_GT_F32_sdwa
18490 { 2428, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2428 = V_CMPSX_GT_F64_e32
18491 { 2429, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2429 = V_CMPSX_GT_F64_e64
18492 { 2430, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2430 = V_CMPSX_GT_F64_nosdst_e32
18493 { 2431, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2431 = V_CMPSX_GT_F64_nosdst_e64
18494 { 2432, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2432 = V_CMPSX_LE_F32_e32
18495 { 2433, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2433 = V_CMPSX_LE_F32_e64
18496 { 2434, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2434 = V_CMPSX_LE_F32_nosdst_e32
18497 { 2435, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2435 = V_CMPSX_LE_F32_nosdst_e64
18498 { 2436, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2436 = V_CMPSX_LE_F32_nosdst_sdwa
18499 { 2437, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2437 = V_CMPSX_LE_F32_sdwa
18500 { 2438, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2438 = V_CMPSX_LE_F64_e32
18501 { 2439, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2439 = V_CMPSX_LE_F64_e64
18502 { 2440, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2440 = V_CMPSX_LE_F64_nosdst_e32
18503 { 2441, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2441 = V_CMPSX_LE_F64_nosdst_e64
18504 { 2442, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2442 = V_CMPSX_LG_F32_e32
18505 { 2443, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2443 = V_CMPSX_LG_F32_e64
18506 { 2444, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2444 = V_CMPSX_LG_F32_nosdst_e32
18507 { 2445, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2445 = V_CMPSX_LG_F32_nosdst_e64
18508 { 2446, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2446 = V_CMPSX_LG_F32_nosdst_sdwa
18509 { 2447, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2447 = V_CMPSX_LG_F32_sdwa
18510 { 2448, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2448 = V_CMPSX_LG_F64_e32
18511 { 2449, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2449 = V_CMPSX_LG_F64_e64
18512 { 2450, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2450 = V_CMPSX_LG_F64_nosdst_e32
18513 { 2451, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2451 = V_CMPSX_LG_F64_nosdst_e64
18514 { 2452, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2452 = V_CMPSX_LT_F32_e32
18515 { 2453, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2453 = V_CMPSX_LT_F32_e64
18516 { 2454, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2454 = V_CMPSX_LT_F32_nosdst_e32
18517 { 2455, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2455 = V_CMPSX_LT_F32_nosdst_e64
18518 { 2456, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2456 = V_CMPSX_LT_F32_nosdst_sdwa
18519 { 2457, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2457 = V_CMPSX_LT_F32_sdwa
18520 { 2458, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2458 = V_CMPSX_LT_F64_e32
18521 { 2459, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2459 = V_CMPSX_LT_F64_e64
18522 { 2460, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2460 = V_CMPSX_LT_F64_nosdst_e32
18523 { 2461, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2461 = V_CMPSX_LT_F64_nosdst_e64
18524 { 2462, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2462 = V_CMPSX_NEQ_F32_e32
18525 { 2463, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2463 = V_CMPSX_NEQ_F32_e64
18526 { 2464, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2464 = V_CMPSX_NEQ_F32_nosdst_e32
18527 { 2465, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2465 = V_CMPSX_NEQ_F32_nosdst_e64
18528 { 2466, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2466 = V_CMPSX_NEQ_F32_nosdst_sdwa
18529 { 2467, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2467 = V_CMPSX_NEQ_F32_sdwa
18530 { 2468, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2468 = V_CMPSX_NEQ_F64_e32
18531 { 2469, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2469 = V_CMPSX_NEQ_F64_e64
18532 { 2470, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2470 = V_CMPSX_NEQ_F64_nosdst_e32
18533 { 2471, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2471 = V_CMPSX_NEQ_F64_nosdst_e64
18534 { 2472, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2472 = V_CMPSX_NGE_F32_e32
18535 { 2473, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2473 = V_CMPSX_NGE_F32_e64
18536 { 2474, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2474 = V_CMPSX_NGE_F32_nosdst_e32
18537 { 2475, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2475 = V_CMPSX_NGE_F32_nosdst_e64
18538 { 2476, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2476 = V_CMPSX_NGE_F32_nosdst_sdwa
18539 { 2477, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2477 = V_CMPSX_NGE_F32_sdwa
18540 { 2478, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2478 = V_CMPSX_NGE_F64_e32
18541 { 2479, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2479 = V_CMPSX_NGE_F64_e64
18542 { 2480, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2480 = V_CMPSX_NGE_F64_nosdst_e32
18543 { 2481, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2481 = V_CMPSX_NGE_F64_nosdst_e64
18544 { 2482, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2482 = V_CMPSX_NGT_F32_e32
18545 { 2483, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2483 = V_CMPSX_NGT_F32_e64
18546 { 2484, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2484 = V_CMPSX_NGT_F32_nosdst_e32
18547 { 2485, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2485 = V_CMPSX_NGT_F32_nosdst_e64
18548 { 2486, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2486 = V_CMPSX_NGT_F32_nosdst_sdwa
18549 { 2487, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2487 = V_CMPSX_NGT_F32_sdwa
18550 { 2488, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2488 = V_CMPSX_NGT_F64_e32
18551 { 2489, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2489 = V_CMPSX_NGT_F64_e64
18552 { 2490, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2490 = V_CMPSX_NGT_F64_nosdst_e32
18553 { 2491, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2491 = V_CMPSX_NGT_F64_nosdst_e64
18554 { 2492, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2492 = V_CMPSX_NLE_F32_e32
18555 { 2493, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2493 = V_CMPSX_NLE_F32_e64
18556 { 2494, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2494 = V_CMPSX_NLE_F32_nosdst_e32
18557 { 2495, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2495 = V_CMPSX_NLE_F32_nosdst_e64
18558 { 2496, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2496 = V_CMPSX_NLE_F32_nosdst_sdwa
18559 { 2497, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2497 = V_CMPSX_NLE_F32_sdwa
18560 { 2498, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2498 = V_CMPSX_NLE_F64_e32
18561 { 2499, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2499 = V_CMPSX_NLE_F64_e64
18562 { 2500, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2500 = V_CMPSX_NLE_F64_nosdst_e32
18563 { 2501, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2501 = V_CMPSX_NLE_F64_nosdst_e64
18564 { 2502, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2502 = V_CMPSX_NLG_F32_e32
18565 { 2503, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2503 = V_CMPSX_NLG_F32_e64
18566 { 2504, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2504 = V_CMPSX_NLG_F32_nosdst_e32
18567 { 2505, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2505 = V_CMPSX_NLG_F32_nosdst_e64
18568 { 2506, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2506 = V_CMPSX_NLG_F32_nosdst_sdwa
18569 { 2507, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2507 = V_CMPSX_NLG_F32_sdwa
18570 { 2508, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2508 = V_CMPSX_NLG_F64_e32
18571 { 2509, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2509 = V_CMPSX_NLG_F64_e64
18572 { 2510, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2510 = V_CMPSX_NLG_F64_nosdst_e32
18573 { 2511, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2511 = V_CMPSX_NLG_F64_nosdst_e64
18574 { 2512, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2512 = V_CMPSX_NLT_F32_e32
18575 { 2513, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2513 = V_CMPSX_NLT_F32_e64
18576 { 2514, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2514 = V_CMPSX_NLT_F32_nosdst_e32
18577 { 2515, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2515 = V_CMPSX_NLT_F32_nosdst_e64
18578 { 2516, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2516 = V_CMPSX_NLT_F32_nosdst_sdwa
18579 { 2517, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2517 = V_CMPSX_NLT_F32_sdwa
18580 { 2518, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2518 = V_CMPSX_NLT_F64_e32
18581 { 2519, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2519 = V_CMPSX_NLT_F64_e64
18582 { 2520, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2520 = V_CMPSX_NLT_F64_nosdst_e32
18583 { 2521, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2521 = V_CMPSX_NLT_F64_nosdst_e64
18584 { 2522, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2522 = V_CMPSX_O_F32_e32
18585 { 2523, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2523 = V_CMPSX_O_F32_e64
18586 { 2524, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2524 = V_CMPSX_O_F32_nosdst_e32
18587 { 2525, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2525 = V_CMPSX_O_F32_nosdst_e64
18588 { 2526, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2526 = V_CMPSX_O_F32_nosdst_sdwa
18589 { 2527, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2527 = V_CMPSX_O_F32_sdwa
18590 { 2528, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2528 = V_CMPSX_O_F64_e32
18591 { 2529, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2529 = V_CMPSX_O_F64_e64
18592 { 2530, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2530 = V_CMPSX_O_F64_nosdst_e32
18593 { 2531, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2531 = V_CMPSX_O_F64_nosdst_e64
18594 { 2532, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2532 = V_CMPSX_TRU_F32_e32
18595 { 2533, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2533 = V_CMPSX_TRU_F32_e64
18596 { 2534, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2534 = V_CMPSX_TRU_F32_nosdst_e32
18597 { 2535, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2535 = V_CMPSX_TRU_F32_nosdst_e64
18598 { 2536, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2536 = V_CMPSX_TRU_F32_nosdst_sdwa
18599 { 2537, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2537 = V_CMPSX_TRU_F32_sdwa
18600 { 2538, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2538 = V_CMPSX_TRU_F64_e32
18601 { 2539, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2539 = V_CMPSX_TRU_F64_e64
18602 { 2540, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2540 = V_CMPSX_TRU_F64_nosdst_e32
18603 { 2541, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2541 = V_CMPSX_TRU_F64_nosdst_e64
18604 { 2542, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2542 = V_CMPSX_U_F32_e32
18605 { 2543, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2543 = V_CMPSX_U_F32_e64
18606 { 2544, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2544 = V_CMPSX_U_F32_nosdst_e32
18607 { 2545, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2545 = V_CMPSX_U_F32_nosdst_e64
18608 { 2546, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2546 = V_CMPSX_U_F32_nosdst_sdwa
18609 { 2547, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2547 = V_CMPSX_U_F32_sdwa
18610 { 2548, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2548 = V_CMPSX_U_F64_e32
18611 { 2549, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2549 = V_CMPSX_U_F64_e64
18612 { 2550, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2550 = V_CMPSX_U_F64_nosdst_e32
18613 { 2551, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2551 = V_CMPSX_U_F64_nosdst_e64
18614 { 2552, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2552 = V_CMPS_EQ_F32_e32
18615 { 2553, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2553 = V_CMPS_EQ_F32_e64
18616 { 2554, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2554 = V_CMPS_EQ_F32_sdwa
18617 { 2555, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2555 = V_CMPS_EQ_F64_e32
18618 { 2556, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2556 = V_CMPS_EQ_F64_e64
18619 { 2557, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2557 = V_CMPS_F_F32_e32
18620 { 2558, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2558 = V_CMPS_F_F32_e64
18621 { 2559, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2559 = V_CMPS_F_F32_sdwa
18622 { 2560, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2560 = V_CMPS_F_F64_e32
18623 { 2561, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2561 = V_CMPS_F_F64_e64
18624 { 2562, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2562 = V_CMPS_GE_F32_e32
18625 { 2563, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2563 = V_CMPS_GE_F32_e64
18626 { 2564, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2564 = V_CMPS_GE_F32_sdwa
18627 { 2565, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2565 = V_CMPS_GE_F64_e32
18628 { 2566, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2566 = V_CMPS_GE_F64_e64
18629 { 2567, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2567 = V_CMPS_GT_F32_e32
18630 { 2568, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2568 = V_CMPS_GT_F32_e64
18631 { 2569, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2569 = V_CMPS_GT_F32_sdwa
18632 { 2570, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2570 = V_CMPS_GT_F64_e32
18633 { 2571, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2571 = V_CMPS_GT_F64_e64
18634 { 2572, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2572 = V_CMPS_LE_F32_e32
18635 { 2573, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2573 = V_CMPS_LE_F32_e64
18636 { 2574, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2574 = V_CMPS_LE_F32_sdwa
18637 { 2575, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2575 = V_CMPS_LE_F64_e32
18638 { 2576, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2576 = V_CMPS_LE_F64_e64
18639 { 2577, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2577 = V_CMPS_LG_F32_e32
18640 { 2578, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2578 = V_CMPS_LG_F32_e64
18641 { 2579, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2579 = V_CMPS_LG_F32_sdwa
18642 { 2580, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2580 = V_CMPS_LG_F64_e32
18643 { 2581, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2581 = V_CMPS_LG_F64_e64
18644 { 2582, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2582 = V_CMPS_LT_F32_e32
18645 { 2583, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2583 = V_CMPS_LT_F32_e64
18646 { 2584, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2584 = V_CMPS_LT_F32_sdwa
18647 { 2585, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2585 = V_CMPS_LT_F64_e32
18648 { 2586, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2586 = V_CMPS_LT_F64_e64
18649 { 2587, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2587 = V_CMPS_NEQ_F32_e32
18650 { 2588, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2588 = V_CMPS_NEQ_F32_e64
18651 { 2589, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2589 = V_CMPS_NEQ_F32_sdwa
18652 { 2590, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2590 = V_CMPS_NEQ_F64_e32
18653 { 2591, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2591 = V_CMPS_NEQ_F64_e64
18654 { 2592, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2592 = V_CMPS_NGE_F32_e32
18655 { 2593, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2593 = V_CMPS_NGE_F32_e64
18656 { 2594, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2594 = V_CMPS_NGE_F32_sdwa
18657 { 2595, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2595 = V_CMPS_NGE_F64_e32
18658 { 2596, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2596 = V_CMPS_NGE_F64_e64
18659 { 2597, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2597 = V_CMPS_NGT_F32_e32
18660 { 2598, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2598 = V_CMPS_NGT_F32_e64
18661 { 2599, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2599 = V_CMPS_NGT_F32_sdwa
18662 { 2600, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2600 = V_CMPS_NGT_F64_e32
18663 { 2601, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2601 = V_CMPS_NGT_F64_e64
18664 { 2602, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2602 = V_CMPS_NLE_F32_e32
18665 { 2603, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2603 = V_CMPS_NLE_F32_e64
18666 { 2604, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2604 = V_CMPS_NLE_F32_sdwa
18667 { 2605, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2605 = V_CMPS_NLE_F64_e32
18668 { 2606, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2606 = V_CMPS_NLE_F64_e64
18669 { 2607, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2607 = V_CMPS_NLG_F32_e32
18670 { 2608, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2608 = V_CMPS_NLG_F32_e64
18671 { 2609, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2609 = V_CMPS_NLG_F32_sdwa
18672 { 2610, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2610 = V_CMPS_NLG_F64_e32
18673 { 2611, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2611 = V_CMPS_NLG_F64_e64
18674 { 2612, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2612 = V_CMPS_NLT_F32_e32
18675 { 2613, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2613 = V_CMPS_NLT_F32_e64
18676 { 2614, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2614 = V_CMPS_NLT_F32_sdwa
18677 { 2615, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2615 = V_CMPS_NLT_F64_e32
18678 { 2616, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2616 = V_CMPS_NLT_F64_e64
18679 { 2617, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2617 = V_CMPS_O_F32_e32
18680 { 2618, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2618 = V_CMPS_O_F32_e64
18681 { 2619, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2619 = V_CMPS_O_F32_sdwa
18682 { 2620, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2620 = V_CMPS_O_F64_e32
18683 { 2621, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2621 = V_CMPS_O_F64_e64
18684 { 2622, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2622 = V_CMPS_TRU_F32_e32
18685 { 2623, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2623 = V_CMPS_TRU_F32_e64
18686 { 2624, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2624 = V_CMPS_TRU_F32_sdwa
18687 { 2625, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2625 = V_CMPS_TRU_F64_e32
18688 { 2626, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2626 = V_CMPS_TRU_F64_e64
18689 { 2627, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #2627 = V_CMPS_U_F32_e32
18690 { 2628, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2628 = V_CMPS_U_F32_e64
18691 { 2629, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #2629 = V_CMPS_U_F32_sdwa
18692 { 2630, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #2630 = V_CMPS_U_F64_e32
18693 { 2631, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2631 = V_CMPS_U_F64_e64
18694 { 2632, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2632 = V_CMPX_CLASS_F16_e32
18695 { 2633, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo319, -1 ,nullptr }, // Inst #2633 = V_CMPX_CLASS_F16_e64
18696 { 2634, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2634 = V_CMPX_CLASS_F16_nosdst_e32
18697 { 2635, 3, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo320, -1 ,nullptr }, // Inst #2635 = V_CMPX_CLASS_F16_nosdst_e64
18698 { 2636, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2636 = V_CMPX_CLASS_F16_nosdst_sdwa
18699 { 2637, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2637 = V_CMPX_CLASS_F16_sdwa
18700 { 2638, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2638 = V_CMPX_CLASS_F32_e32
18701 { 2639, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo323, -1 ,nullptr }, // Inst #2639 = V_CMPX_CLASS_F32_e64
18702 { 2640, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2640 = V_CMPX_CLASS_F32_nosdst_e32
18703 { 2641, 3, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo324, -1 ,nullptr }, // Inst #2641 = V_CMPX_CLASS_F32_nosdst_e64
18704 { 2642, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2642 = V_CMPX_CLASS_F32_nosdst_sdwa
18705 { 2643, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2643 = V_CMPX_CLASS_F32_sdwa
18706 { 2644, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo325, -1 ,nullptr }, // Inst #2644 = V_CMPX_CLASS_F64_e32
18707 { 2645, 4, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo326, -1 ,nullptr }, // Inst #2645 = V_CMPX_CLASS_F64_e64
18708 { 2646, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo325, -1 ,nullptr }, // Inst #2646 = V_CMPX_CLASS_F64_nosdst_e32
18709 { 2647, 3, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo327, -1 ,nullptr }, // Inst #2647 = V_CMPX_CLASS_F64_nosdst_e64
18710 { 2648, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2648 = V_CMPX_EQ_F16_e32
18711 { 2649, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2649 = V_CMPX_EQ_F16_e64
18712 { 2650, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2650 = V_CMPX_EQ_F16_nosdst_e32
18713 { 2651, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2651 = V_CMPX_EQ_F16_nosdst_e64
18714 { 2652, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2652 = V_CMPX_EQ_F16_nosdst_sdwa
18715 { 2653, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2653 = V_CMPX_EQ_F16_sdwa
18716 { 2654, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2654 = V_CMPX_EQ_F32_e32
18717 { 2655, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2655 = V_CMPX_EQ_F32_e64
18718 { 2656, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2656 = V_CMPX_EQ_F32_nosdst_e32
18719 { 2657, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2657 = V_CMPX_EQ_F32_nosdst_e64
18720 { 2658, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2658 = V_CMPX_EQ_F32_nosdst_sdwa
18721 { 2659, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2659 = V_CMPX_EQ_F32_sdwa
18722 { 2660, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2660 = V_CMPX_EQ_F64_e32
18723 { 2661, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2661 = V_CMPX_EQ_F64_e64
18724 { 2662, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2662 = V_CMPX_EQ_F64_nosdst_e32
18725 { 2663, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2663 = V_CMPX_EQ_F64_nosdst_e64
18726 { 2664, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2664 = V_CMPX_EQ_I16_e32
18727 { 2665, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2665 = V_CMPX_EQ_I16_e64
18728 { 2666, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2666 = V_CMPX_EQ_I16_nosdst_e32
18729 { 2667, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2667 = V_CMPX_EQ_I16_nosdst_e64
18730 { 2668, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2668 = V_CMPX_EQ_I16_nosdst_sdwa
18731 { 2669, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2669 = V_CMPX_EQ_I16_sdwa
18732 { 2670, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2670 = V_CMPX_EQ_I32_e32
18733 { 2671, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2671 = V_CMPX_EQ_I32_e64
18734 { 2672, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2672 = V_CMPX_EQ_I32_nosdst_e32
18735 { 2673, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2673 = V_CMPX_EQ_I32_nosdst_e64
18736 { 2674, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2674 = V_CMPX_EQ_I32_nosdst_sdwa
18737 { 2675, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2675 = V_CMPX_EQ_I32_sdwa
18738 { 2676, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2676 = V_CMPX_EQ_I64_e32
18739 { 2677, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2677 = V_CMPX_EQ_I64_e64
18740 { 2678, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2678 = V_CMPX_EQ_I64_nosdst_e32
18741 { 2679, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2679 = V_CMPX_EQ_I64_nosdst_e64
18742 { 2680, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2680 = V_CMPX_EQ_U16_e32
18743 { 2681, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2681 = V_CMPX_EQ_U16_e64
18744 { 2682, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2682 = V_CMPX_EQ_U16_nosdst_e32
18745 { 2683, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2683 = V_CMPX_EQ_U16_nosdst_e64
18746 { 2684, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2684 = V_CMPX_EQ_U16_nosdst_sdwa
18747 { 2685, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2685 = V_CMPX_EQ_U16_sdwa
18748 { 2686, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2686 = V_CMPX_EQ_U32_e32
18749 { 2687, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2687 = V_CMPX_EQ_U32_e64
18750 { 2688, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2688 = V_CMPX_EQ_U32_nosdst_e32
18751 { 2689, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2689 = V_CMPX_EQ_U32_nosdst_e64
18752 { 2690, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2690 = V_CMPX_EQ_U32_nosdst_sdwa
18753 { 2691, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2691 = V_CMPX_EQ_U32_sdwa
18754 { 2692, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2692 = V_CMPX_EQ_U64_e32
18755 { 2693, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2693 = V_CMPX_EQ_U64_e64
18756 { 2694, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2694 = V_CMPX_EQ_U64_nosdst_e32
18757 { 2695, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2695 = V_CMPX_EQ_U64_nosdst_e64
18758 { 2696, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2696 = V_CMPX_F_F16_e32
18759 { 2697, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2697 = V_CMPX_F_F16_e64
18760 { 2698, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2698 = V_CMPX_F_F16_nosdst_e32
18761 { 2699, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2699 = V_CMPX_F_F16_nosdst_e64
18762 { 2700, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2700 = V_CMPX_F_F16_nosdst_sdwa
18763 { 2701, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2701 = V_CMPX_F_F16_sdwa
18764 { 2702, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2702 = V_CMPX_F_F32_e32
18765 { 2703, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2703 = V_CMPX_F_F32_e64
18766 { 2704, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2704 = V_CMPX_F_F32_nosdst_e32
18767 { 2705, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2705 = V_CMPX_F_F32_nosdst_e64
18768 { 2706, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2706 = V_CMPX_F_F32_nosdst_sdwa
18769 { 2707, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2707 = V_CMPX_F_F32_sdwa
18770 { 2708, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2708 = V_CMPX_F_F64_e32
18771 { 2709, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2709 = V_CMPX_F_F64_e64
18772 { 2710, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2710 = V_CMPX_F_F64_nosdst_e32
18773 { 2711, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2711 = V_CMPX_F_F64_nosdst_e64
18774 { 2712, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2712 = V_CMPX_F_I16_e32
18775 { 2713, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2713 = V_CMPX_F_I16_e64
18776 { 2714, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2714 = V_CMPX_F_I16_nosdst_e32
18777 { 2715, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2715 = V_CMPX_F_I16_nosdst_e64
18778 { 2716, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2716 = V_CMPX_F_I16_nosdst_sdwa
18779 { 2717, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2717 = V_CMPX_F_I16_sdwa
18780 { 2718, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2718 = V_CMPX_F_I32_e32
18781 { 2719, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2719 = V_CMPX_F_I32_e64
18782 { 2720, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2720 = V_CMPX_F_I32_nosdst_e32
18783 { 2721, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2721 = V_CMPX_F_I32_nosdst_e64
18784 { 2722, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2722 = V_CMPX_F_I32_nosdst_sdwa
18785 { 2723, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2723 = V_CMPX_F_I32_sdwa
18786 { 2724, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2724 = V_CMPX_F_I64_e32
18787 { 2725, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2725 = V_CMPX_F_I64_e64
18788 { 2726, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2726 = V_CMPX_F_I64_nosdst_e32
18789 { 2727, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2727 = V_CMPX_F_I64_nosdst_e64
18790 { 2728, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2728 = V_CMPX_F_U16_e32
18791 { 2729, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2729 = V_CMPX_F_U16_e64
18792 { 2730, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2730 = V_CMPX_F_U16_nosdst_e32
18793 { 2731, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2731 = V_CMPX_F_U16_nosdst_e64
18794 { 2732, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2732 = V_CMPX_F_U16_nosdst_sdwa
18795 { 2733, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2733 = V_CMPX_F_U16_sdwa
18796 { 2734, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2734 = V_CMPX_F_U32_e32
18797 { 2735, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2735 = V_CMPX_F_U32_e64
18798 { 2736, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2736 = V_CMPX_F_U32_nosdst_e32
18799 { 2737, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2737 = V_CMPX_F_U32_nosdst_e64
18800 { 2738, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2738 = V_CMPX_F_U32_nosdst_sdwa
18801 { 2739, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2739 = V_CMPX_F_U32_sdwa
18802 { 2740, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2740 = V_CMPX_F_U64_e32
18803 { 2741, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2741 = V_CMPX_F_U64_e64
18804 { 2742, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2742 = V_CMPX_F_U64_nosdst_e32
18805 { 2743, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2743 = V_CMPX_F_U64_nosdst_e64
18806 { 2744, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2744 = V_CMPX_GE_F16_e32
18807 { 2745, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2745 = V_CMPX_GE_F16_e64
18808 { 2746, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2746 = V_CMPX_GE_F16_nosdst_e32
18809 { 2747, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2747 = V_CMPX_GE_F16_nosdst_e64
18810 { 2748, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2748 = V_CMPX_GE_F16_nosdst_sdwa
18811 { 2749, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2749 = V_CMPX_GE_F16_sdwa
18812 { 2750, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2750 = V_CMPX_GE_F32_e32
18813 { 2751, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2751 = V_CMPX_GE_F32_e64
18814 { 2752, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2752 = V_CMPX_GE_F32_nosdst_e32
18815 { 2753, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2753 = V_CMPX_GE_F32_nosdst_e64
18816 { 2754, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2754 = V_CMPX_GE_F32_nosdst_sdwa
18817 { 2755, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2755 = V_CMPX_GE_F32_sdwa
18818 { 2756, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2756 = V_CMPX_GE_F64_e32
18819 { 2757, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2757 = V_CMPX_GE_F64_e64
18820 { 2758, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2758 = V_CMPX_GE_F64_nosdst_e32
18821 { 2759, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2759 = V_CMPX_GE_F64_nosdst_e64
18822 { 2760, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2760 = V_CMPX_GE_I16_e32
18823 { 2761, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2761 = V_CMPX_GE_I16_e64
18824 { 2762, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2762 = V_CMPX_GE_I16_nosdst_e32
18825 { 2763, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2763 = V_CMPX_GE_I16_nosdst_e64
18826 { 2764, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2764 = V_CMPX_GE_I16_nosdst_sdwa
18827 { 2765, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2765 = V_CMPX_GE_I16_sdwa
18828 { 2766, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2766 = V_CMPX_GE_I32_e32
18829 { 2767, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2767 = V_CMPX_GE_I32_e64
18830 { 2768, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2768 = V_CMPX_GE_I32_nosdst_e32
18831 { 2769, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2769 = V_CMPX_GE_I32_nosdst_e64
18832 { 2770, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2770 = V_CMPX_GE_I32_nosdst_sdwa
18833 { 2771, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2771 = V_CMPX_GE_I32_sdwa
18834 { 2772, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2772 = V_CMPX_GE_I64_e32
18835 { 2773, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2773 = V_CMPX_GE_I64_e64
18836 { 2774, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2774 = V_CMPX_GE_I64_nosdst_e32
18837 { 2775, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2775 = V_CMPX_GE_I64_nosdst_e64
18838 { 2776, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2776 = V_CMPX_GE_U16_e32
18839 { 2777, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2777 = V_CMPX_GE_U16_e64
18840 { 2778, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2778 = V_CMPX_GE_U16_nosdst_e32
18841 { 2779, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2779 = V_CMPX_GE_U16_nosdst_e64
18842 { 2780, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2780 = V_CMPX_GE_U16_nosdst_sdwa
18843 { 2781, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2781 = V_CMPX_GE_U16_sdwa
18844 { 2782, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2782 = V_CMPX_GE_U32_e32
18845 { 2783, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2783 = V_CMPX_GE_U32_e64
18846 { 2784, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2784 = V_CMPX_GE_U32_nosdst_e32
18847 { 2785, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2785 = V_CMPX_GE_U32_nosdst_e64
18848 { 2786, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2786 = V_CMPX_GE_U32_nosdst_sdwa
18849 { 2787, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2787 = V_CMPX_GE_U32_sdwa
18850 { 2788, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2788 = V_CMPX_GE_U64_e32
18851 { 2789, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2789 = V_CMPX_GE_U64_e64
18852 { 2790, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2790 = V_CMPX_GE_U64_nosdst_e32
18853 { 2791, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2791 = V_CMPX_GE_U64_nosdst_e64
18854 { 2792, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2792 = V_CMPX_GT_F16_e32
18855 { 2793, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2793 = V_CMPX_GT_F16_e64
18856 { 2794, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2794 = V_CMPX_GT_F16_nosdst_e32
18857 { 2795, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2795 = V_CMPX_GT_F16_nosdst_e64
18858 { 2796, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2796 = V_CMPX_GT_F16_nosdst_sdwa
18859 { 2797, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2797 = V_CMPX_GT_F16_sdwa
18860 { 2798, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2798 = V_CMPX_GT_F32_e32
18861 { 2799, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2799 = V_CMPX_GT_F32_e64
18862 { 2800, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2800 = V_CMPX_GT_F32_nosdst_e32
18863 { 2801, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2801 = V_CMPX_GT_F32_nosdst_e64
18864 { 2802, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2802 = V_CMPX_GT_F32_nosdst_sdwa
18865 { 2803, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2803 = V_CMPX_GT_F32_sdwa
18866 { 2804, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2804 = V_CMPX_GT_F64_e32
18867 { 2805, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2805 = V_CMPX_GT_F64_e64
18868 { 2806, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2806 = V_CMPX_GT_F64_nosdst_e32
18869 { 2807, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2807 = V_CMPX_GT_F64_nosdst_e64
18870 { 2808, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2808 = V_CMPX_GT_I16_e32
18871 { 2809, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2809 = V_CMPX_GT_I16_e64
18872 { 2810, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2810 = V_CMPX_GT_I16_nosdst_e32
18873 { 2811, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2811 = V_CMPX_GT_I16_nosdst_e64
18874 { 2812, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2812 = V_CMPX_GT_I16_nosdst_sdwa
18875 { 2813, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2813 = V_CMPX_GT_I16_sdwa
18876 { 2814, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2814 = V_CMPX_GT_I32_e32
18877 { 2815, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2815 = V_CMPX_GT_I32_e64
18878 { 2816, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2816 = V_CMPX_GT_I32_nosdst_e32
18879 { 2817, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2817 = V_CMPX_GT_I32_nosdst_e64
18880 { 2818, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2818 = V_CMPX_GT_I32_nosdst_sdwa
18881 { 2819, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2819 = V_CMPX_GT_I32_sdwa
18882 { 2820, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2820 = V_CMPX_GT_I64_e32
18883 { 2821, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2821 = V_CMPX_GT_I64_e64
18884 { 2822, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2822 = V_CMPX_GT_I64_nosdst_e32
18885 { 2823, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2823 = V_CMPX_GT_I64_nosdst_e64
18886 { 2824, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2824 = V_CMPX_GT_U16_e32
18887 { 2825, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2825 = V_CMPX_GT_U16_e64
18888 { 2826, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2826 = V_CMPX_GT_U16_nosdst_e32
18889 { 2827, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2827 = V_CMPX_GT_U16_nosdst_e64
18890 { 2828, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2828 = V_CMPX_GT_U16_nosdst_sdwa
18891 { 2829, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2829 = V_CMPX_GT_U16_sdwa
18892 { 2830, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2830 = V_CMPX_GT_U32_e32
18893 { 2831, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2831 = V_CMPX_GT_U32_e64
18894 { 2832, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2832 = V_CMPX_GT_U32_nosdst_e32
18895 { 2833, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2833 = V_CMPX_GT_U32_nosdst_e64
18896 { 2834, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2834 = V_CMPX_GT_U32_nosdst_sdwa
18897 { 2835, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2835 = V_CMPX_GT_U32_sdwa
18898 { 2836, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2836 = V_CMPX_GT_U64_e32
18899 { 2837, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2837 = V_CMPX_GT_U64_e64
18900 { 2838, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2838 = V_CMPX_GT_U64_nosdst_e32
18901 { 2839, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2839 = V_CMPX_GT_U64_nosdst_e64
18902 { 2840, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2840 = V_CMPX_LE_F16_e32
18903 { 2841, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2841 = V_CMPX_LE_F16_e64
18904 { 2842, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2842 = V_CMPX_LE_F16_nosdst_e32
18905 { 2843, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2843 = V_CMPX_LE_F16_nosdst_e64
18906 { 2844, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2844 = V_CMPX_LE_F16_nosdst_sdwa
18907 { 2845, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2845 = V_CMPX_LE_F16_sdwa
18908 { 2846, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2846 = V_CMPX_LE_F32_e32
18909 { 2847, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2847 = V_CMPX_LE_F32_e64
18910 { 2848, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2848 = V_CMPX_LE_F32_nosdst_e32
18911 { 2849, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2849 = V_CMPX_LE_F32_nosdst_e64
18912 { 2850, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2850 = V_CMPX_LE_F32_nosdst_sdwa
18913 { 2851, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2851 = V_CMPX_LE_F32_sdwa
18914 { 2852, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2852 = V_CMPX_LE_F64_e32
18915 { 2853, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2853 = V_CMPX_LE_F64_e64
18916 { 2854, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2854 = V_CMPX_LE_F64_nosdst_e32
18917 { 2855, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2855 = V_CMPX_LE_F64_nosdst_e64
18918 { 2856, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2856 = V_CMPX_LE_I16_e32
18919 { 2857, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2857 = V_CMPX_LE_I16_e64
18920 { 2858, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2858 = V_CMPX_LE_I16_nosdst_e32
18921 { 2859, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2859 = V_CMPX_LE_I16_nosdst_e64
18922 { 2860, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2860 = V_CMPX_LE_I16_nosdst_sdwa
18923 { 2861, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2861 = V_CMPX_LE_I16_sdwa
18924 { 2862, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2862 = V_CMPX_LE_I32_e32
18925 { 2863, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2863 = V_CMPX_LE_I32_e64
18926 { 2864, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2864 = V_CMPX_LE_I32_nosdst_e32
18927 { 2865, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2865 = V_CMPX_LE_I32_nosdst_e64
18928 { 2866, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2866 = V_CMPX_LE_I32_nosdst_sdwa
18929 { 2867, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2867 = V_CMPX_LE_I32_sdwa
18930 { 2868, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2868 = V_CMPX_LE_I64_e32
18931 { 2869, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2869 = V_CMPX_LE_I64_e64
18932 { 2870, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2870 = V_CMPX_LE_I64_nosdst_e32
18933 { 2871, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2871 = V_CMPX_LE_I64_nosdst_e64
18934 { 2872, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2872 = V_CMPX_LE_U16_e32
18935 { 2873, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2873 = V_CMPX_LE_U16_e64
18936 { 2874, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2874 = V_CMPX_LE_U16_nosdst_e32
18937 { 2875, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2875 = V_CMPX_LE_U16_nosdst_e64
18938 { 2876, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2876 = V_CMPX_LE_U16_nosdst_sdwa
18939 { 2877, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2877 = V_CMPX_LE_U16_sdwa
18940 { 2878, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2878 = V_CMPX_LE_U32_e32
18941 { 2879, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2879 = V_CMPX_LE_U32_e64
18942 { 2880, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2880 = V_CMPX_LE_U32_nosdst_e32
18943 { 2881, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2881 = V_CMPX_LE_U32_nosdst_e64
18944 { 2882, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2882 = V_CMPX_LE_U32_nosdst_sdwa
18945 { 2883, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2883 = V_CMPX_LE_U32_sdwa
18946 { 2884, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2884 = V_CMPX_LE_U64_e32
18947 { 2885, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2885 = V_CMPX_LE_U64_e64
18948 { 2886, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2886 = V_CMPX_LE_U64_nosdst_e32
18949 { 2887, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2887 = V_CMPX_LE_U64_nosdst_e64
18950 { 2888, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2888 = V_CMPX_LG_F16_e32
18951 { 2889, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2889 = V_CMPX_LG_F16_e64
18952 { 2890, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2890 = V_CMPX_LG_F16_nosdst_e32
18953 { 2891, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2891 = V_CMPX_LG_F16_nosdst_e64
18954 { 2892, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2892 = V_CMPX_LG_F16_nosdst_sdwa
18955 { 2893, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2893 = V_CMPX_LG_F16_sdwa
18956 { 2894, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2894 = V_CMPX_LG_F32_e32
18957 { 2895, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2895 = V_CMPX_LG_F32_e64
18958 { 2896, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2896 = V_CMPX_LG_F32_nosdst_e32
18959 { 2897, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2897 = V_CMPX_LG_F32_nosdst_e64
18960 { 2898, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2898 = V_CMPX_LG_F32_nosdst_sdwa
18961 { 2899, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2899 = V_CMPX_LG_F32_sdwa
18962 { 2900, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2900 = V_CMPX_LG_F64_e32
18963 { 2901, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2901 = V_CMPX_LG_F64_e64
18964 { 2902, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2902 = V_CMPX_LG_F64_nosdst_e32
18965 { 2903, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2903 = V_CMPX_LG_F64_nosdst_e64
18966 { 2904, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2904 = V_CMPX_LT_F16_e32
18967 { 2905, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2905 = V_CMPX_LT_F16_e64
18968 { 2906, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2906 = V_CMPX_LT_F16_nosdst_e32
18969 { 2907, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2907 = V_CMPX_LT_F16_nosdst_e64
18970 { 2908, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2908 = V_CMPX_LT_F16_nosdst_sdwa
18971 { 2909, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2909 = V_CMPX_LT_F16_sdwa
18972 { 2910, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2910 = V_CMPX_LT_F32_e32
18973 { 2911, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2911 = V_CMPX_LT_F32_e64
18974 { 2912, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2912 = V_CMPX_LT_F32_nosdst_e32
18975 { 2913, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2913 = V_CMPX_LT_F32_nosdst_e64
18976 { 2914, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2914 = V_CMPX_LT_F32_nosdst_sdwa
18977 { 2915, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2915 = V_CMPX_LT_F32_sdwa
18978 { 2916, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2916 = V_CMPX_LT_F64_e32
18979 { 2917, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2917 = V_CMPX_LT_F64_e64
18980 { 2918, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2918 = V_CMPX_LT_F64_nosdst_e32
18981 { 2919, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2919 = V_CMPX_LT_F64_nosdst_e64
18982 { 2920, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2920 = V_CMPX_LT_I16_e32
18983 { 2921, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2921 = V_CMPX_LT_I16_e64
18984 { 2922, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2922 = V_CMPX_LT_I16_nosdst_e32
18985 { 2923, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2923 = V_CMPX_LT_I16_nosdst_e64
18986 { 2924, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2924 = V_CMPX_LT_I16_nosdst_sdwa
18987 { 2925, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2925 = V_CMPX_LT_I16_sdwa
18988 { 2926, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2926 = V_CMPX_LT_I32_e32
18989 { 2927, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2927 = V_CMPX_LT_I32_e64
18990 { 2928, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2928 = V_CMPX_LT_I32_nosdst_e32
18991 { 2929, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2929 = V_CMPX_LT_I32_nosdst_e64
18992 { 2930, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2930 = V_CMPX_LT_I32_nosdst_sdwa
18993 { 2931, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2931 = V_CMPX_LT_I32_sdwa
18994 { 2932, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2932 = V_CMPX_LT_I64_e32
18995 { 2933, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2933 = V_CMPX_LT_I64_e64
18996 { 2934, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2934 = V_CMPX_LT_I64_nosdst_e32
18997 { 2935, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2935 = V_CMPX_LT_I64_nosdst_e64
18998 { 2936, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2936 = V_CMPX_LT_U16_e32
18999 { 2937, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2937 = V_CMPX_LT_U16_e64
19000 { 2938, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2938 = V_CMPX_LT_U16_nosdst_e32
19001 { 2939, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2939 = V_CMPX_LT_U16_nosdst_e64
19002 { 2940, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2940 = V_CMPX_LT_U16_nosdst_sdwa
19003 { 2941, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2941 = V_CMPX_LT_U16_sdwa
19004 { 2942, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2942 = V_CMPX_LT_U32_e32
19005 { 2943, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2943 = V_CMPX_LT_U32_e64
19006 { 2944, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2944 = V_CMPX_LT_U32_nosdst_e32
19007 { 2945, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2945 = V_CMPX_LT_U32_nosdst_e64
19008 { 2946, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2946 = V_CMPX_LT_U32_nosdst_sdwa
19009 { 2947, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2947 = V_CMPX_LT_U32_sdwa
19010 { 2948, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2948 = V_CMPX_LT_U64_e32
19011 { 2949, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2949 = V_CMPX_LT_U64_e64
19012 { 2950, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2950 = V_CMPX_LT_U64_nosdst_e32
19013 { 2951, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2951 = V_CMPX_LT_U64_nosdst_e64
19014 { 2952, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #2952 = V_CMPX_NEQ_F16_e32
19015 { 2953, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #2953 = V_CMPX_NEQ_F16_e64
19016 { 2954, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #2954 = V_CMPX_NEQ_F16_nosdst_e32
19017 { 2955, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #2955 = V_CMPX_NEQ_F16_nosdst_e64
19018 { 2956, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #2956 = V_CMPX_NEQ_F16_nosdst_sdwa
19019 { 2957, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #2957 = V_CMPX_NEQ_F16_sdwa
19020 { 2958, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #2958 = V_CMPX_NEQ_F32_e32
19021 { 2959, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #2959 = V_CMPX_NEQ_F32_e64
19022 { 2960, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #2960 = V_CMPX_NEQ_F32_nosdst_e32
19023 { 2961, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #2961 = V_CMPX_NEQ_F32_nosdst_e64
19024 { 2962, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #2962 = V_CMPX_NEQ_F32_nosdst_sdwa
19025 { 2963, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #2963 = V_CMPX_NEQ_F32_sdwa
19026 { 2964, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #2964 = V_CMPX_NEQ_F64_e32
19027 { 2965, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #2965 = V_CMPX_NEQ_F64_e64
19028 { 2966, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #2966 = V_CMPX_NEQ_F64_nosdst_e32
19029 { 2967, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #2967 = V_CMPX_NEQ_F64_nosdst_e64
19030 { 2968, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2968 = V_CMPX_NE_I16_e32
19031 { 2969, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2969 = V_CMPX_NE_I16_e64
19032 { 2970, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2970 = V_CMPX_NE_I16_nosdst_e32
19033 { 2971, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2971 = V_CMPX_NE_I16_nosdst_e64
19034 { 2972, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2972 = V_CMPX_NE_I16_nosdst_sdwa
19035 { 2973, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2973 = V_CMPX_NE_I16_sdwa
19036 { 2974, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2974 = V_CMPX_NE_I32_e32
19037 { 2975, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2975 = V_CMPX_NE_I32_e64
19038 { 2976, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2976 = V_CMPX_NE_I32_nosdst_e32
19039 { 2977, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2977 = V_CMPX_NE_I32_nosdst_e64
19040 { 2978, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2978 = V_CMPX_NE_I32_nosdst_sdwa
19041 { 2979, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2979 = V_CMPX_NE_I32_sdwa
19042 { 2980, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2980 = V_CMPX_NE_I64_e32
19043 { 2981, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2981 = V_CMPX_NE_I64_e64
19044 { 2982, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2982 = V_CMPX_NE_I64_nosdst_e32
19045 { 2983, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2983 = V_CMPX_NE_I64_nosdst_e64
19046 { 2984, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #2984 = V_CMPX_NE_U16_e32
19047 { 2985, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #2985 = V_CMPX_NE_U16_e64
19048 { 2986, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #2986 = V_CMPX_NE_U16_nosdst_e32
19049 { 2987, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #2987 = V_CMPX_NE_U16_nosdst_e64
19050 { 2988, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #2988 = V_CMPX_NE_U16_nosdst_sdwa
19051 { 2989, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #2989 = V_CMPX_NE_U16_sdwa
19052 { 2990, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #2990 = V_CMPX_NE_U32_e32
19053 { 2991, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #2991 = V_CMPX_NE_U32_e64
19054 { 2992, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #2992 = V_CMPX_NE_U32_nosdst_e32
19055 { 2993, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #2993 = V_CMPX_NE_U32_nosdst_e64
19056 { 2994, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #2994 = V_CMPX_NE_U32_nosdst_sdwa
19057 { 2995, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #2995 = V_CMPX_NE_U32_sdwa
19058 { 2996, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #2996 = V_CMPX_NE_U64_e32
19059 { 2997, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #2997 = V_CMPX_NE_U64_e64
19060 { 2998, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #2998 = V_CMPX_NE_U64_nosdst_e32
19061 { 2999, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #2999 = V_CMPX_NE_U64_nosdst_e64
19062 { 3000, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3000 = V_CMPX_NGE_F16_e32
19063 { 3001, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3001 = V_CMPX_NGE_F16_e64
19064 { 3002, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3002 = V_CMPX_NGE_F16_nosdst_e32
19065 { 3003, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3003 = V_CMPX_NGE_F16_nosdst_e64
19066 { 3004, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3004 = V_CMPX_NGE_F16_nosdst_sdwa
19067 { 3005, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3005 = V_CMPX_NGE_F16_sdwa
19068 { 3006, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3006 = V_CMPX_NGE_F32_e32
19069 { 3007, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3007 = V_CMPX_NGE_F32_e64
19070 { 3008, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3008 = V_CMPX_NGE_F32_nosdst_e32
19071 { 3009, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3009 = V_CMPX_NGE_F32_nosdst_e64
19072 { 3010, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3010 = V_CMPX_NGE_F32_nosdst_sdwa
19073 { 3011, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3011 = V_CMPX_NGE_F32_sdwa
19074 { 3012, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3012 = V_CMPX_NGE_F64_e32
19075 { 3013, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3013 = V_CMPX_NGE_F64_e64
19076 { 3014, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3014 = V_CMPX_NGE_F64_nosdst_e32
19077 { 3015, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3015 = V_CMPX_NGE_F64_nosdst_e64
19078 { 3016, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3016 = V_CMPX_NGT_F16_e32
19079 { 3017, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3017 = V_CMPX_NGT_F16_e64
19080 { 3018, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3018 = V_CMPX_NGT_F16_nosdst_e32
19081 { 3019, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3019 = V_CMPX_NGT_F16_nosdst_e64
19082 { 3020, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3020 = V_CMPX_NGT_F16_nosdst_sdwa
19083 { 3021, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3021 = V_CMPX_NGT_F16_sdwa
19084 { 3022, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3022 = V_CMPX_NGT_F32_e32
19085 { 3023, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3023 = V_CMPX_NGT_F32_e64
19086 { 3024, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3024 = V_CMPX_NGT_F32_nosdst_e32
19087 { 3025, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3025 = V_CMPX_NGT_F32_nosdst_e64
19088 { 3026, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3026 = V_CMPX_NGT_F32_nosdst_sdwa
19089 { 3027, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3027 = V_CMPX_NGT_F32_sdwa
19090 { 3028, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3028 = V_CMPX_NGT_F64_e32
19091 { 3029, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3029 = V_CMPX_NGT_F64_e64
19092 { 3030, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3030 = V_CMPX_NGT_F64_nosdst_e32
19093 { 3031, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3031 = V_CMPX_NGT_F64_nosdst_e64
19094 { 3032, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3032 = V_CMPX_NLE_F16_e32
19095 { 3033, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3033 = V_CMPX_NLE_F16_e64
19096 { 3034, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3034 = V_CMPX_NLE_F16_nosdst_e32
19097 { 3035, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3035 = V_CMPX_NLE_F16_nosdst_e64
19098 { 3036, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3036 = V_CMPX_NLE_F16_nosdst_sdwa
19099 { 3037, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3037 = V_CMPX_NLE_F16_sdwa
19100 { 3038, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3038 = V_CMPX_NLE_F32_e32
19101 { 3039, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3039 = V_CMPX_NLE_F32_e64
19102 { 3040, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3040 = V_CMPX_NLE_F32_nosdst_e32
19103 { 3041, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3041 = V_CMPX_NLE_F32_nosdst_e64
19104 { 3042, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3042 = V_CMPX_NLE_F32_nosdst_sdwa
19105 { 3043, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3043 = V_CMPX_NLE_F32_sdwa
19106 { 3044, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3044 = V_CMPX_NLE_F64_e32
19107 { 3045, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3045 = V_CMPX_NLE_F64_e64
19108 { 3046, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3046 = V_CMPX_NLE_F64_nosdst_e32
19109 { 3047, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3047 = V_CMPX_NLE_F64_nosdst_e64
19110 { 3048, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3048 = V_CMPX_NLG_F16_e32
19111 { 3049, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3049 = V_CMPX_NLG_F16_e64
19112 { 3050, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3050 = V_CMPX_NLG_F16_nosdst_e32
19113 { 3051, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3051 = V_CMPX_NLG_F16_nosdst_e64
19114 { 3052, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3052 = V_CMPX_NLG_F16_nosdst_sdwa
19115 { 3053, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3053 = V_CMPX_NLG_F16_sdwa
19116 { 3054, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3054 = V_CMPX_NLG_F32_e32
19117 { 3055, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3055 = V_CMPX_NLG_F32_e64
19118 { 3056, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3056 = V_CMPX_NLG_F32_nosdst_e32
19119 { 3057, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3057 = V_CMPX_NLG_F32_nosdst_e64
19120 { 3058, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3058 = V_CMPX_NLG_F32_nosdst_sdwa
19121 { 3059, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3059 = V_CMPX_NLG_F32_sdwa
19122 { 3060, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3060 = V_CMPX_NLG_F64_e32
19123 { 3061, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3061 = V_CMPX_NLG_F64_e64
19124 { 3062, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3062 = V_CMPX_NLG_F64_nosdst_e32
19125 { 3063, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3063 = V_CMPX_NLG_F64_nosdst_e64
19126 { 3064, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3064 = V_CMPX_NLT_F16_e32
19127 { 3065, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3065 = V_CMPX_NLT_F16_e64
19128 { 3066, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3066 = V_CMPX_NLT_F16_nosdst_e32
19129 { 3067, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3067 = V_CMPX_NLT_F16_nosdst_e64
19130 { 3068, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3068 = V_CMPX_NLT_F16_nosdst_sdwa
19131 { 3069, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3069 = V_CMPX_NLT_F16_sdwa
19132 { 3070, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3070 = V_CMPX_NLT_F32_e32
19133 { 3071, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3071 = V_CMPX_NLT_F32_e64
19134 { 3072, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3072 = V_CMPX_NLT_F32_nosdst_e32
19135 { 3073, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3073 = V_CMPX_NLT_F32_nosdst_e64
19136 { 3074, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3074 = V_CMPX_NLT_F32_nosdst_sdwa
19137 { 3075, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3075 = V_CMPX_NLT_F32_sdwa
19138 { 3076, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3076 = V_CMPX_NLT_F64_e32
19139 { 3077, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3077 = V_CMPX_NLT_F64_e64
19140 { 3078, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3078 = V_CMPX_NLT_F64_nosdst_e32
19141 { 3079, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3079 = V_CMPX_NLT_F64_nosdst_e64
19142 { 3080, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3080 = V_CMPX_O_F16_e32
19143 { 3081, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3081 = V_CMPX_O_F16_e64
19144 { 3082, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3082 = V_CMPX_O_F16_nosdst_e32
19145 { 3083, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3083 = V_CMPX_O_F16_nosdst_e64
19146 { 3084, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3084 = V_CMPX_O_F16_nosdst_sdwa
19147 { 3085, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3085 = V_CMPX_O_F16_sdwa
19148 { 3086, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3086 = V_CMPX_O_F32_e32
19149 { 3087, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3087 = V_CMPX_O_F32_e64
19150 { 3088, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3088 = V_CMPX_O_F32_nosdst_e32
19151 { 3089, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3089 = V_CMPX_O_F32_nosdst_e64
19152 { 3090, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3090 = V_CMPX_O_F32_nosdst_sdwa
19153 { 3091, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3091 = V_CMPX_O_F32_sdwa
19154 { 3092, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3092 = V_CMPX_O_F64_e32
19155 { 3093, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3093 = V_CMPX_O_F64_e64
19156 { 3094, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3094 = V_CMPX_O_F64_nosdst_e32
19157 { 3095, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3095 = V_CMPX_O_F64_nosdst_e64
19158 { 3096, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3096 = V_CMPX_TRU_F16_e32
19159 { 3097, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3097 = V_CMPX_TRU_F16_e64
19160 { 3098, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3098 = V_CMPX_TRU_F16_nosdst_e32
19161 { 3099, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3099 = V_CMPX_TRU_F16_nosdst_e64
19162 { 3100, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3100 = V_CMPX_TRU_F16_nosdst_sdwa
19163 { 3101, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3101 = V_CMPX_TRU_F16_sdwa
19164 { 3102, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3102 = V_CMPX_TRU_F32_e32
19165 { 3103, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3103 = V_CMPX_TRU_F32_e64
19166 { 3104, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3104 = V_CMPX_TRU_F32_nosdst_e32
19167 { 3105, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3105 = V_CMPX_TRU_F32_nosdst_e64
19168 { 3106, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3106 = V_CMPX_TRU_F32_nosdst_sdwa
19169 { 3107, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3107 = V_CMPX_TRU_F32_sdwa
19170 { 3108, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3108 = V_CMPX_TRU_F64_e32
19171 { 3109, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3109 = V_CMPX_TRU_F64_e64
19172 { 3110, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3110 = V_CMPX_TRU_F64_nosdst_e32
19173 { 3111, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3111 = V_CMPX_TRU_F64_nosdst_e64
19174 { 3112, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #3112 = V_CMPX_T_I16_e32
19175 { 3113, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #3113 = V_CMPX_T_I16_e64
19176 { 3114, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #3114 = V_CMPX_T_I16_nosdst_e32
19177 { 3115, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #3115 = V_CMPX_T_I16_nosdst_e64
19178 { 3116, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #3116 = V_CMPX_T_I16_nosdst_sdwa
19179 { 3117, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #3117 = V_CMPX_T_I16_sdwa
19180 { 3118, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #3118 = V_CMPX_T_I32_e32
19181 { 3119, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #3119 = V_CMPX_T_I32_e64
19182 { 3120, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #3120 = V_CMPX_T_I32_nosdst_e32
19183 { 3121, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #3121 = V_CMPX_T_I32_nosdst_e64
19184 { 3122, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #3122 = V_CMPX_T_I32_nosdst_sdwa
19185 { 3123, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #3123 = V_CMPX_T_I32_sdwa
19186 { 3124, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #3124 = V_CMPX_T_I64_e32
19187 { 3125, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #3125 = V_CMPX_T_I64_e64
19188 { 3126, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #3126 = V_CMPX_T_I64_nosdst_e32
19189 { 3127, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #3127 = V_CMPX_T_I64_nosdst_e64
19190 { 3128, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo330, -1 ,nullptr }, // Inst #3128 = V_CMPX_T_U16_e32
19191 { 3129, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo331, -1 ,nullptr }, // Inst #3129 = V_CMPX_T_U16_e64
19192 { 3130, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo330, -1 ,nullptr }, // Inst #3130 = V_CMPX_T_U16_nosdst_e32
19193 { 3131, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo332, -1 ,nullptr }, // Inst #3131 = V_CMPX_T_U16_nosdst_e64
19194 { 3132, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo333, -1 ,nullptr }, // Inst #3132 = V_CMPX_T_U16_nosdst_sdwa
19195 { 3133, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo334, -1 ,nullptr }, // Inst #3133 = V_CMPX_T_U16_sdwa
19196 { 3134, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo335, -1 ,nullptr }, // Inst #3134 = V_CMPX_T_U32_e32
19197 { 3135, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo336, -1 ,nullptr }, // Inst #3135 = V_CMPX_T_U32_e64
19198 { 3136, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo335, -1 ,nullptr }, // Inst #3136 = V_CMPX_T_U32_nosdst_e32
19199 { 3137, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo337, -1 ,nullptr }, // Inst #3137 = V_CMPX_T_U32_nosdst_e64
19200 { 3138, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo338, -1 ,nullptr }, // Inst #3138 = V_CMPX_T_U32_nosdst_sdwa
19201 { 3139, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo339, -1 ,nullptr }, // Inst #3139 = V_CMPX_T_U32_sdwa
19202 { 3140, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo340, -1 ,nullptr }, // Inst #3140 = V_CMPX_T_U64_e32
19203 { 3141, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo341, -1 ,nullptr }, // Inst #3141 = V_CMPX_T_U64_e64
19204 { 3142, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo340, -1 ,nullptr }, // Inst #3142 = V_CMPX_T_U64_nosdst_e32
19205 { 3143, 2, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, ImplicitList2, OperandInfo342, -1 ,nullptr }, // Inst #3143 = V_CMPX_T_U64_nosdst_e64
19206 { 3144, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo318, -1 ,nullptr }, // Inst #3144 = V_CMPX_U_F16_e32
19207 { 3145, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo328, -1 ,nullptr }, // Inst #3145 = V_CMPX_U_F16_e64
19208 { 3146, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo318, -1 ,nullptr }, // Inst #3146 = V_CMPX_U_F16_nosdst_e32
19209 { 3147, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo329, -1 ,nullptr }, // Inst #3147 = V_CMPX_U_F16_nosdst_e64
19210 { 3148, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo321, -1 ,nullptr }, // Inst #3148 = V_CMPX_U_F16_nosdst_sdwa
19211 { 3149, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo322, -1 ,nullptr }, // Inst #3149 = V_CMPX_U_F16_sdwa
19212 { 3150, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo310, -1 ,nullptr }, // Inst #3150 = V_CMPX_U_F32_e32
19213 { 3151, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo311, -1 ,nullptr }, // Inst #3151 = V_CMPX_U_F32_e64
19214 { 3152, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo310, -1 ,nullptr }, // Inst #3152 = V_CMPX_U_F32_nosdst_e32
19215 { 3153, 5, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo312, -1 ,nullptr }, // Inst #3153 = V_CMPX_U_F32_nosdst_e64
19216 { 3154, 6, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList2, OperandInfo313, -1 ,nullptr }, // Inst #3154 = V_CMPX_U_F32_nosdst_sdwa
19217 { 3155, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x4002ULL, ImplicitList2, ImplicitList13, OperandInfo314, -1 ,nullptr }, // Inst #3155 = V_CMPX_U_F32_sdwa
19218 { 3156, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList13, OperandInfo315, -1 ,nullptr }, // Inst #3156 = V_CMPX_U_F64_e32
19219 { 3157, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo316, -1 ,nullptr }, // Inst #3157 = V_CMPX_U_F64_e64
19220 { 3158, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x202ULL, ImplicitList2, ImplicitList2, OperandInfo315, -1 ,nullptr }, // Inst #3158 = V_CMPX_U_F64_nosdst_e32
19221 { 3159, 5, 0, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, ImplicitList2, OperandInfo317, -1 ,nullptr }, // Inst #3159 = V_CMPX_U_F64_nosdst_e64
19222 { 3160, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3160 = V_CMP_CLASS_F16_e32
19223 { 3161, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #3161 = V_CMP_CLASS_F16_e64
19224 { 3162, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3162 = V_CMP_CLASS_F16_sdwa
19225 { 3163, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3163 = V_CMP_CLASS_F32_e32
19226 { 3164, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #3164 = V_CMP_CLASS_F32_e64
19227 { 3165, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3165 = V_CMP_CLASS_F32_sdwa
19228 { 3166, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo325, -1 ,nullptr }, // Inst #3166 = V_CMP_CLASS_F64_e32
19229 { 3167, 4, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #3167 = V_CMP_CLASS_F64_e64
19230 { 3168, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3168 = V_CMP_EQ_F16_e32
19231 { 3169, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3169 = V_CMP_EQ_F16_e64
19232 { 3170, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3170 = V_CMP_EQ_F16_sdwa
19233 { 3171, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3171 = V_CMP_EQ_F32_e32
19234 { 3172, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3172 = V_CMP_EQ_F32_e64
19235 { 3173, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3173 = V_CMP_EQ_F32_sdwa
19236 { 3174, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3174 = V_CMP_EQ_F64_e32
19237 { 3175, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3175 = V_CMP_EQ_F64_e64
19238 { 3176, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3176 = V_CMP_EQ_I16_e32
19239 { 3177, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3177 = V_CMP_EQ_I16_e64
19240 { 3178, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3178 = V_CMP_EQ_I16_sdwa
19241 { 3179, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3179 = V_CMP_EQ_I32_e32
19242 { 3180, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3180 = V_CMP_EQ_I32_e64
19243 { 3181, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3181 = V_CMP_EQ_I32_sdwa
19244 { 3182, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3182 = V_CMP_EQ_I64_e32
19245 { 3183, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3183 = V_CMP_EQ_I64_e64
19246 { 3184, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3184 = V_CMP_EQ_U16_e32
19247 { 3185, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3185 = V_CMP_EQ_U16_e64
19248 { 3186, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3186 = V_CMP_EQ_U16_sdwa
19249 { 3187, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3187 = V_CMP_EQ_U32_e32
19250 { 3188, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3188 = V_CMP_EQ_U32_e64
19251 { 3189, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3189 = V_CMP_EQ_U32_sdwa
19252 { 3190, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3190 = V_CMP_EQ_U64_e32
19253 { 3191, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3191 = V_CMP_EQ_U64_e64
19254 { 3192, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3192 = V_CMP_F_F16_e32
19255 { 3193, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3193 = V_CMP_F_F16_e64
19256 { 3194, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3194 = V_CMP_F_F16_sdwa
19257 { 3195, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3195 = V_CMP_F_F32_e32
19258 { 3196, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3196 = V_CMP_F_F32_e64
19259 { 3197, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3197 = V_CMP_F_F32_sdwa
19260 { 3198, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3198 = V_CMP_F_F64_e32
19261 { 3199, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3199 = V_CMP_F_F64_e64
19262 { 3200, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3200 = V_CMP_F_I16_e32
19263 { 3201, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3201 = V_CMP_F_I16_e64
19264 { 3202, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3202 = V_CMP_F_I16_sdwa
19265 { 3203, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3203 = V_CMP_F_I32_e32
19266 { 3204, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3204 = V_CMP_F_I32_e64
19267 { 3205, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3205 = V_CMP_F_I32_sdwa
19268 { 3206, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3206 = V_CMP_F_I64_e32
19269 { 3207, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3207 = V_CMP_F_I64_e64
19270 { 3208, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3208 = V_CMP_F_U16_e32
19271 { 3209, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3209 = V_CMP_F_U16_e64
19272 { 3210, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3210 = V_CMP_F_U16_sdwa
19273 { 3211, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3211 = V_CMP_F_U32_e32
19274 { 3212, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3212 = V_CMP_F_U32_e64
19275 { 3213, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3213 = V_CMP_F_U32_sdwa
19276 { 3214, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3214 = V_CMP_F_U64_e32
19277 { 3215, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3215 = V_CMP_F_U64_e64
19278 { 3216, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3216 = V_CMP_GE_F16_e32
19279 { 3217, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3217 = V_CMP_GE_F16_e64
19280 { 3218, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3218 = V_CMP_GE_F16_sdwa
19281 { 3219, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3219 = V_CMP_GE_F32_e32
19282 { 3220, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3220 = V_CMP_GE_F32_e64
19283 { 3221, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3221 = V_CMP_GE_F32_sdwa
19284 { 3222, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3222 = V_CMP_GE_F64_e32
19285 { 3223, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3223 = V_CMP_GE_F64_e64
19286 { 3224, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3224 = V_CMP_GE_I16_e32
19287 { 3225, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3225 = V_CMP_GE_I16_e64
19288 { 3226, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3226 = V_CMP_GE_I16_sdwa
19289 { 3227, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3227 = V_CMP_GE_I32_e32
19290 { 3228, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3228 = V_CMP_GE_I32_e64
19291 { 3229, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3229 = V_CMP_GE_I32_sdwa
19292 { 3230, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3230 = V_CMP_GE_I64_e32
19293 { 3231, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3231 = V_CMP_GE_I64_e64
19294 { 3232, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3232 = V_CMP_GE_U16_e32
19295 { 3233, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3233 = V_CMP_GE_U16_e64
19296 { 3234, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3234 = V_CMP_GE_U16_sdwa
19297 { 3235, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3235 = V_CMP_GE_U32_e32
19298 { 3236, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3236 = V_CMP_GE_U32_e64
19299 { 3237, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3237 = V_CMP_GE_U32_sdwa
19300 { 3238, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3238 = V_CMP_GE_U64_e32
19301 { 3239, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3239 = V_CMP_GE_U64_e64
19302 { 3240, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3240 = V_CMP_GT_F16_e32
19303 { 3241, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3241 = V_CMP_GT_F16_e64
19304 { 3242, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3242 = V_CMP_GT_F16_sdwa
19305 { 3243, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3243 = V_CMP_GT_F32_e32
19306 { 3244, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3244 = V_CMP_GT_F32_e64
19307 { 3245, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3245 = V_CMP_GT_F32_sdwa
19308 { 3246, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3246 = V_CMP_GT_F64_e32
19309 { 3247, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3247 = V_CMP_GT_F64_e64
19310 { 3248, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3248 = V_CMP_GT_I16_e32
19311 { 3249, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3249 = V_CMP_GT_I16_e64
19312 { 3250, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3250 = V_CMP_GT_I16_sdwa
19313 { 3251, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3251 = V_CMP_GT_I32_e32
19314 { 3252, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3252 = V_CMP_GT_I32_e64
19315 { 3253, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3253 = V_CMP_GT_I32_sdwa
19316 { 3254, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3254 = V_CMP_GT_I64_e32
19317 { 3255, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3255 = V_CMP_GT_I64_e64
19318 { 3256, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3256 = V_CMP_GT_U16_e32
19319 { 3257, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3257 = V_CMP_GT_U16_e64
19320 { 3258, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3258 = V_CMP_GT_U16_sdwa
19321 { 3259, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3259 = V_CMP_GT_U32_e32
19322 { 3260, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3260 = V_CMP_GT_U32_e64
19323 { 3261, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3261 = V_CMP_GT_U32_sdwa
19324 { 3262, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3262 = V_CMP_GT_U64_e32
19325 { 3263, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3263 = V_CMP_GT_U64_e64
19326 { 3264, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3264 = V_CMP_LE_F16_e32
19327 { 3265, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3265 = V_CMP_LE_F16_e64
19328 { 3266, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3266 = V_CMP_LE_F16_sdwa
19329 { 3267, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3267 = V_CMP_LE_F32_e32
19330 { 3268, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3268 = V_CMP_LE_F32_e64
19331 { 3269, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3269 = V_CMP_LE_F32_sdwa
19332 { 3270, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3270 = V_CMP_LE_F64_e32
19333 { 3271, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3271 = V_CMP_LE_F64_e64
19334 { 3272, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3272 = V_CMP_LE_I16_e32
19335 { 3273, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3273 = V_CMP_LE_I16_e64
19336 { 3274, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3274 = V_CMP_LE_I16_sdwa
19337 { 3275, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3275 = V_CMP_LE_I32_e32
19338 { 3276, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3276 = V_CMP_LE_I32_e64
19339 { 3277, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3277 = V_CMP_LE_I32_sdwa
19340 { 3278, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3278 = V_CMP_LE_I64_e32
19341 { 3279, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3279 = V_CMP_LE_I64_e64
19342 { 3280, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3280 = V_CMP_LE_U16_e32
19343 { 3281, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3281 = V_CMP_LE_U16_e64
19344 { 3282, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3282 = V_CMP_LE_U16_sdwa
19345 { 3283, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3283 = V_CMP_LE_U32_e32
19346 { 3284, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3284 = V_CMP_LE_U32_e64
19347 { 3285, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3285 = V_CMP_LE_U32_sdwa
19348 { 3286, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3286 = V_CMP_LE_U64_e32
19349 { 3287, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3287 = V_CMP_LE_U64_e64
19350 { 3288, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3288 = V_CMP_LG_F16_e32
19351 { 3289, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3289 = V_CMP_LG_F16_e64
19352 { 3290, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3290 = V_CMP_LG_F16_sdwa
19353 { 3291, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3291 = V_CMP_LG_F32_e32
19354 { 3292, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3292 = V_CMP_LG_F32_e64
19355 { 3293, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3293 = V_CMP_LG_F32_sdwa
19356 { 3294, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3294 = V_CMP_LG_F64_e32
19357 { 3295, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3295 = V_CMP_LG_F64_e64
19358 { 3296, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3296 = V_CMP_LT_F16_e32
19359 { 3297, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3297 = V_CMP_LT_F16_e64
19360 { 3298, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3298 = V_CMP_LT_F16_sdwa
19361 { 3299, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3299 = V_CMP_LT_F32_e32
19362 { 3300, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3300 = V_CMP_LT_F32_e64
19363 { 3301, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3301 = V_CMP_LT_F32_sdwa
19364 { 3302, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3302 = V_CMP_LT_F64_e32
19365 { 3303, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3303 = V_CMP_LT_F64_e64
19366 { 3304, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3304 = V_CMP_LT_I16_e32
19367 { 3305, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3305 = V_CMP_LT_I16_e64
19368 { 3306, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3306 = V_CMP_LT_I16_sdwa
19369 { 3307, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3307 = V_CMP_LT_I32_e32
19370 { 3308, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3308 = V_CMP_LT_I32_e64
19371 { 3309, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3309 = V_CMP_LT_I32_sdwa
19372 { 3310, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3310 = V_CMP_LT_I64_e32
19373 { 3311, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3311 = V_CMP_LT_I64_e64
19374 { 3312, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3312 = V_CMP_LT_U16_e32
19375 { 3313, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3313 = V_CMP_LT_U16_e64
19376 { 3314, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3314 = V_CMP_LT_U16_sdwa
19377 { 3315, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3315 = V_CMP_LT_U32_e32
19378 { 3316, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3316 = V_CMP_LT_U32_e64
19379 { 3317, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3317 = V_CMP_LT_U32_sdwa
19380 { 3318, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3318 = V_CMP_LT_U64_e32
19381 { 3319, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3319 = V_CMP_LT_U64_e64
19382 { 3320, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3320 = V_CMP_NEQ_F16_e32
19383 { 3321, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3321 = V_CMP_NEQ_F16_e64
19384 { 3322, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3322 = V_CMP_NEQ_F16_sdwa
19385 { 3323, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3323 = V_CMP_NEQ_F32_e32
19386 { 3324, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3324 = V_CMP_NEQ_F32_e64
19387 { 3325, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3325 = V_CMP_NEQ_F32_sdwa
19388 { 3326, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3326 = V_CMP_NEQ_F64_e32
19389 { 3327, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3327 = V_CMP_NEQ_F64_e64
19390 { 3328, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3328 = V_CMP_NE_I16_e32
19391 { 3329, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3329 = V_CMP_NE_I16_e64
19392 { 3330, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3330 = V_CMP_NE_I16_sdwa
19393 { 3331, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3331 = V_CMP_NE_I32_e32
19394 { 3332, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3332 = V_CMP_NE_I32_e64
19395 { 3333, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3333 = V_CMP_NE_I32_sdwa
19396 { 3334, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3334 = V_CMP_NE_I64_e32
19397 { 3335, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3335 = V_CMP_NE_I64_e64
19398 { 3336, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3336 = V_CMP_NE_U16_e32
19399 { 3337, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3337 = V_CMP_NE_U16_e64
19400 { 3338, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3338 = V_CMP_NE_U16_sdwa
19401 { 3339, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3339 = V_CMP_NE_U32_e32
19402 { 3340, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3340 = V_CMP_NE_U32_e64
19403 { 3341, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3341 = V_CMP_NE_U32_sdwa
19404 { 3342, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3342 = V_CMP_NE_U64_e32
19405 { 3343, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3343 = V_CMP_NE_U64_e64
19406 { 3344, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3344 = V_CMP_NGE_F16_e32
19407 { 3345, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3345 = V_CMP_NGE_F16_e64
19408 { 3346, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3346 = V_CMP_NGE_F16_sdwa
19409 { 3347, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3347 = V_CMP_NGE_F32_e32
19410 { 3348, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3348 = V_CMP_NGE_F32_e64
19411 { 3349, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3349 = V_CMP_NGE_F32_sdwa
19412 { 3350, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3350 = V_CMP_NGE_F64_e32
19413 { 3351, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3351 = V_CMP_NGE_F64_e64
19414 { 3352, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3352 = V_CMP_NGT_F16_e32
19415 { 3353, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3353 = V_CMP_NGT_F16_e64
19416 { 3354, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3354 = V_CMP_NGT_F16_sdwa
19417 { 3355, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3355 = V_CMP_NGT_F32_e32
19418 { 3356, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3356 = V_CMP_NGT_F32_e64
19419 { 3357, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3357 = V_CMP_NGT_F32_sdwa
19420 { 3358, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3358 = V_CMP_NGT_F64_e32
19421 { 3359, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3359 = V_CMP_NGT_F64_e64
19422 { 3360, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3360 = V_CMP_NLE_F16_e32
19423 { 3361, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3361 = V_CMP_NLE_F16_e64
19424 { 3362, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3362 = V_CMP_NLE_F16_sdwa
19425 { 3363, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3363 = V_CMP_NLE_F32_e32
19426 { 3364, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3364 = V_CMP_NLE_F32_e64
19427 { 3365, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3365 = V_CMP_NLE_F32_sdwa
19428 { 3366, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3366 = V_CMP_NLE_F64_e32
19429 { 3367, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3367 = V_CMP_NLE_F64_e64
19430 { 3368, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3368 = V_CMP_NLG_F16_e32
19431 { 3369, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3369 = V_CMP_NLG_F16_e64
19432 { 3370, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3370 = V_CMP_NLG_F16_sdwa
19433 { 3371, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3371 = V_CMP_NLG_F32_e32
19434 { 3372, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3372 = V_CMP_NLG_F32_e64
19435 { 3373, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3373 = V_CMP_NLG_F32_sdwa
19436 { 3374, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3374 = V_CMP_NLG_F64_e32
19437 { 3375, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3375 = V_CMP_NLG_F64_e64
19438 { 3376, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3376 = V_CMP_NLT_F16_e32
19439 { 3377, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3377 = V_CMP_NLT_F16_e64
19440 { 3378, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3378 = V_CMP_NLT_F16_sdwa
19441 { 3379, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3379 = V_CMP_NLT_F32_e32
19442 { 3380, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3380 = V_CMP_NLT_F32_e64
19443 { 3381, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3381 = V_CMP_NLT_F32_sdwa
19444 { 3382, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3382 = V_CMP_NLT_F64_e32
19445 { 3383, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3383 = V_CMP_NLT_F64_e64
19446 { 3384, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3384 = V_CMP_O_F16_e32
19447 { 3385, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3385 = V_CMP_O_F16_e64
19448 { 3386, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3386 = V_CMP_O_F16_sdwa
19449 { 3387, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3387 = V_CMP_O_F32_e32
19450 { 3388, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3388 = V_CMP_O_F32_e64
19451 { 3389, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3389 = V_CMP_O_F32_sdwa
19452 { 3390, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3390 = V_CMP_O_F64_e32
19453 { 3391, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3391 = V_CMP_O_F64_e64
19454 { 3392, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3392 = V_CMP_TRU_F16_e32
19455 { 3393, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3393 = V_CMP_TRU_F16_e64
19456 { 3394, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3394 = V_CMP_TRU_F16_sdwa
19457 { 3395, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3395 = V_CMP_TRU_F32_e32
19458 { 3396, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3396 = V_CMP_TRU_F32_e64
19459 { 3397, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3397 = V_CMP_TRU_F32_sdwa
19460 { 3398, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3398 = V_CMP_TRU_F64_e32
19461 { 3399, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3399 = V_CMP_TRU_F64_e64
19462 { 3400, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3400 = V_CMP_T_I16_e32
19463 { 3401, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3401 = V_CMP_T_I16_e64
19464 { 3402, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3402 = V_CMP_T_I16_sdwa
19465 { 3403, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3403 = V_CMP_T_I32_e32
19466 { 3404, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3404 = V_CMP_T_I32_e64
19467 { 3405, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3405 = V_CMP_T_I32_sdwa
19468 { 3406, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3406 = V_CMP_T_I64_e32
19469 { 3407, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3407 = V_CMP_T_I64_e64
19470 { 3408, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo330, -1 ,nullptr }, // Inst #3408 = V_CMP_T_U16_e32
19471 { 3409, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #3409 = V_CMP_T_U16_e64
19472 { 3410, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo334, -1 ,nullptr }, // Inst #3410 = V_CMP_T_U16_sdwa
19473 { 3411, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo335, -1 ,nullptr }, // Inst #3411 = V_CMP_T_U32_e32
19474 { 3412, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #3412 = V_CMP_T_U32_e64
19475 { 3413, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo339, -1 ,nullptr }, // Inst #3413 = V_CMP_T_U32_sdwa
19476 { 3414, 2, 0, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo340, -1 ,nullptr }, // Inst #3414 = V_CMP_T_U64_e32
19477 { 3415, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #3415 = V_CMP_T_U64_e64
19478 { 3416, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo318, -1 ,nullptr }, // Inst #3416 = V_CMP_U_F16_e32
19479 { 3417, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #3417 = V_CMP_U_F16_e64
19480 { 3418, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo322, -1 ,nullptr }, // Inst #3418 = V_CMP_U_F16_sdwa
19481 { 3419, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo310, -1 ,nullptr }, // Inst #3419 = V_CMP_U_F32_e32
19482 { 3420, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #3420 = V_CMP_U_F32_e64
19483 { 3421, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, ImplicitList14, OperandInfo314, -1 ,nullptr }, // Inst #3421 = V_CMP_U_F32_sdwa
19484 { 3422, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x202ULL, ImplicitList2, ImplicitList14, OperandInfo315, -1 ,nullptr }, // Inst #3422 = V_CMP_U_F64_e32
19485 { 3423, 6, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #3423 = V_CMP_U_F64_e64
19486 { 3424, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList13, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3424 = V_CNDMASK_B32_dpp
19487 { 3425, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList13, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3425 = V_CNDMASK_B32_e32
19488 { 3426, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #3426 = V_CNDMASK_B32_e64
19489 { 3427, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList13, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3427 = V_CNDMASK_B32_sdwa
19490 { 3428, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #3428 = V_CNDMASK_B64_PSEUDO
19491 { 3429, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3429 = V_COS_F16_dpp
19492 { 3430, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3430 = V_COS_F16_e32
19493 { 3431, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3431 = V_COS_F16_e64
19494 { 3432, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3432 = V_COS_F16_sdwa
19495 { 3433, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3433 = V_COS_F32_dpp
19496 { 3434, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3434 = V_COS_F32_e32
19497 { 3435, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3435 = V_COS_F32_e64
19498 { 3436, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3436 = V_COS_F32_sdwa
19499 { 3437, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3437 = V_CUBEID_F32
19500 { 3438, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3438 = V_CUBEMA_F32
19501 { 3439, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3439 = V_CUBESC_F32
19502 { 3440, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3440 = V_CUBETC_F32
19503 { 3441, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3441 = V_CVT_F16_F32_dpp
19504 { 3442, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3442 = V_CVT_F16_F32_e32
19505 { 3443, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3443 = V_CVT_F16_F32_e64
19506 { 3444, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3444 = V_CVT_F16_F32_sdwa
19507 { 3445, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3445 = V_CVT_F16_I16_dpp
19508 { 3446, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #3446 = V_CVT_F16_I16_e32
19509 { 3447, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo347, -1 ,nullptr }, // Inst #3447 = V_CVT_F16_I16_e64
19510 { 3448, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo348, -1 ,nullptr }, // Inst #3448 = V_CVT_F16_I16_sdwa
19511 { 3449, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3449 = V_CVT_F16_U16_dpp
19512 { 3450, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #3450 = V_CVT_F16_U16_e32
19513 { 3451, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo347, -1 ,nullptr }, // Inst #3451 = V_CVT_F16_U16_e64
19514 { 3452, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo348, -1 ,nullptr }, // Inst #3452 = V_CVT_F16_U16_sdwa
19515 { 3453, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3453 = V_CVT_F32_F16_dpp
19516 { 3454, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3454 = V_CVT_F32_F16_e32
19517 { 3455, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3455 = V_CVT_F32_F16_e64
19518 { 3456, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3456 = V_CVT_F32_F16_sdwa
19519 { 3457, 2, 1, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #3457 = V_CVT_F32_F64_e32
19520 { 3458, 5, 1, 8, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #3458 = V_CVT_F32_F64_e64
19521 { 3459, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3459 = V_CVT_F32_I32_dpp
19522 { 3460, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3460 = V_CVT_F32_I32_e32
19523 { 3461, 4, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3461 = V_CVT_F32_I32_e64
19524 { 3462, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3462 = V_CVT_F32_I32_sdwa
19525 { 3463, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3463 = V_CVT_F32_U32_dpp
19526 { 3464, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3464 = V_CVT_F32_U32_e32
19527 { 3465, 4, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3465 = V_CVT_F32_U32_e64
19528 { 3466, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3466 = V_CVT_F32_U32_sdwa
19529 { 3467, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3467 = V_CVT_F32_UBYTE0_dpp
19530 { 3468, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3468 = V_CVT_F32_UBYTE0_e32
19531 { 3469, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3469 = V_CVT_F32_UBYTE0_e64
19532 { 3470, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3470 = V_CVT_F32_UBYTE0_sdwa
19533 { 3471, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3471 = V_CVT_F32_UBYTE1_dpp
19534 { 3472, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3472 = V_CVT_F32_UBYTE1_e32
19535 { 3473, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3473 = V_CVT_F32_UBYTE1_e64
19536 { 3474, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3474 = V_CVT_F32_UBYTE1_sdwa
19537 { 3475, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3475 = V_CVT_F32_UBYTE2_dpp
19538 { 3476, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3476 = V_CVT_F32_UBYTE2_e32
19539 { 3477, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3477 = V_CVT_F32_UBYTE2_e64
19540 { 3478, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3478 = V_CVT_F32_UBYTE2_sdwa
19541 { 3479, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3479 = V_CVT_F32_UBYTE3_dpp
19542 { 3480, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3480 = V_CVT_F32_UBYTE3_e32
19543 { 3481, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3481 = V_CVT_F32_UBYTE3_e64
19544 { 3482, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3482 = V_CVT_F32_UBYTE3_sdwa
19545 { 3483, 2, 1, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #3483 = V_CVT_F64_F32_e32
19546 { 3484, 5, 1, 8, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo354, -1 ,nullptr }, // Inst #3484 = V_CVT_F64_F32_e64
19547 { 3485, 2, 1, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #3485 = V_CVT_F64_I32_e32
19548 { 3486, 4, 1, 8, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #3486 = V_CVT_F64_I32_e64
19549 { 3487, 2, 1, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #3487 = V_CVT_F64_U32_e32
19550 { 3488, 4, 1, 8, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #3488 = V_CVT_F64_U32_e64
19551 { 3489, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3489 = V_CVT_FLR_I32_F32_dpp
19552 { 3490, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3490 = V_CVT_FLR_I32_F32_e32
19553 { 3491, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3491 = V_CVT_FLR_I32_F32_e64
19554 { 3492, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #3492 = V_CVT_FLR_I32_F32_sdwa
19555 { 3493, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3493 = V_CVT_I16_F16_dpp
19556 { 3494, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3494 = V_CVT_I16_F16_e32
19557 { 3495, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3495 = V_CVT_I16_F16_e64
19558 { 3496, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3496 = V_CVT_I16_F16_sdwa
19559 { 3497, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3497 = V_CVT_I32_F32_dpp
19560 { 3498, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3498 = V_CVT_I32_F32_e32
19561 { 3499, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3499 = V_CVT_I32_F32_e64
19562 { 3500, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #3500 = V_CVT_I32_F32_sdwa
19563 { 3501, 2, 1, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #3501 = V_CVT_I32_F64_e32
19564 { 3502, 5, 1, 8, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #3502 = V_CVT_I32_F64_e64
19565 { 3503, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3503 = V_CVT_NORM_I16_F16_dpp
19566 { 3504, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3504 = V_CVT_NORM_I16_F16_e32
19567 { 3505, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3505 = V_CVT_NORM_I16_F16_e64
19568 { 3506, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3506 = V_CVT_NORM_I16_F16_sdwa
19569 { 3507, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3507 = V_CVT_NORM_U16_F16_dpp
19570 { 3508, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3508 = V_CVT_NORM_U16_F16_e32
19571 { 3509, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3509 = V_CVT_NORM_U16_F16_e64
19572 { 3510, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3510 = V_CVT_NORM_U16_F16_sdwa
19573 { 3511, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3511 = V_CVT_OFF_F32_I4_dpp
19574 { 3512, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3512 = V_CVT_OFF_F32_I4_e32
19575 { 3513, 4, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #3513 = V_CVT_OFF_F32_I4_e64
19576 { 3514, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #3514 = V_CVT_OFF_F32_I4_sdwa
19577 { 3515, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3515 = V_CVT_PKACCUM_U8_F32_e32
19578 { 3516, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3516 = V_CVT_PKACCUM_U8_F32_e64
19579 { 3517, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3517 = V_CVT_PKNORM_I16_F16
19580 { 3518, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3518 = V_CVT_PKNORM_I16_F32_e32
19581 { 3519, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x1c00000000402ULL, ImplicitList2, nullptr, OperandInfo360, -1 ,nullptr }, // Inst #3519 = V_CVT_PKNORM_I16_F32_e64
19582 { 3520, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3520 = V_CVT_PKNORM_U16_F16
19583 { 3521, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3521 = V_CVT_PKNORM_U16_F32_e32
19584 { 3522, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x1c00000000402ULL, ImplicitList2, nullptr, OperandInfo360, -1 ,nullptr }, // Inst #3522 = V_CVT_PKNORM_U16_F32_e64
19585 { 3523, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3523 = V_CVT_PKRTZ_F16_F32_e32
19586 { 3524, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x1a00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3524 = V_CVT_PKRTZ_F16_F32_e64
19587 { 3525, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3525 = V_CVT_PK_I16_I32_e32
19588 { 3526, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3526 = V_CVT_PK_I16_I32_e64
19589 { 3527, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3527 = V_CVT_PK_U16_U32_e32
19590 { 3528, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3528 = V_CVT_PK_U16_U32_e64
19591 { 3529, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo361, -1 ,nullptr }, // Inst #3529 = V_CVT_PK_U8_F32
19592 { 3530, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3530 = V_CVT_RPI_I32_F32_dpp
19593 { 3531, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3531 = V_CVT_RPI_I32_F32_e32
19594 { 3532, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3532 = V_CVT_RPI_I32_F32_e64
19595 { 3533, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #3533 = V_CVT_RPI_I32_F32_sdwa
19596 { 3534, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3534 = V_CVT_U16_F16_dpp
19597 { 3535, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3535 = V_CVT_U16_F16_e32
19598 { 3536, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3536 = V_CVT_U16_F16_e64
19599 { 3537, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3537 = V_CVT_U16_F16_sdwa
19600 { 3538, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3538 = V_CVT_U32_F32_dpp
19601 { 3539, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3539 = V_CVT_U32_F32_e32
19602 { 3540, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3540 = V_CVT_U32_F32_e64
19603 { 3541, 7, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #3541 = V_CVT_U32_F32_sdwa
19604 { 3542, 2, 1, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #3542 = V_CVT_U32_F64_e32
19605 { 3543, 5, 1, 8, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #3543 = V_CVT_U32_F64_e64
19606 { 3544, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3544 = V_DIV_FIXUP_F16
19607 { 3545, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3545 = V_DIV_FIXUP_F16_gfx9
19608 { 3546, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3546 = V_DIV_FIXUP_F32
19609 { 3547, 9, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #3547 = V_DIV_FIXUP_F64
19610 { 3548, 9, 1, 8, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList13, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3548 = V_DIV_FMAS_F32
19611 { 3549, 9, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList13, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #3549 = V_DIV_FMAS_F64
19612 { 3550, 5, 2, 8, 16, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #3550 = V_DIV_SCALE_F32
19613 { 3551, 5, 2, 8, 17, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000402ULL, ImplicitList2, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #3551 = V_DIV_SCALE_F64
19614 { 3552, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3552 = V_DOT2C_F32_F16_dpp
19615 { 3553, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo367, -1 ,nullptr }, // Inst #3553 = V_DOT2C_F32_F16_e32
19616 { 3554, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo368, -1 ,nullptr }, // Inst #3554 = V_DOT2C_F32_F16_e64
19617 { 3555, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3555 = V_DOT2C_I32_I16_dpp
19618 { 3556, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3556 = V_DOT2C_I32_I16_e32
19619 { 3557, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #3557 = V_DOT2C_I32_I16_e64
19620 { 3558, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82a00000001402ULL, ImplicitList2, nullptr, OperandInfo371, -1 ,nullptr }, // Inst #3558 = V_DOT2_F32_F16
19621 { 3559, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82c00000001402ULL, ImplicitList2, nullptr, OperandInfo372, -1 ,nullptr }, // Inst #3559 = V_DOT2_I32_I16
19622 { 3560, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82c00000001402ULL, ImplicitList2, nullptr, OperandInfo372, -1 ,nullptr }, // Inst #3560 = V_DOT2_U32_U16
19623 { 3561, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3561 = V_DOT4C_I32_I8_dpp
19624 { 3562, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3562 = V_DOT4C_I32_I8_e32
19625 { 3563, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #3563 = V_DOT4C_I32_I8_e64
19626 { 3564, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82c00000001402ULL, ImplicitList2, nullptr, OperandInfo373, -1 ,nullptr }, // Inst #3564 = V_DOT4_I32_I8
19627 { 3565, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82c00000001402ULL, ImplicitList2, nullptr, OperandInfo373, -1 ,nullptr }, // Inst #3565 = V_DOT4_U32_U8
19628 { 3566, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3566 = V_DOT8C_I32_I4_dpp
19629 { 3567, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3567 = V_DOT8C_I32_I4_e32
19630 { 3568, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #3568 = V_DOT8C_I32_I4_e64
19631 { 3569, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82c00000001402ULL, ImplicitList2, nullptr, OperandInfo373, -1 ,nullptr }, // Inst #3569 = V_DOT8_I32_I4
19632 { 3570, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82c00000001402ULL, ImplicitList2, nullptr, OperandInfo373, -1 ,nullptr }, // Inst #3570 = V_DOT8_U32_U4
19633 { 3571, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3571 = V_EXP_F16_dpp
19634 { 3572, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3572 = V_EXP_F16_e32
19635 { 3573, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3573 = V_EXP_F16_e64
19636 { 3574, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3574 = V_EXP_F16_sdwa
19637 { 3575, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3575 = V_EXP_F32_dpp
19638 { 3576, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3576 = V_EXP_F32_e32
19639 { 3577, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3577 = V_EXP_F32_e64
19640 { 3578, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3578 = V_EXP_F32_sdwa
19641 { 3579, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3579 = V_EXP_LEGACY_F32_dpp
19642 { 3580, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3580 = V_EXP_LEGACY_F32_e32
19643 { 3581, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3581 = V_EXP_LEGACY_F32_e64
19644 { 3582, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3582 = V_EXP_LEGACY_F32_sdwa
19645 { 3583, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3583 = V_FFBH_I32_dpp
19646 { 3584, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3584 = V_FFBH_I32_e32
19647 { 3585, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3585 = V_FFBH_I32_e64
19648 { 3586, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3586 = V_FFBH_I32_sdwa
19649 { 3587, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3587 = V_FFBH_U32_dpp
19650 { 3588, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3588 = V_FFBH_U32_e32
19651 { 3589, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3589 = V_FFBH_U32_e64
19652 { 3590, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3590 = V_FFBH_U32_sdwa
19653 { 3591, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3591 = V_FFBL_B32_dpp
19654 { 3592, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3592 = V_FFBL_B32_e32
19655 { 3593, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3593 = V_FFBL_B32_e64
19656 { 3594, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3594 = V_FFBL_B32_sdwa
19657 { 3595, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3595 = V_FLOOR_F16_dpp
19658 { 3596, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3596 = V_FLOOR_F16_e32
19659 { 3597, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3597 = V_FLOOR_F16_e64
19660 { 3598, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3598 = V_FLOOR_F16_sdwa
19661 { 3599, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3599 = V_FLOOR_F32_dpp
19662 { 3600, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3600 = V_FLOOR_F32_e32
19663 { 3601, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3601 = V_FLOOR_F32_e64
19664 { 3602, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3602 = V_FLOOR_F32_sdwa
19665 { 3603, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3603 = V_FLOOR_F64_e32
19666 { 3604, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3604 = V_FLOOR_F64_e64
19667 { 3605, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo374, -1 ,nullptr }, // Inst #3605 = V_FMAAK_F16
19668 { 3606, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo375, -1 ,nullptr }, // Inst #3606 = V_FMAAK_F32
19669 { 3607, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3607 = V_FMAC_F16_dpp
19670 { 3608, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo376, -1 ,nullptr }, // Inst #3608 = V_FMAC_F16_e32
19671 { 3609, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo377, -1 ,nullptr }, // Inst #3609 = V_FMAC_F16_e64
19672 { 3610, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo378, -1 ,nullptr }, // Inst #3610 = V_FMAC_F16_sdwa
19673 { 3611, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3611 = V_FMAC_F32_dpp
19674 { 3612, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo379, -1 ,nullptr }, // Inst #3612 = V_FMAC_F32_e32
19675 { 3613, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo380, -1 ,nullptr }, // Inst #3613 = V_FMAC_F32_e64
19676 { 3614, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo381, -1 ,nullptr }, // Inst #3614 = V_FMAC_F32_sdwa
19677 { 3615, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #3615 = V_FMAMK_F16
19678 { 3616, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo383, -1 ,nullptr }, // Inst #3616 = V_FMAMK_F32
19679 { 3617, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3617 = V_FMA_F16
19680 { 3618, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3618 = V_FMA_F16_gfx9
19681 { 3619, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3619 = V_FMA_F32
19682 { 3620, 9, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #3620 = V_FMA_F64
19683 { 3621, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11200000001402ULL, ImplicitList2, nullptr, OperandInfo384, -1 ,nullptr }, // Inst #3621 = V_FMA_MIXHI_F16
19684 { 3622, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000001402ULL, ImplicitList2, nullptr, OperandInfo384, -1 ,nullptr }, // Inst #3622 = V_FMA_MIXLO_F16
19685 { 3623, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000001402ULL, ImplicitList2, nullptr, OperandInfo385, -1 ,nullptr }, // Inst #3623 = V_FMA_MIX_F32
19686 { 3624, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3624 = V_FRACT_F16_dpp
19687 { 3625, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3625 = V_FRACT_F16_e32
19688 { 3626, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3626 = V_FRACT_F16_e64
19689 { 3627, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3627 = V_FRACT_F16_sdwa
19690 { 3628, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3628 = V_FRACT_F32_dpp
19691 { 3629, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3629 = V_FRACT_F32_e32
19692 { 3630, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3630 = V_FRACT_F32_e64
19693 { 3631, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3631 = V_FRACT_F32_sdwa
19694 { 3632, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000082ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3632 = V_FRACT_F64_e32
19695 { 3633, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3633 = V_FRACT_F64_e64
19696 { 3634, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3634 = V_FREXP_EXP_I16_F16_dpp
19697 { 3635, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3635 = V_FREXP_EXP_I16_F16_e32
19698 { 3636, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3636 = V_FREXP_EXP_I16_F16_e64
19699 { 3637, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #3637 = V_FREXP_EXP_I16_F16_sdwa
19700 { 3638, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3638 = V_FREXP_EXP_I32_F32_dpp
19701 { 3639, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3639 = V_FREXP_EXP_I32_F32_e32
19702 { 3640, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3640 = V_FREXP_EXP_I32_F32_e64
19703 { 3641, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #3641 = V_FREXP_EXP_I32_F32_sdwa
19704 { 3642, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #3642 = V_FREXP_EXP_I32_F64_e32
19705 { 3643, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #3643 = V_FREXP_EXP_I32_F64_e64
19706 { 3644, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3644 = V_FREXP_MANT_F16_dpp
19707 { 3645, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3645 = V_FREXP_MANT_F16_e32
19708 { 3646, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3646 = V_FREXP_MANT_F16_e64
19709 { 3647, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3647 = V_FREXP_MANT_F16_sdwa
19710 { 3648, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3648 = V_FREXP_MANT_F32_dpp
19711 { 3649, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3649 = V_FREXP_MANT_F32_e32
19712 { 3650, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3650 = V_FREXP_MANT_F32_e64
19713 { 3651, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3651 = V_FREXP_MANT_F32_sdwa
19714 { 3652, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3652 = V_FREXP_MANT_F64_e32
19715 { 3653, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3653 = V_FREXP_MANT_F64_e64
19716 { 3654, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo386, -1 ,nullptr }, // Inst #3654 = V_INTERP_MOV_F32
19717 { 3655, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo387, -1 ,nullptr }, // Inst #3655 = V_INTERP_MOV_F32_e64
19718 { 3656, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo388, -1 ,nullptr }, // Inst #3656 = V_INTERP_P1LL_F16
19719 { 3657, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList4, nullptr, OperandInfo389, -1 ,nullptr }, // Inst #3657 = V_INTERP_P1LV_F16
19720 { 3658, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #3658 = V_INTERP_P1_F32
19721 { 3659, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo390, -1 ,nullptr }, // Inst #3659 = V_INTERP_P1_F32_16bank
19722 { 3660, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #3660 = V_INTERP_P1_F32_e64
19723 { 3661, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b00000000402ULL, ImplicitList4, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #3661 = V_INTERP_P2_F16
19724 { 3662, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #3662 = V_INTERP_P2_F16_gfx9
19725 { 3663, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #3663 = V_INTERP_P2_F32
19726 { 3664, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList4, nullptr, OperandInfo391, -1 ,nullptr }, // Inst #3664 = V_INTERP_P2_F32_e64
19727 { 3665, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3665 = V_LDEXP_F16_dpp
19728 { 3666, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3666 = V_LDEXP_F16_e32
19729 { 3667, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3667 = V_LDEXP_F16_e64
19730 { 3668, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3668 = V_LDEXP_F16_sdwa
19731 { 3669, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3669 = V_LDEXP_F32_e32
19732 { 3670, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo395, -1 ,nullptr }, // Inst #3670 = V_LDEXP_F32_e64
19733 { 3671, 7, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo396, -1 ,nullptr }, // Inst #3671 = V_LDEXP_F64
19734 { 3672, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3672 = V_LERP_U8
19735 { 3673, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3673 = V_LOG_CLAMP_F32_dpp
19736 { 3674, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3674 = V_LOG_CLAMP_F32_e32
19737 { 3675, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3675 = V_LOG_CLAMP_F32_e64
19738 { 3676, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3676 = V_LOG_CLAMP_F32_sdwa
19739 { 3677, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3677 = V_LOG_F16_dpp
19740 { 3678, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3678 = V_LOG_F16_e32
19741 { 3679, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3679 = V_LOG_F16_e64
19742 { 3680, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3680 = V_LOG_F16_sdwa
19743 { 3681, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3681 = V_LOG_F32_dpp
19744 { 3682, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3682 = V_LOG_F32_e32
19745 { 3683, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3683 = V_LOG_F32_e64
19746 { 3684, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3684 = V_LOG_F32_sdwa
19747 { 3685, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3685 = V_LOG_LEGACY_F32_dpp
19748 { 3686, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3686 = V_LOG_LEGACY_F32_e32
19749 { 3687, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3687 = V_LOG_LEGACY_F32_e64
19750 { 3688, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3688 = V_LOG_LEGACY_F32_sdwa
19751 { 3689, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3689 = V_LSHLREV_B16_dpp
19752 { 3690, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3690 = V_LSHLREV_B16_e32
19753 { 3691, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3691 = V_LSHLREV_B16_e64
19754 { 3692, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3692 = V_LSHLREV_B16_sdwa
19755 { 3693, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3693 = V_LSHLREV_B32_dpp
19756 { 3694, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3694 = V_LSHLREV_B32_e32
19757 { 3695, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3695 = V_LSHLREV_B32_e64
19758 { 3696, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3696 = V_LSHLREV_B32_sdwa
19759 { 3697, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #3697 = V_LSHLREV_B64
19760 { 3698, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3698 = V_LSHL_ADD_U32
19761 { 3699, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3699 = V_LSHL_B32_dpp
19762 { 3700, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3700 = V_LSHL_B32_e32
19763 { 3701, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3701 = V_LSHL_B32_e64
19764 { 3702, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3702 = V_LSHL_B32_sdwa
19765 { 3703, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #3703 = V_LSHL_B64
19766 { 3704, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3704 = V_LSHL_OR_B32
19767 { 3705, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3705 = V_LSHRREV_B16_dpp
19768 { 3706, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3706 = V_LSHRREV_B16_e32
19769 { 3707, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3707 = V_LSHRREV_B16_e64
19770 { 3708, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3708 = V_LSHRREV_B16_sdwa
19771 { 3709, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3709 = V_LSHRREV_B32_dpp
19772 { 3710, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3710 = V_LSHRREV_B32_e32
19773 { 3711, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3711 = V_LSHRREV_B32_e64
19774 { 3712, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3712 = V_LSHRREV_B32_sdwa
19775 { 3713, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #3713 = V_LSHRREV_B64
19776 { 3714, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3714 = V_LSHR_B32_dpp
19777 { 3715, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3715 = V_LSHR_B32_e32
19778 { 3716, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3716 = V_LSHR_B32_e64
19779 { 3717, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3717 = V_LSHR_B32_sdwa
19780 { 3718, 3, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #3718 = V_LSHR_B64
19781 { 3719, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3719 = V_MAC_F16_dpp
19782 { 3720, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo376, -1 ,nullptr }, // Inst #3720 = V_MAC_F16_e32
19783 { 3721, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo377, -1 ,nullptr }, // Inst #3721 = V_MAC_F16_e64
19784 { 3722, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo378, -1 ,nullptr }, // Inst #3722 = V_MAC_F16_sdwa
19785 { 3723, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3723 = V_MAC_F32_dpp
19786 { 3724, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo379, -1 ,nullptr }, // Inst #3724 = V_MAC_F32_e32
19787 { 3725, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo380, -1 ,nullptr }, // Inst #3725 = V_MAC_F32_e64
19788 { 3726, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo381, -1 ,nullptr }, // Inst #3726 = V_MAC_F32_sdwa
19789 { 3727, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3727 = V_MAC_LEGACY_F32_dpp
19790 { 3728, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3728 = V_MAC_LEGACY_F32_e32
19791 { 3729, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3729 = V_MAC_LEGACY_F32_e64
19792 { 3730, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3730 = V_MAC_LEGACY_F32_sdwa
19793 { 3731, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo374, -1 ,nullptr }, // Inst #3731 = V_MADAK_F16
19794 { 3732, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo375, -1 ,nullptr }, // Inst #3732 = V_MADAK_F32
19795 { 3733, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #3733 = V_MADMK_F16
19796 { 3734, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo383, -1 ,nullptr }, // Inst #3734 = V_MADMK_F32
19797 { 3735, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10b00000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3735 = V_MAD_F16
19798 { 3736, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3736 = V_MAD_F16_gfx9
19799 { 3737, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3737 = V_MAD_F32
19800 { 3738, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo397, -1 ,nullptr }, // Inst #3738 = V_MAD_I16
19801 { 3739, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3739 = V_MAD_I16_gfx9
19802 { 3740, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3740 = V_MAD_I32_I16
19803 { 3741, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #3741 = V_MAD_I32_I24
19804 { 3742, 6, 2, 8, 18, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo401, -1 ,nullptr }, // Inst #3742 = V_MAD_I64_I32
19805 { 3743, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3743 = V_MAD_LEGACY_F32
19806 { 3744, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11200000001402ULL, ImplicitList2, nullptr, OperandInfo384, -1 ,nullptr }, // Inst #3744 = V_MAD_MIXHI_F16
19807 { 3745, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000001402ULL, ImplicitList2, nullptr, OperandInfo384, -1 ,nullptr }, // Inst #3745 = V_MAD_MIXLO_F16
19808 { 3746, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000001402ULL, ImplicitList2, nullptr, OperandInfo385, -1 ,nullptr }, // Inst #3746 = V_MAD_MIX_F32
19809 { 3747, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo397, -1 ,nullptr }, // Inst #3747 = V_MAD_U16
19810 { 3748, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3748 = V_MAD_U16_gfx9
19811 { 3749, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3749 = V_MAD_U32_U16
19812 { 3750, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #3750 = V_MAD_U32_U24
19813 { 3751, 6, 2, 8, 18, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo401, -1 ,nullptr }, // Inst #3751 = V_MAD_U64_U32
19814 { 3752, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3752 = V_MAX3_F16
19815 { 3753, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3753 = V_MAX3_F32
19816 { 3754, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3754 = V_MAX3_I16
19817 { 3755, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3755 = V_MAX3_I32
19818 { 3756, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3756 = V_MAX3_U16
19819 { 3757, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3757 = V_MAX3_U32
19820 { 3758, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3758 = V_MAX_F16_dpp
19821 { 3759, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3759 = V_MAX_F16_e32
19822 { 3760, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3760 = V_MAX_F16_e64
19823 { 3761, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3761 = V_MAX_F16_sdwa
19824 { 3762, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3762 = V_MAX_F32_dpp
19825 { 3763, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3763 = V_MAX_F32_e32
19826 { 3764, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3764 = V_MAX_F32_e64
19827 { 3765, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3765 = V_MAX_F32_sdwa
19828 { 3766, 7, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #3766 = V_MAX_F64
19829 { 3767, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3767 = V_MAX_I16_dpp
19830 { 3768, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3768 = V_MAX_I16_e32
19831 { 3769, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3769 = V_MAX_I16_e64
19832 { 3770, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3770 = V_MAX_I16_sdwa
19833 { 3771, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3771 = V_MAX_I32_dpp
19834 { 3772, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3772 = V_MAX_I32_e32
19835 { 3773, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3773 = V_MAX_I32_e64
19836 { 3774, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3774 = V_MAX_I32_sdwa
19837 { 3775, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3775 = V_MAX_LEGACY_F32_dpp
19838 { 3776, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3776 = V_MAX_LEGACY_F32_e32
19839 { 3777, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3777 = V_MAX_LEGACY_F32_e64
19840 { 3778, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3778 = V_MAX_LEGACY_F32_sdwa
19841 { 3779, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3779 = V_MAX_U16_dpp
19842 { 3780, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3780 = V_MAX_U16_e32
19843 { 3781, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3781 = V_MAX_U16_e64
19844 { 3782, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3782 = V_MAX_U16_sdwa
19845 { 3783, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3783 = V_MAX_U32_dpp
19846 { 3784, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3784 = V_MAX_U32_e32
19847 { 3785, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3785 = V_MAX_U32_e64
19848 { 3786, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3786 = V_MAX_U32_sdwa
19849 { 3787, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3787 = V_MBCNT_HI_U32_B32_e32
19850 { 3788, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3788 = V_MBCNT_HI_U32_B32_e64
19851 { 3789, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3789 = V_MBCNT_LO_U32_B32_e32
19852 { 3790, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3790 = V_MBCNT_LO_U32_B32_e64
19853 { 3791, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3791 = V_MED3_F16
19854 { 3792, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3792 = V_MED3_F32
19855 { 3793, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3793 = V_MED3_I16
19856 { 3794, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3794 = V_MED3_I32
19857 { 3795, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3795 = V_MED3_U16
19858 { 3796, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3796 = V_MED3_U32
19859 { 3797, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo402, -1 ,nullptr }, // Inst #3797 = V_MFMA_F32_16X16X16F16
19860 { 3798, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo403, -1 ,nullptr }, // Inst #3798 = V_MFMA_F32_16X16X1F32
19861 { 3799, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3799 = V_MFMA_F32_16X16X2BF16
19862 { 3800, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo405, -1 ,nullptr }, // Inst #3800 = V_MFMA_F32_16X16X4F16
19863 { 3801, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo406, -1 ,nullptr }, // Inst #3801 = V_MFMA_F32_16X16X4F32
19864 { 3802, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3802 = V_MFMA_F32_16X16X8BF16
19865 { 3803, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo408, -1 ,nullptr }, // Inst #3803 = V_MFMA_F32_32X32X1F32
19866 { 3804, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo409, -1 ,nullptr }, // Inst #3804 = V_MFMA_F32_32X32X2BF16
19867 { 3805, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo403, -1 ,nullptr }, // Inst #3805 = V_MFMA_F32_32X32X2F32
19868 { 3806, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3806 = V_MFMA_F32_32X32X4BF16
19869 { 3807, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo410, -1 ,nullptr }, // Inst #3807 = V_MFMA_F32_32X32X4F16
19870 { 3808, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo405, -1 ,nullptr }, // Inst #3808 = V_MFMA_F32_32X32X8F16
19871 { 3809, 7, 1, 8, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo406, -1 ,nullptr }, // Inst #3809 = V_MFMA_F32_4X4X1F32
19872 { 3810, 7, 1, 8, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3810 = V_MFMA_F32_4X4X2BF16
19873 { 3811, 7, 1, 8, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo402, -1 ,nullptr }, // Inst #3811 = V_MFMA_F32_4X4X4F16
19874 { 3812, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3812 = V_MFMA_I32_16X16X16I8
19875 { 3813, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3813 = V_MFMA_I32_16X16X4I8
19876 { 3814, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo409, -1 ,nullptr }, // Inst #3814 = V_MFMA_I32_32X32X4I8
19877 { 3815, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3815 = V_MFMA_I32_32X32X8I8
19878 { 3816, 7, 1, 8, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo407, -1 ,nullptr }, // Inst #3816 = V_MFMA_I32_4X4X4I8
19879 { 3817, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa40000000402ULL, ImplicitList2, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #3817 = V_MIN3_F16
19880 { 3818, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3818 = V_MIN3_F32
19881 { 3819, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3819 = V_MIN3_I16
19882 { 3820, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3820 = V_MIN3_I32
19883 { 3821, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3821 = V_MIN3_U16
19884 { 3822, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3822 = V_MIN3_U32
19885 { 3823, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3823 = V_MIN_F16_dpp
19886 { 3824, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3824 = V_MIN_F16_e32
19887 { 3825, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3825 = V_MIN_F16_e64
19888 { 3826, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3826 = V_MIN_F16_sdwa
19889 { 3827, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3827 = V_MIN_F32_dpp
19890 { 3828, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3828 = V_MIN_F32_e32
19891 { 3829, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3829 = V_MIN_F32_e64
19892 { 3830, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3830 = V_MIN_F32_sdwa
19893 { 3831, 7, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #3831 = V_MIN_F64
19894 { 3832, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3832 = V_MIN_I16_dpp
19895 { 3833, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3833 = V_MIN_I16_e32
19896 { 3834, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3834 = V_MIN_I16_e64
19897 { 3835, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3835 = V_MIN_I16_sdwa
19898 { 3836, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3836 = V_MIN_I32_dpp
19899 { 3837, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3837 = V_MIN_I32_e32
19900 { 3838, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3838 = V_MIN_I32_e64
19901 { 3839, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3839 = V_MIN_I32_sdwa
19902 { 3840, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3840 = V_MIN_LEGACY_F32_dpp
19903 { 3841, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3841 = V_MIN_LEGACY_F32_e32
19904 { 3842, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3842 = V_MIN_LEGACY_F32_e64
19905 { 3843, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3843 = V_MIN_LEGACY_F32_sdwa
19906 { 3844, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3844 = V_MIN_U16_dpp
19907 { 3845, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3845 = V_MIN_U16_e32
19908 { 3846, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3846 = V_MIN_U16_e64
19909 { 3847, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3847 = V_MIN_U16_sdwa
19910 { 3848, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3848 = V_MIN_U32_dpp
19911 { 3849, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3849 = V_MIN_U32_e32
19912 { 3850, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3850 = V_MIN_U32_e64
19913 { 3851, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3851 = V_MIN_U32_sdwa
19914 { 3852, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo411, -1 ,nullptr }, // Inst #3852 = V_MOVRELD_B32_V1
19915 { 3853, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo412, -1 ,nullptr }, // Inst #3853 = V_MOVRELD_B32_V16
19916 { 3854, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #3854 = V_MOVRELD_B32_V2
19917 { 3855, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #3855 = V_MOVRELD_B32_V4
19918 { 3856, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo415, -1 ,nullptr }, // Inst #3856 = V_MOVRELD_B32_V8
19919 { 3857, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3857 = V_MOVRELD_B32_e32
19920 { 3858, 2, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3858 = V_MOVRELD_B32_e64
19921 { 3859, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList10, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3859 = V_MOVRELSD_2_B32_e32
19922 { 3860, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList10, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3860 = V_MOVRELSD_2_B32_e64
19923 { 3861, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3861 = V_MOVRELSD_B32_e32
19924 { 3862, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3862 = V_MOVRELSD_B32_e64
19925 { 3863, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #3863 = V_MOVRELS_B32_e32
19926 { 3864, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList4, nullptr, OperandInfo416, -1 ,nullptr }, // Inst #3864 = V_MOVRELS_B32_e64
19927 { 3865, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3865 = V_MOV_B32_dpp
19928 { 3866, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3866 = V_MOV_B32_e32
19929 { 3867, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3867 = V_MOV_B32_e64
19930 { 3868, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3868 = V_MOV_B32_indirect
19931 { 3869, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3869 = V_MOV_B32_sdwa
19932 { 3870, 7, 1, 16, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo417, -1 ,nullptr }, // Inst #3870 = V_MOV_B64_DPP_PSEUDO
19933 { 3871, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, nullptr, OperandInfo418, -1 ,nullptr }, // Inst #3871 = V_MOV_B64_PSEUDO
19934 { 3872, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3872 = V_MOV_FED_B32_dpp
19935 { 3873, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3873 = V_MOV_FED_B32_e32
19936 { 3874, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3874 = V_MOV_FED_B32_e64
19937 { 3875, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3875 = V_MOV_FED_B32_sdwa
19938 { 3876, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #3876 = V_MQSAD_PK_U16_U8
19939 { 3877, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3877 = V_MQSAD_U32_U8
19940 { 3878, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #3878 = V_MSAD_U8
19941 { 3879, 9, 1, 8, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #3879 = V_MULLIT_F32
19942 { 3880, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3880 = V_MUL_F16_dpp
19943 { 3881, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3881 = V_MUL_F16_e32
19944 { 3882, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3882 = V_MUL_F16_e64
19945 { 3883, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3883 = V_MUL_F16_sdwa
19946 { 3884, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3884 = V_MUL_F32_dpp
19947 { 3885, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3885 = V_MUL_F32_e32
19948 { 3886, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3886 = V_MUL_F32_e64
19949 { 3887, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3887 = V_MUL_F32_sdwa
19950 { 3888, 7, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #3888 = V_MUL_F64
19951 { 3889, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3889 = V_MUL_HI_I32
19952 { 3890, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3890 = V_MUL_HI_I32_I24_dpp
19953 { 3891, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3891 = V_MUL_HI_I32_I24_e32
19954 { 3892, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3892 = V_MUL_HI_I32_I24_e64
19955 { 3893, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3893 = V_MUL_HI_I32_I24_sdwa
19956 { 3894, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3894 = V_MUL_HI_U32
19957 { 3895, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3895 = V_MUL_HI_U32_U24_dpp
19958 { 3896, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3896 = V_MUL_HI_U32_U24_e32
19959 { 3897, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3897 = V_MUL_HI_U32_U24_e64
19960 { 3898, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3898 = V_MUL_HI_U32_U24_sdwa
19961 { 3899, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3899 = V_MUL_I32_I24_dpp
19962 { 3900, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3900 = V_MUL_I32_I24_e32
19963 { 3901, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3901 = V_MUL_I32_I24_e64
19964 { 3902, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3902 = V_MUL_I32_I24_sdwa
19965 { 3903, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3903 = V_MUL_LEGACY_F32_dpp
19966 { 3904, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #3904 = V_MUL_LEGACY_F32_e32
19967 { 3905, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3905 = V_MUL_LEGACY_F32_e64
19968 { 3906, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3906 = V_MUL_LEGACY_F32_sdwa
19969 { 3907, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3907 = V_MUL_LO_I32
19970 { 3908, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3908 = V_MUL_LO_U16_dpp
19971 { 3909, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #3909 = V_MUL_LO_U16_e32
19972 { 3910, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #3910 = V_MUL_LO_U16_e64
19973 { 3911, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #3911 = V_MUL_LO_U16_sdwa
19974 { 3912, 3, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3912 = V_MUL_LO_U32
19975 { 3913, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3913 = V_MUL_U32_U24_dpp
19976 { 3914, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3914 = V_MUL_U32_U24_e32
19977 { 3915, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3915 = V_MUL_U32_U24_e64
19978 { 3916, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3916 = V_MUL_U32_U24_sdwa
19979 { 3917, 0, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20000000082ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #3917 = V_NOP_e32
19980 { 3918, 0, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20000000402ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #3918 = V_NOP_e64
19981 { 3919, 0, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20000004002ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #3919 = V_NOP_sdwa
19982 { 3920, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3920 = V_NOT_B32_dpp
19983 { 3921, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3921 = V_NOT_B32_e32
19984 { 3922, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3922 = V_NOT_B32_e64
19985 { 3923, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3923 = V_NOT_B32_sdwa
19986 { 3924, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3924 = V_OR3_B32
19987 { 3925, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #3925 = V_OR_B32_dpp
19988 { 3926, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #3926 = V_OR_B32_e32
19989 { 3927, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #3927 = V_OR_B32_e64
19990 { 3928, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #3928 = V_OR_B32_sdwa
19991 { 3929, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3929 = V_PACK_B32_F16
19992 { 3930, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40000000402ULL, ImplicitList2, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3930 = V_PERMLANE16_B32
19993 { 3931, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40000000402ULL, ImplicitList2, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3931 = V_PERMLANEX16_B32
19994 { 3932, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #3932 = V_PERM_B32
19995 { 3933, 0, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #3933 = V_PIPEFLUSH_e32
19996 { 3934, 0, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #3934 = V_PIPEFLUSH_e64
19997 { 3935, 0, 0, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #3935 = V_PIPEFLUSH_sdwa
19998 { 3936, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x13a00000001402ULL, ImplicitList2, nullptr, OperandInfo422, -1 ,nullptr }, // Inst #3936 = V_PK_ADD_F16
19999 { 3937, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3937 = V_PK_ADD_I16
20000 { 3938, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3938 = V_PK_ADD_U16
20001 { 3939, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3939 = V_PK_ASHRREV_I16
20002 { 3940, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #3940 = V_PK_FMAC_F16_dpp
20003 { 3941, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo424, -1 ,nullptr }, // Inst #3941 = V_PK_FMAC_F16_e32
20004 { 3942, 6, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3a00000000402ULL, ImplicitList2, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #3942 = V_PK_FMAC_F16_e64
20005 { 3943, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3943 = V_PK_FMAC_F16_sdwa
20006 { 3944, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x13a00000001402ULL, ImplicitList2, nullptr, OperandInfo426, -1 ,nullptr }, // Inst #3944 = V_PK_FMA_F16
20007 { 3945, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3945 = V_PK_LSHLREV_B16
20008 { 3946, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3946 = V_PK_LSHRREV_B16
20009 { 3947, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #3947 = V_PK_MAD_I16
20010 { 3948, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #3948 = V_PK_MAD_U16
20011 { 3949, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3a00000001402ULL, ImplicitList2, nullptr, OperandInfo422, -1 ,nullptr }, // Inst #3949 = V_PK_MAX_F16
20012 { 3950, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3950 = V_PK_MAX_I16
20013 { 3951, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3951 = V_PK_MAX_U16
20014 { 3952, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3a00000001402ULL, ImplicitList2, nullptr, OperandInfo422, -1 ,nullptr }, // Inst #3952 = V_PK_MIN_F16
20015 { 3953, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3953 = V_PK_MIN_I16
20016 { 3954, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3954 = V_PK_MIN_U16
20017 { 3955, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x13a00000001402ULL, ImplicitList2, nullptr, OperandInfo422, -1 ,nullptr }, // Inst #3955 = V_PK_MUL_F16
20018 { 3956, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3956 = V_PK_MUL_LO_U16
20019 { 3957, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3957 = V_PK_SUB_I16
20020 { 3958, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3958 = V_PK_SUB_U16
20021 { 3959, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #3959 = V_QSAD_PK_U16_U8
20022 { 3960, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3960 = V_RCP_CLAMP_F32_dpp
20023 { 3961, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3961 = V_RCP_CLAMP_F32_e32
20024 { 3962, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3962 = V_RCP_CLAMP_F32_e64
20025 { 3963, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3963 = V_RCP_CLAMP_F32_sdwa
20026 { 3964, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3964 = V_RCP_CLAMP_F64_e32
20027 { 3965, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3965 = V_RCP_CLAMP_F64_e64
20028 { 3966, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3966 = V_RCP_F16_dpp
20029 { 3967, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3967 = V_RCP_F16_e32
20030 { 3968, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3968 = V_RCP_F16_e64
20031 { 3969, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3969 = V_RCP_F16_sdwa
20032 { 3970, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3970 = V_RCP_F32_dpp
20033 { 3971, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3971 = V_RCP_F32_e32
20034 { 3972, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3972 = V_RCP_F32_e64
20035 { 3973, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3973 = V_RCP_F32_sdwa
20036 { 3974, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3974 = V_RCP_F64_e32
20037 { 3975, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3975 = V_RCP_F64_e64
20038 { 3976, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3976 = V_RCP_IFLAG_F32_dpp
20039 { 3977, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3977 = V_RCP_IFLAG_F32_e32
20040 { 3978, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3978 = V_RCP_IFLAG_F32_e64
20041 { 3979, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3979 = V_RCP_IFLAG_F32_sdwa
20042 { 3980, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3980 = V_RCP_LEGACY_F32_dpp
20043 { 3981, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3981 = V_RCP_LEGACY_F32_e32
20044 { 3982, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3982 = V_RCP_LEGACY_F32_e64
20045 { 3983, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3983 = V_RCP_LEGACY_F32_sdwa
20046 { 3984, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x102ULL, nullptr, nullptr, OperandInfo428, -1 ,nullptr }, // Inst #3984 = V_READLANE_B32
20047 { 3985, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3985 = V_RNDNE_F16_dpp
20048 { 3986, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #3986 = V_RNDNE_F16_e32
20049 { 3987, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #3987 = V_RNDNE_F16_e64
20050 { 3988, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #3988 = V_RNDNE_F16_sdwa
20051 { 3989, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3989 = V_RNDNE_F32_dpp
20052 { 3990, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3990 = V_RNDNE_F32_e32
20053 { 3991, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3991 = V_RNDNE_F32_e64
20054 { 3992, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3992 = V_RNDNE_F32_sdwa
20055 { 3993, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3993 = V_RNDNE_F64_e32
20056 { 3994, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3994 = V_RNDNE_F64_e64
20057 { 3995, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #3995 = V_RSQ_CLAMP_F32_dpp
20058 { 3996, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #3996 = V_RSQ_CLAMP_F32_e32
20059 { 3997, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #3997 = V_RSQ_CLAMP_F32_e64
20060 { 3998, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #3998 = V_RSQ_CLAMP_F32_sdwa
20061 { 3999, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #3999 = V_RSQ_CLAMP_F64_e32
20062 { 4000, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4000 = V_RSQ_CLAMP_F64_e64
20063 { 4001, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4001 = V_RSQ_F16_dpp
20064 { 4002, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4002 = V_RSQ_F16_e32
20065 { 4003, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4003 = V_RSQ_F16_e64
20066 { 4004, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #4004 = V_RSQ_F16_sdwa
20067 { 4005, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4005 = V_RSQ_F32_dpp
20068 { 4006, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4006 = V_RSQ_F32_e32
20069 { 4007, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4007 = V_RSQ_F32_e64
20070 { 4008, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #4008 = V_RSQ_F32_sdwa
20071 { 4009, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #4009 = V_RSQ_F64_e32
20072 { 4010, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4010 = V_RSQ_F64_e64
20073 { 4011, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4011 = V_RSQ_LEGACY_F32_dpp
20074 { 4012, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4012 = V_RSQ_LEGACY_F32_e32
20075 { 4013, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4013 = V_RSQ_LEGACY_F32_e64
20076 { 4014, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #4014 = V_RSQ_LEGACY_F32_sdwa
20077 { 4015, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4015 = V_SAD_HI_U8
20078 { 4016, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4016 = V_SAD_U16
20079 { 4017, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4017 = V_SAD_U32
20080 { 4018, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4018 = V_SAD_U8
20081 { 4019, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #4019 = V_SAT_PK_U8_I16_dpp
20082 { 4020, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4020 = V_SAT_PK_U8_I16_e32
20083 { 4021, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4021 = V_SAT_PK_U8_I16_e64
20084 { 4022, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #4022 = V_SAT_PK_U8_I16_sdwa
20085 { 4023, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #4023 = V_SCREEN_PARTITION_4SE_B32_dpp
20086 { 4024, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4024 = V_SCREEN_PARTITION_4SE_B32_e32
20087 { 4025, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #4025 = V_SCREEN_PARTITION_4SE_B32_e64
20088 { 4026, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #4026 = V_SCREEN_PARTITION_4SE_B32_sdwa
20089 { 4027, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #4027 = V_SET_INACTIVE_B32
20090 { 4028, 3, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2ULL, ImplicitList2, nullptr, OperandInfo430, -1 ,nullptr }, // Inst #4028 = V_SET_INACTIVE_B64
20091 { 4029, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4029 = V_SIN_F16_dpp
20092 { 4030, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4030 = V_SIN_F16_e32
20093 { 4031, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4031 = V_SIN_F16_e64
20094 { 4032, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #4032 = V_SIN_F16_sdwa
20095 { 4033, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4033 = V_SIN_F32_dpp
20096 { 4034, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4034 = V_SIN_F32_e32
20097 { 4035, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4035 = V_SIN_F32_e64
20098 { 4036, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #4036 = V_SIN_F32_sdwa
20099 { 4037, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4037 = V_SQRT_F16_dpp
20100 { 4038, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4038 = V_SQRT_F16_e32
20101 { 4039, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4039 = V_SQRT_F16_e64
20102 { 4040, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #4040 = V_SQRT_F16_sdwa
20103 { 4041, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4041 = V_SQRT_F32_dpp
20104 { 4042, 2, 1, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4042 = V_SQRT_F32_e32
20105 { 4043, 5, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4043 = V_SQRT_F32_e64
20106 { 4044, 8, 1, 8, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #4044 = V_SQRT_F32_sdwa
20107 { 4045, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #4045 = V_SQRT_F64_e32
20108 { 4046, 5, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4046 = V_SQRT_F64_e64
20109 { 4047, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4047 = V_SUBBREV_U32_dpp
20110 { 4048, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4048 = V_SUBBREV_U32_e32
20111 { 4049, 6, 2, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #4049 = V_SUBBREV_U32_e64
20112 { 4050, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4050 = V_SUBBREV_U32_sdwa
20113 { 4051, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList13, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4051 = V_SUBB_U32_dpp
20114 { 4052, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList13, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4052 = V_SUBB_U32_e32
20115 { 4053, 6, 2, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #4053 = V_SUBB_U32_e64
20116 { 4054, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList13, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4054 = V_SUBB_U32_sdwa
20117 { 4055, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4055 = V_SUBREV_F16_dpp
20118 { 4056, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #4056 = V_SUBREV_F16_e32
20119 { 4057, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #4057 = V_SUBREV_F16_e64
20120 { 4058, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #4058 = V_SUBREV_F16_sdwa
20121 { 4059, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4059 = V_SUBREV_F32_dpp
20122 { 4060, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #4060 = V_SUBREV_F32_e32
20123 { 4061, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #4061 = V_SUBREV_F32_e64
20124 { 4062, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #4062 = V_SUBREV_F32_sdwa
20125 { 4063, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4063 = V_SUBREV_I32_dpp
20126 { 4064, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4064 = V_SUBREV_I32_e32
20127 { 4065, 5, 2, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #4065 = V_SUBREV_I32_e64
20128 { 4066, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4066 = V_SUBREV_I32_sdwa
20129 { 4067, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4067 = V_SUBREV_U16_dpp
20130 { 4068, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #4068 = V_SUBREV_U16_e32
20131 { 4069, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #4069 = V_SUBREV_U16_e64
20132 { 4070, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #4070 = V_SUBREV_U16_sdwa
20133 { 4071, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4071 = V_SUBREV_U32_dpp
20134 { 4072, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4072 = V_SUBREV_U32_e32
20135 { 4073, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #4073 = V_SUBREV_U32_e64
20136 { 4074, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4074 = V_SUBREV_U32_sdwa
20137 { 4075, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x10000000008002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4075 = V_SUB_F16_dpp
20138 { 4076, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000000102ULL, ImplicitList2, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #4076 = V_SUB_F16_e32
20139 { 4077, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10a00000000402ULL, ImplicitList2, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #4077 = V_SUB_F16_e64
20140 { 4078, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10000000004002ULL, ImplicitList2, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #4078 = V_SUB_F16_sdwa
20141 { 4079, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #4079 = V_SUB_F32_dpp
20142 { 4080, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #4080 = V_SUB_F32_e32
20143 { 4081, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #4081 = V_SUB_F32_e64
20144 { 4082, 11, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #4082 = V_SUB_F32_sdwa
20145 { 4083, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc40000000402ULL, ImplicitList2, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #4083 = V_SUB_I16
20146 { 4084, 8, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, ImplicitList14, OperandInfo277, -1 ,nullptr }, // Inst #4084 = V_SUB_I32_dpp
20147 { 4085, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, ImplicitList14, OperandInfo278, -1 ,nullptr }, // Inst #4085 = V_SUB_I32_e32
20148 { 4086, 5, 2, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #4086 = V_SUB_I32_e64
20149 { 4087, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #4087 = V_SUB_I32_gfx9
20150 { 4088, 10, 1, 8, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, ImplicitList14, OperandInfo280, -1 ,nullptr }, // Inst #4088 = V_SUB_I32_sdwa
20151 { 4089, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4089 = V_SUB_U16_dpp
20152 { 4090, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #4090 = V_SUB_U16_e32
20153 { 4091, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #4091 = V_SUB_U16_e64
20154 { 4092, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #4092 = V_SUB_U16_sdwa
20155 { 4093, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x100000008002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4093 = V_SUB_U32_dpp
20156 { 4094, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000000102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4094 = V_SUB_U32_e32
20157 { 4095, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xd00000000402ULL, ImplicitList2, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #4095 = V_SUB_U32_e64
20158 { 4096, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x100000004002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4096 = V_SUB_U32_sdwa
20159 { 4097, 4, 2, 4, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList10, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #4097 = V_SWAPREL_B32
20160 { 4098, 4, 2, 4, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo431, -1 ,nullptr }, // Inst #4098 = V_SWAP_B32
20161 { 4099, 7, 1, 8, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo396, -1 ,nullptr }, // Inst #4099 = V_TRIG_PREOP_F64
20162 { 4100, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4100 = V_TRUNC_F16_dpp
20163 { 4101, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #4101 = V_TRUNC_F16_e32
20164 { 4102, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #4102 = V_TRUNC_F16_e64
20165 { 4103, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #4103 = V_TRUNC_F16_sdwa
20166 { 4104, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #4104 = V_TRUNC_F32_dpp
20167 { 4105, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #4105 = V_TRUNC_F32_e32
20168 { 4106, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #4106 = V_TRUNC_F32_e64
20169 { 4107, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #4107 = V_TRUNC_F32_sdwa
20170 { 4108, 2, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #4108 = V_TRUNC_F64_e32
20171 { 4109, 5, 1, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #4109 = V_TRUNC_F64_e64
20172 { 4110, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x102ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr }, // Inst #4110 = V_WRITELANE_B32
20173 { 4111, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #4111 = V_XAD_U32
20174 { 4112, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4112 = V_XNOR_B32_dpp
20175 { 4113, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4113 = V_XNOR_B32_e32
20176 { 4114, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #4114 = V_XNOR_B32_e64
20177 { 4115, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4115 = V_XNOR_B32_sdwa
20178 { 4116, 4, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #4116 = V_XOR3_B32
20179 { 4117, 8, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #4117 = V_XOR_B32_dpp
20180 { 4118, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #4118 = V_XOR_B32_e32
20181 { 4119, 3, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #4119 = V_XOR_B32_e64
20182 { 4120, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #4120 = V_XOR_B32_sdwa
20183 { 4121, 0, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x10000000001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #4121 = WAVE_BARRIER
20184 { 4122, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #4122 = WQM
20185 { 4123, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, nullptr, OperandInfo433, -1 ,nullptr }, // Inst #4123 = WWM
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 638 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
639 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
640 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
641 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
642 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
643 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
644 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
645 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
646 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
647 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
648 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
649 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
650 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
651 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
652 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
653 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
654 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
655 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
656 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
657 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
658 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
659 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
660 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
661 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
662 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
663 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
664 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
665 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
666 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
667 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
668 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
669 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
670 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
671 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
672 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
673 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
674 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
675 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
676 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
677 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
678 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
679 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
680 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
681 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
682 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
683 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
684 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
685 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
686 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
687 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
688 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
689 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
690 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
691 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
692 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
693 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
694 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
695 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
696 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
697 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
698 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
699 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
700 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
701 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
702 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
703 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
704 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
705 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
706 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
707 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
708 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
709 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
710 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
711 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
712 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
713 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
714 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
715 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
716 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
717 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
718 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
719 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
720 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
721 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
722 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
723 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
724 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
725 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
726 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
727 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
728 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
729 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
730 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
731 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
732 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
733 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
734 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
735 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
736 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
737 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
738 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
739 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
740 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
741 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
742 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
743 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
744 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
745 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
746 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
747 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
748 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
749 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
750 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
751 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
752 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
753 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
754 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
755 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
756 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
757 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
758 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
759 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
760 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
761 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
762 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
763 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
764 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
765 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
766 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
767 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
768 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
769 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
770 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
771 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
772 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
773 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
774 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
775 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
776 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
777 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
778 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
779 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
780 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
781 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
782 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
783 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
784 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
785 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
786 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
787 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
788 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
789 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
790 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
791 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
792 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
793 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
794 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
795 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
796 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
797 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
798 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
799 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
800 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
801 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
802 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
803 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
804 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
805 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
806 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
807 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
808 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
809 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
810 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
811 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
812 { 174, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #174 = BRANCH
813 { 175, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #175 = BRANCH_COND_f32
814 { 176, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BRANCH_COND_i32
815 { 177, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #177 = BREAK
816 { 178, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = BREAKC_f32
817 { 179, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #179 = BREAKC_i32
818 { 180, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #180 = BREAK_LOGICALNZ_f32
819 { 181, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #181 = BREAK_LOGICALNZ_i32
820 { 182, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #182 = BREAK_LOGICALZ_f32
821 { 183, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #183 = BREAK_LOGICALZ_i32
822 { 184, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #184 = CONST_COPY
823 { 185, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #185 = CONTINUE
824 { 186, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #186 = CONTINUEC_f32
825 { 187, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #187 = CONTINUEC_i32
826 { 188, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #188 = CONTINUE_LOGICALNZ_f32
827 { 189, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #189 = CONTINUE_LOGICALNZ_i32
828 { 190, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #190 = CONTINUE_LOGICALZ_f32
829 { 191, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #191 = CONTINUE_LOGICALZ_i32
830 { 192, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #192 = CUBE_eg_pseudo
831 { 193, 2, 1, 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #193 = CUBE_r600_pseudo
832 { 194, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #194 = DEFAULT
833 { 195, 71, 1, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #195 = DOT_4
834 { 196, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #196 = DUMMY_CHAIN
835 { 197, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #197 = ELSE
836 { 198, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #198 = END
837 { 199, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #199 = ENDFUNC
838 { 200, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #200 = ENDIF
839 { 201, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #201 = ENDLOOP
840 { 202, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #202 = ENDMAIN
841 { 203, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #203 = ENDSWITCH
842 { 204, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #204 = FABS_R600
843 { 205, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #205 = FNEG_R600
844 { 206, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #206 = FUNC
845 { 207, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #207 = IFC_f32
846 { 208, 2, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #208 = IFC_i32
847 { 209, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #209 = IF_LOGICALNZ_f32
848 { 210, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #210 = IF_LOGICALNZ_i32
849 { 211, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #211 = IF_LOGICALZ_f32
850 { 212, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #212 = IF_LOGICALZ_i32
851 { 213, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #213 = IF_PREDICATE_SET
852 { 214, 1, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #214 = JUMP
853 { 215, 2, 0, 0, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #215 = JUMP_COND
854 { 216, 1, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #216 = MASK_WRITE
855 { 217, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #217 = MOV_IMM_F32
856 { 218, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #218 = MOV_IMM_GLOBAL_ADDR
857 { 219, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #219 = MOV_IMM_I32
858 { 220, 4, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #220 = PRED_X
859 { 221, 3, 1, 0, 3, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #221 = R600_EXTRACT_ELT_V2
860 { 222, 3, 1, 0, 3, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #222 = R600_EXTRACT_ELT_V4
861 { 223, 4, 1, 0, 3, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #223 = R600_INSERT_ELT_V2
862 { 224, 4, 1, 0, 3, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #224 = R600_INSERT_ELT_V4
863 { 225, 4, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #225 = R600_RegisterLoad
864 { 226, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #226 = R600_RegisterStore
865 { 227, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #227 = RETDYN
866 { 228, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #228 = RETURN
867 { 229, 7, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #229 = TXD
868 { 230, 7, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #230 = TXD_SHADOW
869 { 231, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #231 = WHILELOOP
gen/lib/Target/ARC/ARCGenInstrInfo.inc 643 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
644 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
645 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
646 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
647 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
648 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
649 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
650 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
651 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
652 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
653 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
654 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
655 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
656 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
657 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
658 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
659 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
660 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
661 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
662 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
663 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
664 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
665 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
666 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
667 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
668 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
669 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
670 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
671 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
672 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
673 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
674 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
675 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
676 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
677 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
678 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
679 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
680 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
681 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
682 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
683 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
684 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
685 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
686 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
687 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
688 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
689 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
690 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
691 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
692 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
693 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
694 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
695 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
696 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
697 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
698 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
699 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
700 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
701 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
702 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
703 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
704 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
705 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
706 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
707 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
708 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
709 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
710 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
711 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
712 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
713 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
714 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
715 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
716 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
717 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
718 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
719 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
720 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
721 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
722 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
723 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
724 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
725 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
726 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
727 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
728 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
729 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
730 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
731 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
732 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
733 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
734 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
735 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
736 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
737 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
738 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
739 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
740 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
741 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
742 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
743 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
744 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
745 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
746 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
747 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
748 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
749 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
750 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
751 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
752 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
753 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
754 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
755 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
756 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
757 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
758 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
759 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
760 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
761 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
762 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
763 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
764 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
765 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
766 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
767 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
768 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
769 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
770 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
771 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
772 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
773 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
774 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
775 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
776 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
777 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
778 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
779 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
780 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
781 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
782 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
783 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
784 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
785 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
786 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
787 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
788 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
789 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
790 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
791 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
792 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
793 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
794 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
795 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
796 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
797 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
798 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
799 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
800 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
801 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
802 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
803 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
804 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
805 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
806 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
807 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
808 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
809 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
810 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
811 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
812 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
813 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
814 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
815 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
816 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
817 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
818 { 175, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
819 { 176, 4, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BRcc_rr_p
820 { 177, 4, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #177 = BRcc_ru6_p
821 { 178, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = GETFI
822 { 179, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = STB_FAR
823 { 180, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = STH_FAR
824 { 181, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #181 = ST_FAR
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5833 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
5834 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
5835 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
5836 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
5837 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
5838 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
5839 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
5840 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
5841 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
5842 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
5843 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
5844 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
5845 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
5846 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
5847 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
5848 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
5849 { 16, 2, 1, 0, 677, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
5850 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
5851 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
5852 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
5853 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
5854 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
5855 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
5856 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
5857 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
5858 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
5859 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
5860 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
5861 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
5862 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
5863 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
5864 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
5865 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
5866 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
5867 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
5868 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
5869 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
5870 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
5871 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
5872 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
5873 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
5874 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
5875 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
5876 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
5877 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
5878 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
5879 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
5880 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
5881 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
5882 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
5883 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
5884 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
5885 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
5886 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
5887 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
5888 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
5889 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
5890 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
5891 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
5892 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
5893 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
5894 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
5895 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
5896 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
5897 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
5898 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
5899 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
5900 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
5901 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
5902 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
5903 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
5904 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
5905 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
5906 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
5907 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
5908 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
5909 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
5910 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
5911 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
5912 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
5913 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
5914 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
5915 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
5916 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
5917 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
5918 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
5919 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
5920 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
5921 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
5922 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
5923 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
5924 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
5925 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
5926 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
5927 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
5928 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
5929 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
5930 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
5931 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
5932 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
5933 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
5934 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
5935 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
5936 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
5937 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
5938 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
5939 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
5940 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
5941 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
5942 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
5943 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
5944 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
5945 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
5946 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
5947 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
5948 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
5949 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
5950 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
5951 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
5952 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
5953 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
5954 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
5955 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
5956 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
5957 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
5958 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
5959 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
5960 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
5961 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
5962 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
5963 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
5964 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
5965 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
5966 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
5967 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
5968 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
5969 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
5970 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
5971 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
5972 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
5973 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
5974 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
5975 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
5976 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
5977 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
5978 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
5979 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
5980 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
5981 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
5982 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
5983 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
5984 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
5985 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
5986 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
5987 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
5988 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
5989 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
5990 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
5991 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
5992 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
5993 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
5994 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
5995 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
5996 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
5997 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
5998 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
5999 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
6000 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
6001 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
6002 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
6003 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
6004 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
6005 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
6006 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
6007 { 174, 2, 1, 8, 676, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ABS
6008 { 175, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #175 = ADDSri
6009 { 176, 5, 1, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #176 = ADDSrr
6010 { 177, 6, 1, 4, 700, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #177 = ADDSrsi
6011 { 178, 7, 1, 4, 705, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #178 = ADDSrsr
6012 { 179, 4, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #179 = ADJCALLSTACKDOWN
6013 { 180, 4, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #180 = ADJCALLSTACKUP
6014 { 181, 6, 0, 0, 711, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #181 = ASRi
6015 { 182, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #182 = ASRr
6016 { 183, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #183 = B
6017 { 184, 4, 0, 0, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #184 = BCCZi64
6018 { 185, 6, 0, 0, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #185 = BCCi64
6019 { 186, 2, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo47, -1 ,nullptr }, // Inst #186 = BL_PUSHLR
6020 { 187, 1, 0, 8, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #187 = BMOVPCB_CALL
6021 { 188, 1, 0, 8, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #188 = BMOVPCRX_CALL
6022 { 189, 3, 0, 4, 859, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #189 = BR_JTadd
6023 { 190, 3, 0, 4, 862, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #190 = BR_JTm_i12
6024 { 191, 4, 0, 4, 862, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #191 = BR_JTm_rs
6025 { 192, 2, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #192 = BR_JTr
6026 { 193, 1, 0, 8, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #193 = BX_CALL
6027 { 194, 5, 2, 0, 1029, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #194 = CMP_SWAP_16
6028 { 195, 5, 2, 0, 1029, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #195 = CMP_SWAP_32
6029 { 196, 5, 2, 0, 1029, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #196 = CMP_SWAP_64
6030 { 197, 5, 2, 0, 1029, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #197 = CMP_SWAP_8
6031 { 198, 3, 0, 0, 841, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #198 = CONSTPOOL_ENTRY
6032 { 199, 4, 0, 0, 841, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr }, // Inst #199 = COPY_STRUCT_BYVAL_I32
6033 { 200, 1, 0, 0, 841, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #200 = CompilerBarrier
6034 { 201, 2, 0, 0, 454, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,&getITDeprecationInfo }, // Inst #201 = ITasm
6035 { 202, 0, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #202 = Int_eh_sjlj_dispatchsetup
6036 { 203, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo36, -1 ,nullptr }, // Inst #203 = Int_eh_sjlj_longjmp
6037 { 204, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo36, -1 ,nullptr }, // Inst #204 = Int_eh_sjlj_setjmp
6038 { 205, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo36, -1 ,nullptr }, // Inst #205 = Int_eh_sjlj_setjmp_nofp
6039 { 206, 0, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #206 = Int_eh_sjlj_setup_dispatch
6040 { 207, 3, 0, 0, 1030, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #207 = JUMPTABLE_ADDRS
6041 { 208, 3, 0, 0, 1030, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #208 = JUMPTABLE_INSTS
6042 { 209, 3, 0, 0, 1030, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #209 = JUMPTABLE_TBB
6043 { 210, 3, 0, 0, 1030, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #210 = JUMPTABLE_TBH
6044 { 211, 5, 1, 4, 419, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #211 = LDMIA_RET
6045 { 212, 4, 1, 0, 685, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #212 = LDRBT_POST
6046 { 213, 4, 1, 0, 899, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #213 = LDRConstPool
6047 { 214, 2, 1, 0, 450, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #214 = LDRLIT_ga_abs
6048 { 215, 2, 1, 0, 451, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #215 = LDRLIT_ga_pcrel
6049 { 216, 2, 1, 0, 452, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #216 = LDRLIT_ga_pcrel_ldr
6050 { 217, 4, 1, 0, 927, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #217 = LDRT_POST
6051 { 218, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #218 = LEApcrel
6052 { 219, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #219 = LEApcrelJT
6053 { 220, 6, 0, 0, 873, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #220 = LSLi
6054 { 221, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #221 = LSLr
6055 { 222, 6, 0, 0, 873, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #222 = LSRi
6056 { 223, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #223 = LSRr
6057 { 224, 5, 2, 0, 1031, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #224 = MEMCPY
6058 { 225, 7, 1, 4, 337, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #225 = MLAv5
6059 { 226, 5, 1, 4, 866, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #226 = MOVCCi
6060 { 227, 5, 1, 4, 864, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #227 = MOVCCi16
6061 { 228, 5, 1, 8, 330, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #228 = MOVCCi32imm
6062 { 229, 5, 1, 4, 868, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #229 = MOVCCr
6063 { 230, 6, 1, 4, 871, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #230 = MOVCCsi
6064 { 231, 7, 1, 4, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #231 = MOVCCsr
6065 { 232, 1, 0, 4, 880, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #232 = MOVPCRX
6066 { 233, 4, 1, 0, 689, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #233 = MOVTi16_ga_pcrel
6067 { 234, 2, 1, 0, 332, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #234 = MOV_ga_pcrel
6068 { 235, 2, 1, 0, 333, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #235 = MOV_ga_pcrel_ldr
6069 { 236, 3, 1, 0, 864, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #236 = MOVi16_ga_pcrel
6070 { 237, 2, 1, 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #237 = MOVi32imm
6071 { 238, 2, 1, 0, 325, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #238 = MOVsra_flag
6072 { 239, 2, 1, 0, 325, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #239 = MOVsrl_flag
6073 { 240, 6, 1, 4, 336, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #240 = MULv5
6074 { 241, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #241 = MVE_VANDIZ0v4i32
6075 { 242, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #242 = MVE_VANDIZ0v8i16
6076 { 243, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #243 = MVE_VANDIZ16v4i32
6077 { 244, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #244 = MVE_VANDIZ24v4i32
6078 { 245, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #245 = MVE_VANDIZ8v4i32
6079 { 246, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #246 = MVE_VANDIZ8v8i16
6080 { 247, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #247 = MVE_VORNIZ0v4i32
6081 { 248, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #248 = MVE_VORNIZ0v8i16
6082 { 249, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #249 = MVE_VORNIZ16v4i32
6083 { 250, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #250 = MVE_VORNIZ24v4i32
6084 { 251, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #251 = MVE_VORNIZ8v4i32
6085 { 252, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #252 = MVE_VORNIZ8v8i16
6086 { 253, 5, 1, 4, 866, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #253 = MVNCCi
6087 { 254, 5, 1, 4, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #254 = PICADD
6088 { 255, 5, 1, 4, 347, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #255 = PICLDR
6089 { 256, 5, 1, 4, 900, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #256 = PICLDRB
6090 { 257, 5, 1, 4, 900, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #257 = PICLDRH
6091 { 258, 5, 1, 4, 901, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #258 = PICLDRSB
6092 { 259, 5, 1, 4, 901, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #259 = PICLDRSH
6093 { 260, 5, 0, 4, 422, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #260 = PICSTR
6094 { 261, 5, 0, 4, 931, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #261 = PICSTRB
6095 { 262, 5, 0, 4, 931, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #262 = PICSTRH
6096 { 263, 6, 0, 0, 711, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #263 = RORi
6097 { 264, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #264 = RORr
6098 { 265, 2, 1, 0, 719, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #265 = RRX
6099 { 266, 5, 0, 0, 717, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #266 = RRXi
6100 { 267, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #267 = RSBSri
6101 { 268, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #268 = RSBSrsi
6102 { 269, 7, 1, 4, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #269 = RSBSrsr
6103 { 270, 9, 2, 4, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #270 = SMLALv5
6104 { 271, 7, 2, 4, 338, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #271 = SMULLv5
6105 { 272, 3, 1, 0, 841, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #272 = SPACE
6106 { 273, 4, 0, 0, 437, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #273 = STRBT_POST
6107 { 274, 7, 1, 4, 935, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #274 = STRBi_preidx
6108 { 275, 7, 1, 4, 935, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #275 = STRBr_preidx
6109 { 276, 7, 1, 4, 935, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #276 = STRH_preidx
6110 { 277, 4, 0, 0, 437, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #277 = STRT_POST
6111 { 278, 7, 1, 4, 935, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #278 = STRi_preidx
6112 { 279, 7, 1, 4, 935, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #279 = STRr_preidx
6113 { 280, 3, 0, 4, 850, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #280 = SUBS_PC_LR
6114 { 281, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #281 = SUBSri
6115 { 282, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #282 = SUBSrr
6116 { 283, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #283 = SUBSrsi
6117 { 284, 7, 1, 4, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #284 = SUBSrsr
6118 { 285, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #285 = TAILJMPd
6119 { 286, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #286 = TAILJMPr
6120 { 287, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #287 = TAILJMPr4
6121 { 288, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #288 = TCRETURNdi
6122 { 289, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #289 = TCRETURNri
6123 { 290, 0, 0, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #290 = TPsoft
6124 { 291, 9, 2, 4, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #291 = UMLALv5
6125 { 292, 7, 2, 4, 338, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #292 = UMULLv5
6126 { 293, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #293 = VLD1LNdAsm_16
6127 { 294, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #294 = VLD1LNdAsm_32
6128 { 295, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #295 = VLD1LNdAsm_8
6129 { 296, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #296 = VLD1LNdWB_fixed_Asm_16
6130 { 297, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #297 = VLD1LNdWB_fixed_Asm_32
6131 { 298, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #298 = VLD1LNdWB_fixed_Asm_8
6132 { 299, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #299 = VLD1LNdWB_register_Asm_16
6133 { 300, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #300 = VLD1LNdWB_register_Asm_32
6134 { 301, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #301 = VLD1LNdWB_register_Asm_8
6135 { 302, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #302 = VLD2LNdAsm_16
6136 { 303, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #303 = VLD2LNdAsm_32
6137 { 304, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #304 = VLD2LNdAsm_8
6138 { 305, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #305 = VLD2LNdWB_fixed_Asm_16
6139 { 306, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #306 = VLD2LNdWB_fixed_Asm_32
6140 { 307, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #307 = VLD2LNdWB_fixed_Asm_8
6141 { 308, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #308 = VLD2LNdWB_register_Asm_16
6142 { 309, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #309 = VLD2LNdWB_register_Asm_32
6143 { 310, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #310 = VLD2LNdWB_register_Asm_8
6144 { 311, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #311 = VLD2LNqAsm_16
6145 { 312, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #312 = VLD2LNqAsm_32
6146 { 313, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #313 = VLD2LNqWB_fixed_Asm_16
6147 { 314, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #314 = VLD2LNqWB_fixed_Asm_32
6148 { 315, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #315 = VLD2LNqWB_register_Asm_16
6149 { 316, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #316 = VLD2LNqWB_register_Asm_32
6150 { 317, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #317 = VLD3DUPdAsm_16
6151 { 318, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #318 = VLD3DUPdAsm_32
6152 { 319, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #319 = VLD3DUPdAsm_8
6153 { 320, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #320 = VLD3DUPdWB_fixed_Asm_16
6154 { 321, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #321 = VLD3DUPdWB_fixed_Asm_32
6155 { 322, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #322 = VLD3DUPdWB_fixed_Asm_8
6156 { 323, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #323 = VLD3DUPdWB_register_Asm_16
6157 { 324, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #324 = VLD3DUPdWB_register_Asm_32
6158 { 325, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #325 = VLD3DUPdWB_register_Asm_8
6159 { 326, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #326 = VLD3DUPqAsm_16
6160 { 327, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #327 = VLD3DUPqAsm_32
6161 { 328, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #328 = VLD3DUPqAsm_8
6162 { 329, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #329 = VLD3DUPqWB_fixed_Asm_16
6163 { 330, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #330 = VLD3DUPqWB_fixed_Asm_32
6164 { 331, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #331 = VLD3DUPqWB_fixed_Asm_8
6165 { 332, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #332 = VLD3DUPqWB_register_Asm_16
6166 { 333, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #333 = VLD3DUPqWB_register_Asm_32
6167 { 334, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #334 = VLD3DUPqWB_register_Asm_8
6168 { 335, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #335 = VLD3LNdAsm_16
6169 { 336, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #336 = VLD3LNdAsm_32
6170 { 337, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #337 = VLD3LNdAsm_8
6171 { 338, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #338 = VLD3LNdWB_fixed_Asm_16
6172 { 339, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #339 = VLD3LNdWB_fixed_Asm_32
6173 { 340, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #340 = VLD3LNdWB_fixed_Asm_8
6174 { 341, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #341 = VLD3LNdWB_register_Asm_16
6175 { 342, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #342 = VLD3LNdWB_register_Asm_32
6176 { 343, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #343 = VLD3LNdWB_register_Asm_8
6177 { 344, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #344 = VLD3LNqAsm_16
6178 { 345, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #345 = VLD3LNqAsm_32
6179 { 346, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #346 = VLD3LNqWB_fixed_Asm_16
6180 { 347, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #347 = VLD3LNqWB_fixed_Asm_32
6181 { 348, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #348 = VLD3LNqWB_register_Asm_16
6182 { 349, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #349 = VLD3LNqWB_register_Asm_32
6183 { 350, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #350 = VLD3dAsm_16
6184 { 351, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #351 = VLD3dAsm_32
6185 { 352, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #352 = VLD3dAsm_8
6186 { 353, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #353 = VLD3dWB_fixed_Asm_16
6187 { 354, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #354 = VLD3dWB_fixed_Asm_32
6188 { 355, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #355 = VLD3dWB_fixed_Asm_8
6189 { 356, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #356 = VLD3dWB_register_Asm_16
6190 { 357, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #357 = VLD3dWB_register_Asm_32
6191 { 358, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #358 = VLD3dWB_register_Asm_8
6192 { 359, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #359 = VLD3qAsm_16
6193 { 360, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #360 = VLD3qAsm_32
6194 { 361, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #361 = VLD3qAsm_8
6195 { 362, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #362 = VLD3qWB_fixed_Asm_16
6196 { 363, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #363 = VLD3qWB_fixed_Asm_32
6197 { 364, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #364 = VLD3qWB_fixed_Asm_8
6198 { 365, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #365 = VLD3qWB_register_Asm_16
6199 { 366, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #366 = VLD3qWB_register_Asm_32
6200 { 367, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #367 = VLD3qWB_register_Asm_8
6201 { 368, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #368 = VLD4DUPdAsm_16
6202 { 369, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #369 = VLD4DUPdAsm_32
6203 { 370, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #370 = VLD4DUPdAsm_8
6204 { 371, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #371 = VLD4DUPdWB_fixed_Asm_16
6205 { 372, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #372 = VLD4DUPdWB_fixed_Asm_32
6206 { 373, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #373 = VLD4DUPdWB_fixed_Asm_8
6207 { 374, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #374 = VLD4DUPdWB_register_Asm_16
6208 { 375, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #375 = VLD4DUPdWB_register_Asm_32
6209 { 376, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #376 = VLD4DUPdWB_register_Asm_8
6210 { 377, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #377 = VLD4DUPqAsm_16
6211 { 378, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #378 = VLD4DUPqAsm_32
6212 { 379, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #379 = VLD4DUPqAsm_8
6213 { 380, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #380 = VLD4DUPqWB_fixed_Asm_16
6214 { 381, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #381 = VLD4DUPqWB_fixed_Asm_32
6215 { 382, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #382 = VLD4DUPqWB_fixed_Asm_8
6216 { 383, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #383 = VLD4DUPqWB_register_Asm_16
6217 { 384, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #384 = VLD4DUPqWB_register_Asm_32
6218 { 385, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #385 = VLD4DUPqWB_register_Asm_8
6219 { 386, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #386 = VLD4LNdAsm_16
6220 { 387, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #387 = VLD4LNdAsm_32
6221 { 388, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #388 = VLD4LNdAsm_8
6222 { 389, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #389 = VLD4LNdWB_fixed_Asm_16
6223 { 390, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #390 = VLD4LNdWB_fixed_Asm_32
6224 { 391, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #391 = VLD4LNdWB_fixed_Asm_8
6225 { 392, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #392 = VLD4LNdWB_register_Asm_16
6226 { 393, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #393 = VLD4LNdWB_register_Asm_32
6227 { 394, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #394 = VLD4LNdWB_register_Asm_8
6228 { 395, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #395 = VLD4LNqAsm_16
6229 { 396, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #396 = VLD4LNqAsm_32
6230 { 397, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #397 = VLD4LNqWB_fixed_Asm_16
6231 { 398, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #398 = VLD4LNqWB_fixed_Asm_32
6232 { 399, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #399 = VLD4LNqWB_register_Asm_16
6233 { 400, 7, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #400 = VLD4LNqWB_register_Asm_32
6234 { 401, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #401 = VLD4dAsm_16
6235 { 402, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #402 = VLD4dAsm_32
6236 { 403, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #403 = VLD4dAsm_8
6237 { 404, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #404 = VLD4dWB_fixed_Asm_16
6238 { 405, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #405 = VLD4dWB_fixed_Asm_32
6239 { 406, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #406 = VLD4dWB_fixed_Asm_8
6240 { 407, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #407 = VLD4dWB_register_Asm_16
6241 { 408, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #408 = VLD4dWB_register_Asm_32
6242 { 409, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #409 = VLD4dWB_register_Asm_8
6243 { 410, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #410 = VLD4qAsm_16
6244 { 411, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #411 = VLD4qAsm_32
6245 { 412, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #412 = VLD4qAsm_8
6246 { 413, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #413 = VLD4qWB_fixed_Asm_16
6247 { 414, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #414 = VLD4qWB_fixed_Asm_32
6248 { 415, 5, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #415 = VLD4qWB_fixed_Asm_8
6249 { 416, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #416 = VLD4qWB_register_Asm_16
6250 { 417, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #417 = VLD4qWB_register_Asm_32
6251 { 418, 6, 0, 0, 1034, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #418 = VLD4qWB_register_Asm_8
6252 { 419, 1, 1, 4, 1042, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #419 = VMOVD0
6253 { 420, 5, 1, 0, 565, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #420 = VMOVDcc
6254 { 421, 1, 1, 4, 991, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #421 = VMOVQ0
6255 { 422, 5, 1, 0, 566, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #422 = VMOVScc
6256 { 423, 6, 0, 0, 801, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #423 = VST1LNdAsm_16
6257 { 424, 6, 0, 0, 801, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #424 = VST1LNdAsm_32
6258 { 425, 6, 0, 0, 801, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #425 = VST1LNdAsm_8
6259 { 426, 6, 0, 0, 803, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #426 = VST1LNdWB_fixed_Asm_16
6260 { 427, 6, 0, 0, 803, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #427 = VST1LNdWB_fixed_Asm_32
6261 { 428, 6, 0, 0, 803, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #428 = VST1LNdWB_fixed_Asm_8
6262 { 429, 7, 0, 0, 803, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #429 = VST1LNdWB_register_Asm_16
6263 { 430, 7, 0, 0, 803, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #430 = VST1LNdWB_register_Asm_32
6264 { 431, 7, 0, 0, 803, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #431 = VST1LNdWB_register_Asm_8
6265 { 432, 6, 0, 0, 806, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #432 = VST2LNdAsm_16
6266 { 433, 6, 0, 0, 806, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #433 = VST2LNdAsm_32
6267 { 434, 6, 0, 0, 806, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #434 = VST2LNdAsm_8
6268 { 435, 6, 0, 0, 811, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #435 = VST2LNdWB_fixed_Asm_16
6269 { 436, 6, 0, 0, 811, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #436 = VST2LNdWB_fixed_Asm_32
6270 { 437, 6, 0, 0, 811, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #437 = VST2LNdWB_fixed_Asm_8
6271 { 438, 7, 0, 0, 811, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #438 = VST2LNdWB_register_Asm_16
6272 { 439, 7, 0, 0, 811, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #439 = VST2LNdWB_register_Asm_32
6273 { 440, 7, 0, 0, 811, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #440 = VST2LNdWB_register_Asm_8
6274 { 441, 6, 0, 0, 809, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #441 = VST2LNqAsm_16
6275 { 442, 6, 0, 0, 809, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #442 = VST2LNqAsm_32
6276 { 443, 6, 0, 0, 813, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #443 = VST2LNqWB_fixed_Asm_16
6277 { 444, 6, 0, 0, 813, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #444 = VST2LNqWB_fixed_Asm_32
6278 { 445, 7, 0, 0, 813, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #445 = VST2LNqWB_register_Asm_16
6279 { 446, 7, 0, 0, 813, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #446 = VST2LNqWB_register_Asm_32
6280 { 447, 6, 0, 0, 818, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #447 = VST3LNdAsm_16
6281 { 448, 6, 0, 0, 818, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #448 = VST3LNdAsm_32
6282 { 449, 6, 0, 0, 818, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #449 = VST3LNdAsm_8
6283 { 450, 6, 0, 0, 824, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #450 = VST3LNdWB_fixed_Asm_16
6284 { 451, 6, 0, 0, 824, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #451 = VST3LNdWB_fixed_Asm_32
6285 { 452, 6, 0, 0, 824, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #452 = VST3LNdWB_fixed_Asm_8
6286 { 453, 7, 0, 0, 824, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #453 = VST3LNdWB_register_Asm_16
6287 { 454, 7, 0, 0, 824, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #454 = VST3LNdWB_register_Asm_32
6288 { 455, 7, 0, 0, 824, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #455 = VST3LNdWB_register_Asm_8
6289 { 456, 6, 0, 0, 820, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #456 = VST3LNqAsm_16
6290 { 457, 6, 0, 0, 820, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #457 = VST3LNqAsm_32
6291 { 458, 6, 0, 0, 826, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #458 = VST3LNqWB_fixed_Asm_16
6292 { 459, 6, 0, 0, 826, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #459 = VST3LNqWB_fixed_Asm_32
6293 { 460, 7, 0, 0, 826, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #460 = VST3LNqWB_register_Asm_16
6294 { 461, 7, 0, 0, 826, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #461 = VST3LNqWB_register_Asm_32
6295 { 462, 5, 0, 0, 815, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #462 = VST3dAsm_16
6296 { 463, 5, 0, 0, 815, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #463 = VST3dAsm_32
6297 { 464, 5, 0, 0, 815, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #464 = VST3dAsm_8
6298 { 465, 5, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #465 = VST3dWB_fixed_Asm_16
6299 { 466, 5, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #466 = VST3dWB_fixed_Asm_32
6300 { 467, 5, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #467 = VST3dWB_fixed_Asm_8
6301 { 468, 6, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #468 = VST3dWB_register_Asm_16
6302 { 469, 6, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #469 = VST3dWB_register_Asm_32
6303 { 470, 6, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #470 = VST3dWB_register_Asm_8
6304 { 471, 5, 0, 0, 815, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #471 = VST3qAsm_16
6305 { 472, 5, 0, 0, 815, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #472 = VST3qAsm_32
6306 { 473, 5, 0, 0, 815, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #473 = VST3qAsm_8
6307 { 474, 5, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #474 = VST3qWB_fixed_Asm_16
6308 { 475, 5, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #475 = VST3qWB_fixed_Asm_32
6309 { 476, 5, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #476 = VST3qWB_fixed_Asm_8
6310 { 477, 6, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #477 = VST3qWB_register_Asm_16
6311 { 478, 6, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #478 = VST3qWB_register_Asm_32
6312 { 479, 6, 0, 0, 822, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #479 = VST3qWB_register_Asm_8
6313 { 480, 6, 0, 0, 831, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #480 = VST4LNdAsm_16
6314 { 481, 6, 0, 0, 831, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #481 = VST4LNdAsm_32
6315 { 482, 6, 0, 0, 831, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #482 = VST4LNdAsm_8
6316 { 483, 6, 0, 0, 838, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #483 = VST4LNdWB_fixed_Asm_16
6317 { 484, 6, 0, 0, 838, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #484 = VST4LNdWB_fixed_Asm_32
6318 { 485, 6, 0, 0, 838, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #485 = VST4LNdWB_fixed_Asm_8
6319 { 486, 7, 0, 0, 838, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #486 = VST4LNdWB_register_Asm_16
6320 { 487, 7, 0, 0, 838, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #487 = VST4LNdWB_register_Asm_32
6321 { 488, 7, 0, 0, 838, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #488 = VST4LNdWB_register_Asm_8
6322 { 489, 6, 0, 0, 834, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #489 = VST4LNqAsm_16
6323 { 490, 6, 0, 0, 834, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #490 = VST4LNqAsm_32
6324 { 491, 6, 0, 0, 840, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #491 = VST4LNqWB_fixed_Asm_16
6325 { 492, 6, 0, 0, 840, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #492 = VST4LNqWB_fixed_Asm_32
6326 { 493, 7, 0, 0, 840, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #493 = VST4LNqWB_register_Asm_16
6327 { 494, 7, 0, 0, 840, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #494 = VST4LNqWB_register_Asm_32
6328 { 495, 5, 0, 0, 828, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #495 = VST4dAsm_16
6329 { 496, 5, 0, 0, 828, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #496 = VST4dAsm_32
6330 { 497, 5, 0, 0, 828, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #497 = VST4dAsm_8
6331 { 498, 5, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #498 = VST4dWB_fixed_Asm_16
6332 { 499, 5, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #499 = VST4dWB_fixed_Asm_32
6333 { 500, 5, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #500 = VST4dWB_fixed_Asm_8
6334 { 501, 6, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #501 = VST4dWB_register_Asm_16
6335 { 502, 6, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #502 = VST4dWB_register_Asm_32
6336 { 503, 6, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #503 = VST4dWB_register_Asm_8
6337 { 504, 5, 0, 0, 828, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #504 = VST4qAsm_16
6338 { 505, 5, 0, 0, 828, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #505 = VST4qAsm_32
6339 { 506, 5, 0, 0, 828, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #506 = VST4qAsm_8
6340 { 507, 5, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #507 = VST4qWB_fixed_Asm_16
6341 { 508, 5, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #508 = VST4qWB_fixed_Asm_32
6342 { 509, 5, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #509 = VST4qWB_fixed_Asm_8
6343 { 510, 6, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #510 = VST4qWB_register_Asm_16
6344 { 511, 6, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #511 = VST4qWB_register_Asm_32
6345 { 512, 6, 0, 0, 836, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #512 = VST4qWB_register_Asm_8
6346 { 513, 0, 0, 0, 849, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList8, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #513 = WIN__CHKSTK
6347 { 514, 1, 0, 0, 849, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #514 = WIN__DBZCHK
6348 { 515, 2, 1, 0, 680, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo89, -1 ,nullptr }, // Inst #515 = t2ABS
6349 { 516, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr }, // Inst #516 = t2ADDSri
6350 { 517, 5, 1, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #517 = t2ADDSrr
6351 { 518, 6, 1, 4, 701, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr }, // Inst #518 = t2ADDSrs
6352 { 519, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #519 = t2BF_LabelPseudo
6353 { 520, 3, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #520 = t2BR_JT
6354 { 521, 1, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #521 = t2DoLoopStart
6355 { 522, 5, 1, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #522 = t2LDMIA_RET
6356 { 523, 4, 0, 0, 905, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #523 = t2LDRBpcrel
6357 { 524, 4, 0, 0, 1010, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #524 = t2LDRConstPool
6358 { 525, 4, 0, 0, 905, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #525 = t2LDRHpcrel
6359 { 526, 4, 0, 0, 398, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #526 = t2LDRSBpcrel
6360 { 527, 4, 0, 0, 398, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #527 = t2LDRSHpcrel
6361 { 528, 3, 1, 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #528 = t2LDRpci_pic
6362 { 529, 4, 0, 0, 905, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #529 = t2LDRpcrel
6363 { 530, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #530 = t2LEApcrel
6364 { 531, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #531 = t2LEApcrelJT
6365 { 532, 3, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #532 = t2LoopDec
6366 { 533, 2, 0, 8, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #533 = t2LoopEnd
6367 { 534, 6, 1, 4, 874, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #534 = t2MOVCCasr
6368 { 535, 5, 1, 4, 678, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #535 = t2MOVCCi
6369 { 536, 5, 1, 4, 678, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #536 = t2MOVCCi16
6370 { 537, 5, 1, 8, 353, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #537 = t2MOVCCi32imm
6371 { 538, 6, 1, 4, 874, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #538 = t2MOVCClsl
6372 { 539, 6, 1, 4, 874, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #539 = t2MOVCClsr
6373 { 540, 5, 1, 4, 875, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #540 = t2MOVCCr
6374 { 541, 6, 1, 4, 874, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #541 = t2MOVCCror
6375 { 542, 5, 0, 0, 710, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #542 = t2MOVSsi
6376 { 543, 6, 0, 0, 687, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #543 = t2MOVSsr
6377 { 544, 4, 1, 0, 876, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #544 = t2MOVTi16_ga_pcrel
6378 { 545, 2, 1, 0, 355, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #545 = t2MOV_ga_pcrel
6379 { 546, 3, 1, 0, 356, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #546 = t2MOVi16_ga_pcrel
6380 { 547, 2, 1, 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #547 = t2MOVi32imm
6381 { 548, 5, 0, 0, 710, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #548 = t2MOVsi
6382 { 549, 6, 0, 0, 687, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #549 = t2MOVsr
6383 { 550, 5, 1, 4, 693, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #550 = t2MVNCCi
6384 { 551, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #551 = t2RSBSri
6385 { 552, 6, 1, 4, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #552 = t2RSBSrs
6386 { 553, 6, 1, 4, 440, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #553 = t2STRB_preidx
6387 { 554, 6, 1, 4, 440, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #554 = t2STRH_preidx
6388 { 555, 6, 1, 4, 440, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #555 = t2STR_preidx
6389 { 556, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr }, // Inst #556 = t2SUBSri
6390 { 557, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #557 = t2SUBSrr
6391 { 558, 6, 1, 4, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr }, // Inst #558 = t2SUBSrs
6392 { 559, 4, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #559 = t2TBB_JT
6393 { 560, 4, 0, 4, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #560 = t2TBH_JT
6394 { 561, 2, 0, 8, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #561 = t2WhileLoopStart
6395 { 562, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #562 = tADCS
6396 { 563, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #563 = tADDSi3
6397 { 564, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #564 = tADDSi8
6398 { 565, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #565 = tADDSrr
6399 { 566, 3, 1, 0, 863, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #566 = tADDframe
6400 { 567, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #567 = tADJCALLSTACKDOWN
6401 { 568, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #568 = tADJCALLSTACKUP
6402 { 569, 4, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo113, -1 ,nullptr }, // Inst #569 = tBL_PUSHLR
6403 { 570, 3, 0, 2, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #570 = tBRIND
6404 { 571, 2, 0, 2, 859, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #571 = tBR_JTr
6405 { 572, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #572 = tBX_CALL
6406 { 573, 2, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #573 = tBX_RET
6407 { 574, 3, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #574 = tBX_RET_vararg
6408 { 575, 3, 0, 4, 853, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo118, -1 ,nullptr }, // Inst #575 = tBfar
6409 { 576, 5, 1, 2, 1008, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #576 = tLDMIA_UPD
6410 { 577, 4, 0, 0, 1010, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #577 = tLDRConstPool
6411 { 578, 2, 1, 0, 1011, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #578 = tLDRLIT_ga_abs
6412 { 579, 2, 1, 0, 1012, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #579 = tLDRLIT_ga_pcrel
6413 { 580, 5, 2, 4, 902, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #580 = tLDR_postidx
6414 { 581, 3, 1, 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #581 = tLDRpci_pic
6415 { 582, 4, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #582 = tLEApcrel
6416 { 583, 4, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #583 = tLEApcrelJT
6417 { 584, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #584 = tLSLSri
6418 { 585, 5, 1, 0, 869, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #585 = tMOVCCr_pseudo
6419 { 586, 3, 0, 2, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #586 = tPOP_RET
6420 { 587, 2, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #587 = tRSBS
6421 { 588, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #588 = tSBCS
6422 { 589, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #589 = tSUBSi3
6423 { 590, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #590 = tSUBSi8
6424 { 591, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #591 = tSUBSrr
6425 { 592, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #592 = tTAILJMPd
6426 { 593, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #593 = tTAILJMPdND
6427 { 594, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #594 = tTAILJMPr
6428 { 595, 4, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #595 = tTBB_JT
6429 { 596, 4, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #596 = tTBH_JT
6430 { 597, 0, 0, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #597 = tTPsoft
gen/lib/Target/AVR/AVRGenInstrInfo.inc 483 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
484 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
485 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
486 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
487 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
488 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
489 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
490 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
491 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
492 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
493 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
494 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
495 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
496 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
497 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
498 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
499 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
500 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
501 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
502 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
503 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
504 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
505 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
506 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
507 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
508 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
509 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
510 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
511 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
512 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
513 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
514 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
515 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
516 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
517 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
518 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
519 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
520 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
521 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
522 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
523 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
524 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
525 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
526 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
527 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
528 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
529 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
530 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
531 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
532 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
533 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
534 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
535 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
536 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
537 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
538 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
539 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
540 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
541 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
542 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
543 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
544 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
545 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
546 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
547 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
548 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
549 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
550 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
551 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
552 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
553 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
554 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
555 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
556 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
557 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
558 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
559 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
560 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
561 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
562 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
563 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
564 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
565 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
566 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
567 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
568 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
569 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
570 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
571 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
572 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
573 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
574 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
575 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
576 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
577 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
578 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
579 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
580 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
581 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
582 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
583 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
584 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
585 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
586 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
587 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
588 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
589 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
590 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
591 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
592 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
593 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
594 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
595 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
596 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
597 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
598 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
599 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
600 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
601 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
602 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
603 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
604 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
605 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
606 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
607 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
608 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
609 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
610 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
611 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
612 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
613 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
614 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
615 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
616 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
617 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
618 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
619 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
620 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
621 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
622 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
623 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
624 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
625 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
626 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
627 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
628 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
629 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
630 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
631 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
632 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
633 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
634 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
635 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
636 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
637 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
638 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
639 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
640 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
641 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
642 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
643 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
644 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
645 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
646 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
647 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
648 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
649 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
650 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
651 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
652 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
653 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
654 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
655 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
656 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
657 { 174, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ADCWRdRr
658 { 175, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = ADDWRdRr
659 { 176, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr }, // Inst #176 = ADJCALLSTACKDOWN
660 { 177, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr }, // Inst #177 = ADJCALLSTACKUP
661 { 178, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #178 = ANDIWRdK
662 { 179, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #179 = ANDWRdRr
663 { 180, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #180 = ASRWRd
664 { 181, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #181 = Asr16
665 { 182, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #182 = Asr8
666 { 183, 0, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #183 = AtomicFence
667 { 184, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #184 = AtomicLoad16
668 { 185, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #185 = AtomicLoad8
669 { 186, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #186 = AtomicLoadAdd16
670 { 187, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #187 = AtomicLoadAdd8
671 { 188, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #188 = AtomicLoadAnd16
672 { 189, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #189 = AtomicLoadAnd8
673 { 190, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #190 = AtomicLoadOr16
674 { 191, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #191 = AtomicLoadOr8
675 { 192, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #192 = AtomicLoadSub16
676 { 193, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #193 = AtomicLoadSub8
677 { 194, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #194 = AtomicLoadXor16
678 { 195, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #195 = AtomicLoadXor8
679 { 196, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #196 = AtomicStore16
680 { 197, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #197 = AtomicStore8
681 { 198, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #198 = COMWRd
682 { 199, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #199 = CPCWRdRr
683 { 200, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #200 = CPWRdRr
684 { 201, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #201 = EORWRdRr
685 { 202, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #202 = FRMIDX
686 { 203, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #203 = INWRdA
687 { 204, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #204 = LDDWRdPtrQ
688 { 205, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #205 = LDDWRdYQ
689 { 206, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #206 = LDIWRdK
690 { 207, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #207 = LDSWRdK
691 { 208, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #208 = LDWRdPtr
692 { 209, 3, 2, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #209 = LDWRdPtrPd
693 { 210, 3, 2, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #210 = LDWRdPtrPi
694 { 211, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #211 = LPMWRdZ
695 { 212, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #212 = LPMWRdZPi
696 { 213, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #213 = LSLWRd
697 { 214, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #214 = LSRWRd
698 { 215, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #215 = Lsl16
699 { 216, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #216 = Lsl8
700 { 217, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #217 = Lsr16
701 { 218, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #218 = Lsr8
702 { 219, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #219 = ORIWRdK
703 { 220, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #220 = ORWRdRr
704 { 221, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #221 = OUTWARr
705 { 222, 1, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo58, -1 ,nullptr }, // Inst #222 = POPWRd
706 { 223, 1, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo58, -1 ,nullptr }, // Inst #223 = PUSHWRr
707 { 224, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #224 = ROLWRd
708 { 225, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #225 = RORWRd
709 { 226, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #226 = Rol16
710 { 227, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #227 = Rol8
711 { 228, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #228 = Ror16
712 { 229, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #229 = Ror8
713 { 230, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #230 = SBCIWRdK
714 { 231, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #231 = SBCWRdRr
715 { 232, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #232 = SEXT
716 { 233, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #233 = SPREAD
717 { 234, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo61, -1 ,nullptr }, // Inst #234 = SPWRITE
718 { 235, 3, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo62, -1 ,nullptr }, // Inst #235 = STDSPQRr
719 { 236, 3, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #236 = STDWPtrQRr
720 { 237, 3, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList2, OperandInfo64, -1 ,nullptr }, // Inst #237 = STDWSPQRr
721 { 238, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #238 = STSWKRr
722 { 239, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #239 = STWPtrPdRr
723 { 240, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #240 = STWPtrPiRr
724 { 241, 2, 0, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #241 = STWPtrRr
725 { 242, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #242 = SUBIWRdK
726 { 243, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #243 = SUBWRdRr
727 { 244, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #244 = Select16
728 { 245, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #245 = Select8
729 { 246, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #246 = ZEXT
gen/lib/Target/BPF/BPFGenInstrInfo.inc 420 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
421 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
422 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
423 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
424 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
425 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
426 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
427 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
428 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
429 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
430 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
431 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
432 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
433 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
434 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
435 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
436 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
437 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
438 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
439 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
440 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
441 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
442 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
443 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
444 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
445 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
446 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
447 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
448 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
449 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
450 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
451 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
452 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
453 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
454 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
455 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
456 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
457 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
458 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
459 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
460 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
461 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
462 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
463 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
464 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
465 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
466 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
467 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
468 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
469 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
470 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
471 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
472 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
473 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
474 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
475 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
476 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
477 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
478 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
479 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
480 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
481 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
482 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
483 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
484 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
485 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
486 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
487 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
488 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
489 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
490 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
491 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
492 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
493 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
494 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
495 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
496 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
497 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
498 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
499 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
500 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
501 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
502 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
503 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
504 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
505 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
506 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
507 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
508 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
509 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
510 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
511 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
512 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
513 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
514 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
515 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
516 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
517 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
518 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
519 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
520 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
521 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
522 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
523 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
524 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
525 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
526 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
527 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
528 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
529 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
530 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
531 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
532 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
533 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
534 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
535 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
536 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
537 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
538 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
539 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
540 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
541 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
542 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
543 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
544 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
545 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
546 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
547 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
548 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
549 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
550 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
551 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
552 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
553 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
554 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
555 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
556 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
557 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
558 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
559 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
560 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
561 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
562 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
563 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
564 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
565 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
566 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
567 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
568 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
569 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
570 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
571 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
572 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
573 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
574 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
575 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
576 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
577 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
578 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
579 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
580 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
581 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
582 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
583 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
584 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
585 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
586 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
587 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
588 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
589 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
590 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
591 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
592 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
593 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
594 { 174, 2, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
595 { 175, 2, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
596 { 176, 4, 0, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = MEMCPY
597 { 177, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #177 = Select
598 { 178, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = Select_32
599 { 179, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = Select_32_64
600 { 180, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #180 = Select_64_32
601 { 181, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #181 = Select_Ri
602 { 182, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #182 = Select_Ri_32
603 { 183, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #183 = Select_Ri_32_64
604 { 184, 6, 1, 8, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #184 = Select_Ri_64_32
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3630 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
3631 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
3632 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
3633 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
3634 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
3635 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
3636 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
3637 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
3638 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
3639 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
3640 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
3641 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
3642 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
3643 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
3644 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
3645 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
3646 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
3647 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
3648 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
3649 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
3650 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
3651 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
3652 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
3653 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
3654 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
3655 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
3656 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
3657 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
3658 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
3659 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
3660 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
3661 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
3662 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
3663 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
3664 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
3665 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
3666 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
3667 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
3668 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
3669 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
3670 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
3671 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
3672 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
3673 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
3674 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
3675 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
3676 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
3677 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
3678 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
3679 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
3680 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
3681 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
3682 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
3683 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
3684 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
3685 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
3686 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
3687 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
3688 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
3689 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
3690 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
3691 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
3692 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
3693 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
3694 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
3695 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
3696 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
3697 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
3698 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
3699 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
3700 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
3701 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
3702 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
3703 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
3704 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
3705 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
3706 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
3707 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
3708 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
3709 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
3710 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
3711 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
3712 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
3713 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
3714 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
3715 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
3716 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
3717 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
3718 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
3719 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
3720 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
3721 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
3722 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
3723 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
3724 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
3725 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
3726 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
3727 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
3728 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
3729 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
3730 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
3731 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
3732 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
3733 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
3734 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
3735 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
3736 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
3737 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
3738 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
3739 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
3740 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
3741 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
3742 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
3743 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
3744 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
3745 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
3746 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
3747 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
3748 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
3749 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
3750 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
3751 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
3752 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
3753 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
3754 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
3755 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
3756 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
3757 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
3758 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
3759 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
3760 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
3761 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
3762 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
3763 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
3764 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
3765 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
3766 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
3767 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
3768 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
3769 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
3770 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
3771 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
3772 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
3773 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
3774 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
3775 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
3776 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
3777 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
3778 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
3779 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
3780 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
3781 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
3782 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
3783 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
3784 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
3785 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
3786 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
3787 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
3788 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
3789 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
3790 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
3791 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
3792 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
3793 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
3794 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
3795 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
3796 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
3797 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
3798 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
3799 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
3800 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
3801 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
3802 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
3803 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
3804 { 174, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x3ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = A2_addsp
3805 { 175, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #175 = A2_iconst
3806 { 176, 2, 1, 4, 3, 0|(1ULL<<MCID::Pseudo), 0x8000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #176 = A2_neg
3807 { 177, 2, 1, 4, 3, 0|(1ULL<<MCID::Pseudo), 0x8000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #177 = A2_not
3808 { 178, 3, 1, 4, 4, 0|(1ULL<<MCID::Pseudo), 0x8c00ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #178 = A2_tfrf
3809 { 179, 3, 1, 4, 5, 0|(1ULL<<MCID::Pseudo), 0x9c00ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = A2_tfrfnew
3810 { 180, 2, 1, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #180 = A2_tfrp
3811 { 181, 3, 1, 4, 6, 0|(1ULL<<MCID::Pseudo), 0xc00ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #181 = A2_tfrpf
3812 { 182, 3, 1, 4, 7, 0|(1ULL<<MCID::Pseudo), 0x1c00ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #182 = A2_tfrpfnew
3813 { 183, 2, 1, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #183 = A2_tfrpi
3814 { 184, 3, 1, 4, 6, 0|(1ULL<<MCID::Pseudo), 0x400ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #184 = A2_tfrpt
3815 { 185, 3, 1, 4, 7, 0|(1ULL<<MCID::Pseudo), 0x1400ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #185 = A2_tfrptnew
3816 { 186, 3, 1, 4, 4, 0|(1ULL<<MCID::Pseudo), 0x8400ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #186 = A2_tfrt
3817 { 187, 3, 1, 4, 5, 0|(1ULL<<MCID::Pseudo), 0x9400ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #187 = A2_tfrtnew
3818 { 188, 3, 1, 4, 8, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #188 = A2_vaddb_map
3819 { 189, 3, 1, 4, 8, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #189 = A2_vsubb_map
3820 { 190, 2, 1, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x8000ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #190 = A2_zxtb
3821 { 191, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo), 0x3ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #191 = A4_boundscheck
3822 { 192, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x29ULL, ImplicitList1, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #192 = ADJCALLSTACKDOWN
3823 { 193, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x29ULL, ImplicitList3, ImplicitList4, OperandInfo8, -1 ,nullptr }, // Inst #193 = ADJCALLSTACKUP
3824 { 194, 3, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #194 = C2_cmpgei
3825 { 195, 3, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #195 = C2_cmpgeui
3826 { 196, 3, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #196 = C2_cmplt
3827 { 197, 3, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #197 = C2_cmpltu
3828 { 198, 2, 1, 4, 11, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #198 = C2_pxfer_map
3829 { 199, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #199 = DUPLEX_Pseudo
3830 { 200, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList5, ImplicitList6, OperandInfo2, -1 ,nullptr }, // Inst #200 = ENDLOOP0
3831 { 201, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList7, ImplicitList8, OperandInfo2, -1 ,nullptr }, // Inst #201 = ENDLOOP01
3832 { 202, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList9, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #202 = ENDLOOP1
3833 { 203, 0, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x24ULL, ImplicitList11, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #203 = J2_endloop0
3834 { 204, 0, 0, 4, 14, 0|(1ULL<<MCID::Pseudo), 0x24ULL, ImplicitList13, ImplicitList14, nullptr, -1 ,nullptr }, // Inst #204 = J2_endloop01
3835 { 205, 0, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x24ULL, ImplicitList15, ImplicitList16, nullptr, -1 ,nullptr }, // Inst #205 = J2_endloop1
3836 { 206, 2, 0, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #206 = J2_jumpf_nopred_map
3837 { 207, 2, 0, 4, 16, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #207 = J2_jumprf_nopred_map
3838 { 208, 2, 0, 4, 16, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #208 = J2_jumprt_nopred_map
3839 { 209, 2, 0, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #209 = J2_jumpt_nopred_map
3840 { 210, 1, 0, 4, 17, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x27ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #210 = J2_trap1_noregmap
3841 { 211, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #211 = L2_loadalignb_zomap
3842 { 212, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #212 = L2_loadalignh_zomap
3843 { 213, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #213 = L2_loadbsw2_zomap
3844 { 214, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #214 = L2_loadbsw4_zomap
3845 { 215, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #215 = L2_loadbzw2_zomap
3846 { 216, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #216 = L2_loadbzw4_zomap
3847 { 217, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #217 = L2_loadrb_zomap
3848 { 218, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #218 = L2_loadrd_zomap
3849 { 219, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #219 = L2_loadrh_zomap
3850 { 220, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #220 = L2_loadri_zomap
3851 { 221, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #221 = L2_loadrub_zomap
3852 { 222, 2, 1, 4, 19, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #222 = L2_loadruh_zomap
3853 { 223, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #223 = L2_ploadrbf_zomap
3854 { 224, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #224 = L2_ploadrbfnew_zomap
3855 { 225, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #225 = L2_ploadrbt_zomap
3856 { 226, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #226 = L2_ploadrbtnew_zomap
3857 { 227, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #227 = L2_ploadrdf_zomap
3858 { 228, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #228 = L2_ploadrdfnew_zomap
3859 { 229, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #229 = L2_ploadrdt_zomap
3860 { 230, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #230 = L2_ploadrdtnew_zomap
3861 { 231, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #231 = L2_ploadrhf_zomap
3862 { 232, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #232 = L2_ploadrhfnew_zomap
3863 { 233, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #233 = L2_ploadrht_zomap
3864 { 234, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #234 = L2_ploadrhtnew_zomap
3865 { 235, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #235 = L2_ploadrif_zomap
3866 { 236, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #236 = L2_ploadrifnew_zomap
3867 { 237, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #237 = L2_ploadrit_zomap
3868 { 238, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #238 = L2_ploadritnew_zomap
3869 { 239, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #239 = L2_ploadrubf_zomap
3870 { 240, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #240 = L2_ploadrubfnew_zomap
3871 { 241, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #241 = L2_ploadrubt_zomap
3872 { 242, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #242 = L2_ploadrubtnew_zomap
3873 { 243, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #243 = L2_ploadruhf_zomap
3874 { 244, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #244 = L2_ploadruhfnew_zomap
3875 { 245, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #245 = L2_ploadruht_zomap
3876 { 246, 3, 1, 4, 20, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #246 = L2_ploadruhtnew_zomap
3877 { 247, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #247 = L4_add_memopb_zomap
3878 { 248, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #248 = L4_add_memoph_zomap
3879 { 249, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #249 = L4_add_memopw_zomap
3880 { 250, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #250 = L4_and_memopb_zomap
3881 { 251, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #251 = L4_and_memoph_zomap
3882 { 252, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #252 = L4_and_memopw_zomap
3883 { 253, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #253 = L4_iadd_memopb_zomap
3884 { 254, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #254 = L4_iadd_memoph_zomap
3885 { 255, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #255 = L4_iadd_memopw_zomap
3886 { 256, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #256 = L4_iand_memopb_zomap
3887 { 257, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #257 = L4_iand_memoph_zomap
3888 { 258, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #258 = L4_iand_memopw_zomap
3889 { 259, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #259 = L4_ior_memopb_zomap
3890 { 260, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #260 = L4_ior_memoph_zomap
3891 { 261, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #261 = L4_ior_memopw_zomap
3892 { 262, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #262 = L4_isub_memopb_zomap
3893 { 263, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #263 = L4_isub_memoph_zomap
3894 { 264, 2, 0, 4, 22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #264 = L4_isub_memopw_zomap
3895 { 265, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #265 = L4_or_memopb_zomap
3896 { 266, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #266 = L4_or_memoph_zomap
3897 { 267, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #267 = L4_or_memopw_zomap
3898 { 268, 1, 0, 4, 23, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #268 = L4_return_map_to_raw_f
3899 { 269, 1, 0, 4, 24, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #269 = L4_return_map_to_raw_fnew_pnt
3900 { 270, 1, 0, 4, 24, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #270 = L4_return_map_to_raw_fnew_pt
3901 { 271, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #271 = L4_return_map_to_raw_t
3902 { 272, 1, 0, 4, 26, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #272 = L4_return_map_to_raw_tnew_pnt
3903 { 273, 1, 0, 4, 26, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #273 = L4_return_map_to_raw_tnew_pt
3904 { 274, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #274 = L4_sub_memopb_zomap
3905 { 275, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #275 = L4_sub_memoph_zomap
3906 { 276, 2, 0, 4, 21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #276 = L4_sub_memopw_zomap
3907 { 277, 0, 0, 4, 27, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #277 = L6_deallocframe_map_to_raw
3908 { 278, 0, 0, 4, 28, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #278 = L6_return_map_to_raw
3909 { 279, 3, 1, 4, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b4800025ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #279 = LDriw_ctr
3910 { 280, 3, 1, 4, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b4800025ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #280 = LDriw_pred
3911 { 281, 3, 1, 4, 30, 0|(1ULL<<MCID::Pseudo), 0x134808026ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #281 = M2_mpysmi
3912 { 282, 3, 1, 4, 31, 0|(1ULL<<MCID::Pseudo), 0x8026ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #282 = M2_mpyui
3913 { 283, 4, 1, 4, 32, 0|(1ULL<<MCID::Pseudo), 0x26ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #283 = M2_vrcmpys_acc_s1
3914 { 284, 3, 1, 4, 31, 0|(1ULL<<MCID::Pseudo), 0x26ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #284 = M2_vrcmpys_s1
3915 { 285, 3, 1, 4, 31, 0|(1ULL<<MCID::Pseudo), 0x8026ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #285 = M2_vrcmpys_s1rp
3916 { 286, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x29ULL, ImplicitList17, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #286 = PS_aligna
3917 { 287, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x29ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #287 = PS_alloca
3918 { 288, 1, 0, 4, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800029ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #288 = PS_call_nr
3919 { 289, 0, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #289 = PS_crash
3920 { 290, 1, 1, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #290 = PS_false
3921 { 291, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x214800029ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #291 = PS_fi
3922 { 292, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x216800029ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #292 = PS_fia
3923 { 293, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #293 = PS_loadrb_pci
3924 { 294, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #294 = PS_loadrb_pcr
3925 { 295, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr }, // Inst #295 = PS_loadrd_pci
3926 { 296, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, ImplicitList18, OperandInfo64, -1 ,nullptr }, // Inst #296 = PS_loadrd_pcr
3927 { 297, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #297 = PS_loadrh_pci
3928 { 298, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #298 = PS_loadrh_pcr
3929 { 299, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #299 = PS_loadri_pci
3930 { 300, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #300 = PS_loadri_pcr
3931 { 301, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #301 = PS_loadrub_pci
3932 { 302, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #302 = PS_loadrub_pcr
3933 { 303, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #303 = PS_loadruh_pci
3934 { 304, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #304 = PS_loadruh_pcr
3935 { 305, 4, 1, 4, 6, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #305 = PS_pselect
3936 { 306, 1, 1, 4, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #306 = PS_qfalse
3937 { 307, 1, 1, 4, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #307 = PS_qtrue
3938 { 308, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x38000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #308 = PS_storerb_pci
3939 { 309, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x38000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #309 = PS_storerb_pcr
3940 { 310, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo69, -1 ,nullptr }, // Inst #310 = PS_storerd_pci
3941 { 311, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo70, -1 ,nullptr }, // Inst #311 = PS_storerd_pcr
3942 { 312, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #312 = PS_storerf_pci
3943 { 313, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #313 = PS_storerf_pcr
3944 { 314, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #314 = PS_storerh_pci
3945 { 315, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #315 = PS_storerh_pcr
3946 { 316, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #316 = PS_storeri_pci
3947 { 317, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #317 = PS_storeri_pcr
3948 { 318, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #318 = PS_tailcall_i
3949 { 319, 1, 0, 4, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #319 = PS_tailcall_r
3950 { 320, 1, 1, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #320 = PS_true
3951 { 321, 1, 1, 4, 39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x11ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #321 = PS_vdd0
3952 { 322, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x29ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #322 = PS_vloadrq_ai
3953 { 323, 3, 1, 4, 40, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xa00000000013ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #323 = PS_vloadrw_ai
3954 { 324, 3, 1, 4, 40, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xa00000000013ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #324 = PS_vloadrw_nt_ai
3955 { 325, 3, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xa00000000018ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #325 = PS_vloadrwu_ai
3956 { 326, 3, 1, 4, 42, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #326 = PS_vmulw
3957 { 327, 4, 1, 4, 42, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #327 = PS_vmulw_acc
3958 { 328, 4, 1, 4, 43, 0|(1ULL<<MCID::Pseudo), 0x10ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #328 = PS_vselect
3959 { 329, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x29ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #329 = PS_vstorerq_ai
3960 { 330, 3, 0, 4, 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xa00000000015ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #330 = PS_vstorerw_ai
3961 { 331, 3, 0, 4, 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xa00000000015ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #331 = PS_vstorerw_nt_ai
3962 { 332, 3, 0, 4, 45, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xa00000000016ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #332 = PS_vstorerwu_ai
3963 { 333, 4, 1, 4, 46, 0|(1ULL<<MCID::Pseudo), 0x11ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #333 = PS_wselect
3964 { 334, 3, 1, 4, 47, 0|(1ULL<<MCID::Pseudo), 0x2cULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #334 = S2_asr_i_p_rnd_goodsyntax
3965 { 335, 3, 1, 4, 47, 0|(1ULL<<MCID::Pseudo), 0x802cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #335 = S2_asr_i_r_rnd_goodsyntax
3966 { 336, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #336 = S2_pstorerbf_zomap
3967 { 337, 3, 0, 4, 49, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #337 = S2_pstorerbnewf_zomap
3968 { 338, 3, 0, 4, 49, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #338 = S2_pstorerbnewt_zomap
3969 { 339, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #339 = S2_pstorerbt_zomap
3970 { 340, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #340 = S2_pstorerdf_zomap
3971 { 341, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #341 = S2_pstorerdt_zomap
3972 { 342, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #342 = S2_pstorerff_zomap
3973 { 343, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #343 = S2_pstorerft_zomap
3974 { 344, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #344 = S2_pstorerhf_zomap
3975 { 345, 3, 0, 4, 49, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #345 = S2_pstorerhnewf_zomap
3976 { 346, 3, 0, 4, 49, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #346 = S2_pstorerhnewt_zomap
3977 { 347, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #347 = S2_pstorerht_zomap
3978 { 348, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #348 = S2_pstorerif_zomap
3979 { 349, 3, 0, 4, 49, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #349 = S2_pstorerinewf_zomap
3980 { 350, 3, 0, 4, 49, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #350 = S2_pstorerinewt_zomap
3981 { 351, 3, 0, 4, 48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #351 = S2_pstorerit_zomap
3982 { 352, 2, 0, 4, 50, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #352 = S2_storerb_zomap
3983 { 353, 2, 0, 4, 51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #353 = S2_storerbnew_zomap
3984 { 354, 2, 0, 4, 50, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #354 = S2_storerd_zomap
3985 { 355, 2, 0, 4, 50, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #355 = S2_storerf_zomap
3986 { 356, 2, 0, 4, 50, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #356 = S2_storerh_zomap
3987 { 357, 2, 0, 4, 51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #357 = S2_storerhnew_zomap
3988 { 358, 2, 0, 4, 50, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #358 = S2_storeri_zomap
3989 { 359, 2, 0, 4, 51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #359 = S2_storerinew_zomap
3990 { 360, 5, 1, 4, 52, 0|(1ULL<<MCID::Pseudo), 0x802cULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #360 = S2_tableidxb_goodsyntax
3991 { 361, 5, 1, 4, 52, 0|(1ULL<<MCID::Pseudo), 0x802cULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #361 = S2_tableidxd_goodsyntax
3992 { 362, 5, 1, 4, 52, 0|(1ULL<<MCID::Pseudo), 0x802cULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #362 = S2_tableidxh_goodsyntax
3993 { 363, 5, 1, 4, 52, 0|(1ULL<<MCID::Pseudo), 0x802cULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #363 = S2_tableidxw_goodsyntax
3994 { 364, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #364 = S4_pstorerbfnew_zomap
3995 { 365, 3, 0, 4, 53, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #365 = S4_pstorerbnewfnew_zomap
3996 { 366, 3, 0, 4, 53, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #366 = S4_pstorerbnewtnew_zomap
3997 { 367, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #367 = S4_pstorerbtnew_zomap
3998 { 368, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #368 = S4_pstorerdfnew_zomap
3999 { 369, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #369 = S4_pstorerdtnew_zomap
4000 { 370, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #370 = S4_pstorerffnew_zomap
4001 { 371, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #371 = S4_pstorerftnew_zomap
4002 { 372, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #372 = S4_pstorerhfnew_zomap
4003 { 373, 3, 0, 4, 53, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #373 = S4_pstorerhnewfnew_zomap
4004 { 374, 3, 0, 4, 53, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #374 = S4_pstorerhnewtnew_zomap
4005 { 375, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #375 = S4_pstorerhtnew_zomap
4006 { 376, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #376 = S4_pstorerifnew_zomap
4007 { 377, 3, 0, 4, 53, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #377 = S4_pstorerinewfnew_zomap
4008 { 378, 3, 0, 4, 53, 0|(1ULL<<MCID::Pseudo), 0x20027ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #378 = S4_pstorerinewtnew_zomap
4009 { 379, 3, 0, 4, 37, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #379 = S4_pstoreritnew_zomap
4010 { 380, 2, 0, 4, 54, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #380 = S4_storeirb_zomap
4011 { 381, 3, 0, 4, 55, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #381 = S4_storeirbf_zomap
4012 { 382, 3, 0, 4, 56, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #382 = S4_storeirbfnew_zomap
4013 { 383, 3, 0, 4, 55, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #383 = S4_storeirbt_zomap
4014 { 384, 3, 0, 4, 56, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #384 = S4_storeirbtnew_zomap
4015 { 385, 2, 0, 4, 54, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #385 = S4_storeirh_zomap
4016 { 386, 3, 0, 4, 55, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #386 = S4_storeirhf_zomap
4017 { 387, 3, 0, 4, 56, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #387 = S4_storeirhfnew_zomap
4018 { 388, 3, 0, 4, 55, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #388 = S4_storeirht_zomap
4019 { 389, 3, 0, 4, 56, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #389 = S4_storeirhtnew_zomap
4020 { 390, 2, 0, 4, 54, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #390 = S4_storeiri_zomap
4021 { 391, 3, 0, 4, 55, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #391 = S4_storeirif_zomap
4022 { 392, 3, 0, 4, 56, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #392 = S4_storeirifnew_zomap
4023 { 393, 3, 0, 4, 55, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #393 = S4_storeirit_zomap
4024 { 394, 3, 0, 4, 56, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #394 = S4_storeiritnew_zomap
4025 { 395, 3, 1, 4, 47, 0|(1ULL<<MCID::Pseudo), 0x802cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #395 = S5_asrhub_rnd_sat_goodsyntax
4026 { 396, 3, 1, 4, 47, 0|(1ULL<<MCID::Pseudo), 0x2cULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #396 = S5_vasrhrnd_goodsyntax
4027 { 397, 1, 0, 4, 57, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #397 = S6_allocframe_to_raw
4028 { 398, 3, 0, 4, 58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b280002aULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #398 = STriw_ctr
4029 { 399, 3, 0, 4, 58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b280002aULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #399 = STriw_pred
4030 { 400, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #400 = V6_MAP_equb
4031 { 401, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #401 = V6_MAP_equb_and
4032 { 402, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #402 = V6_MAP_equb_ior
4033 { 403, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #403 = V6_MAP_equb_xor
4034 { 404, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #404 = V6_MAP_equh
4035 { 405, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #405 = V6_MAP_equh_and
4036 { 406, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #406 = V6_MAP_equh_ior
4037 { 407, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #407 = V6_MAP_equh_xor
4038 { 408, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #408 = V6_MAP_equw
4039 { 409, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #409 = V6_MAP_equw_and
4040 { 410, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #410 = V6_MAP_equw_ior
4041 { 411, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #411 = V6_MAP_equw_xor
4042 { 412, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #412 = V6_extractw_alt
4043 { 413, 2, 1, 4, 59, 0|(1ULL<<MCID::Pseudo), 0x8010ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #413 = V6_hi
4044 { 414, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8013ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #414 = V6_ld0
4045 { 415, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #415 = V6_ldcnp0
4046 { 416, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #416 = V6_ldcnpnt0
4047 { 417, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #417 = V6_ldcp0
4048 { 418, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #418 = V6_ldcpnt0
4049 { 419, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #419 = V6_ldnp0
4050 { 420, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #420 = V6_ldnpnt0
4051 { 421, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8013ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #421 = V6_ldnt0
4052 { 422, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #422 = V6_ldntnt0
4053 { 423, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #423 = V6_ldp0
4054 { 424, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #424 = V6_ldpnt0
4055 { 425, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #425 = V6_ldtnp0
4056 { 426, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #426 = V6_ldtnpnt0
4057 { 427, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #427 = V6_ldtp0
4058 { 428, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #428 = V6_ldtpnt0
4059 { 429, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8013ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #429 = V6_ldu0
4060 { 430, 2, 1, 4, 59, 0|(1ULL<<MCID::Pseudo), 0x8010ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #430 = V6_lo
4061 { 431, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #431 = V6_st0
4062 { 432, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x10015ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #432 = V6_stn0
4063 { 433, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x10015ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #433 = V6_stnnt0
4064 { 434, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #434 = V6_stnp0
4065 { 435, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #435 = V6_stnpnt0
4066 { 436, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #436 = V6_stnq0
4067 { 437, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #437 = V6_stnqnt0
4068 { 438, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #438 = V6_stnt0
4069 { 439, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #439 = V6_stp0
4070 { 440, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #440 = V6_stpnt0
4071 { 441, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #441 = V6_stq0
4072 { 442, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #442 = V6_stqnt0
4073 { 443, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #443 = V6_stu0
4074 { 444, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #444 = V6_stunp0
4075 { 445, 3, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #445 = V6_stup0
4076 { 446, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #446 = V6_vabsb_alt
4077 { 447, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #447 = V6_vabsb_sat_alt
4078 { 448, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #448 = V6_vabsdiffh_alt
4079 { 449, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #449 = V6_vabsdiffub_alt
4080 { 450, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #450 = V6_vabsdiffuh_alt
4081 { 451, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #451 = V6_vabsdiffw_alt
4082 { 452, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #452 = V6_vabsh_alt
4083 { 453, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #453 = V6_vabsh_sat_alt
4084 { 454, 2, 1, 4, 60, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #454 = V6_vabsub_alt
4085 { 455, 2, 1, 4, 60, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #455 = V6_vabsuh_alt
4086 { 456, 2, 1, 4, 60, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #456 = V6_vabsuw_alt
4087 { 457, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #457 = V6_vabsw_alt
4088 { 458, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #458 = V6_vabsw_sat_alt
4089 { 459, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #459 = V6_vaddb_alt
4090 { 460, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #460 = V6_vaddb_dv_alt
4091 { 461, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #461 = V6_vaddbnq_alt
4092 { 462, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #462 = V6_vaddbq_alt
4093 { 463, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #463 = V6_vaddbsat_alt
4094 { 464, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #464 = V6_vaddbsat_dv_alt
4095 { 465, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #465 = V6_vaddh_alt
4096 { 466, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #466 = V6_vaddh_dv_alt
4097 { 467, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #467 = V6_vaddhnq_alt
4098 { 468, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #468 = V6_vaddhq_alt
4099 { 469, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #469 = V6_vaddhsat_alt
4100 { 470, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #470 = V6_vaddhsat_dv_alt
4101 { 471, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #471 = V6_vaddhw_acc_alt
4102 { 472, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #472 = V6_vaddhw_alt
4103 { 473, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #473 = V6_vaddubh_acc_alt
4104 { 474, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #474 = V6_vaddubh_alt
4105 { 475, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #475 = V6_vaddubsat_alt
4106 { 476, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #476 = V6_vaddubsat_dv_alt
4107 { 477, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #477 = V6_vadduhsat_alt
4108 { 478, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #478 = V6_vadduhsat_dv_alt
4109 { 479, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #479 = V6_vadduhw_acc_alt
4110 { 480, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #480 = V6_vadduhw_alt
4111 { 481, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #481 = V6_vadduwsat_alt
4112 { 482, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #482 = V6_vadduwsat_dv_alt
4113 { 483, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #483 = V6_vaddw_alt
4114 { 484, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #484 = V6_vaddw_dv_alt
4115 { 485, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #485 = V6_vaddwnq_alt
4116 { 486, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #486 = V6_vaddwq_alt
4117 { 487, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #487 = V6_vaddwsat_alt
4118 { 488, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #488 = V6_vaddwsat_dv_alt
4119 { 489, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #489 = V6_vandnqrt_acc_alt
4120 { 490, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #490 = V6_vandnqrt_alt
4121 { 491, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #491 = V6_vandqrt_acc_alt
4122 { 492, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #492 = V6_vandqrt_alt
4123 { 493, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #493 = V6_vandvrt_acc_alt
4124 { 494, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #494 = V6_vandvrt_alt
4125 { 495, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #495 = V6_vaslh_acc_alt
4126 { 496, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #496 = V6_vaslh_alt
4127 { 497, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #497 = V6_vaslhv_alt
4128 { 498, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #498 = V6_vaslw_acc_alt
4129 { 499, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #499 = V6_vaslw_alt
4130 { 500, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #500 = V6_vaslwv_alt
4131 { 501, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #501 = V6_vasr_into_alt
4132 { 502, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #502 = V6_vasrh_acc_alt
4133 { 503, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #503 = V6_vasrh_alt
4134 { 504, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #504 = V6_vasrhbrndsat_alt
4135 { 505, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #505 = V6_vasrhubrndsat_alt
4136 { 506, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #506 = V6_vasrhubsat_alt
4137 { 507, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #507 = V6_vasrhv_alt
4138 { 508, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #508 = V6_vasrw_acc_alt
4139 { 509, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #509 = V6_vasrw_alt
4140 { 510, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #510 = V6_vasrwh_alt
4141 { 511, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #511 = V6_vasrwhrndsat_alt
4142 { 512, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #512 = V6_vasrwhsat_alt
4143 { 513, 4, 1, 4, 61, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #513 = V6_vasrwuhsat_alt
4144 { 514, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #514 = V6_vasrwv_alt
4145 { 515, 2, 1, 4, 59, 0|(1ULL<<MCID::Pseudo), 0x8011ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #515 = V6_vassignp
4146 { 516, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #516 = V6_vavgb_alt
4147 { 517, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #517 = V6_vavgbrnd_alt
4148 { 518, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #518 = V6_vavgh_alt
4149 { 519, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #519 = V6_vavghrnd_alt
4150 { 520, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #520 = V6_vavgub_alt
4151 { 521, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #521 = V6_vavgubrnd_alt
4152 { 522, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #522 = V6_vavguh_alt
4153 { 523, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #523 = V6_vavguhrnd_alt
4154 { 524, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #524 = V6_vavguw_alt
4155 { 525, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #525 = V6_vavguwrnd_alt
4156 { 526, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #526 = V6_vavgw_alt
4157 { 527, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #527 = V6_vavgwrnd_alt
4158 { 528, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #528 = V6_vcl0h_alt
4159 { 529, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #529 = V6_vcl0w_alt
4160 { 530, 1, 1, 4, 59, 0|(1ULL<<MCID::Pseudo), 0x8010ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #530 = V6_vd0
4161 { 531, 1, 1, 4, 62, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #531 = V6_vdd0
4162 { 532, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #532 = V6_vdealb4w_alt
4163 { 533, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #533 = V6_vdealb_alt
4164 { 534, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #534 = V6_vdealh_alt
4165 { 535, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #535 = V6_vdmpybus_acc_alt
4166 { 536, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #536 = V6_vdmpybus_alt
4167 { 537, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #537 = V6_vdmpybus_dv_acc_alt
4168 { 538, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #538 = V6_vdmpybus_dv_alt
4169 { 539, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #539 = V6_vdmpyhb_acc_alt
4170 { 540, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #540 = V6_vdmpyhb_alt
4171 { 541, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #541 = V6_vdmpyhb_dv_acc_alt
4172 { 542, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #542 = V6_vdmpyhb_dv_alt
4173 { 543, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #543 = V6_vdmpyhisat_acc_alt
4174 { 544, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #544 = V6_vdmpyhisat_alt
4175 { 545, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #545 = V6_vdmpyhsat_acc_alt
4176 { 546, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #546 = V6_vdmpyhsat_alt
4177 { 547, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #547 = V6_vdmpyhsuisat_acc_alt
4178 { 548, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #548 = V6_vdmpyhsuisat_alt
4179 { 549, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #549 = V6_vdmpyhsusat_acc_alt
4180 { 550, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #550 = V6_vdmpyhsusat_alt
4181 { 551, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #551 = V6_vdmpyhvsat_acc_alt
4182 { 552, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #552 = V6_vdmpyhvsat_alt
4183 { 553, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #553 = V6_vdsaduh_acc_alt
4184 { 554, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #554 = V6_vdsaduh_alt
4185 { 555, 4, 0, 4, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #555 = V6_vgathermh_pseudo
4186 { 556, 5, 0, 4, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #556 = V6_vgathermhq_pseudo
4187 { 557, 4, 0, 4, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #557 = V6_vgathermhw_pseudo
4188 { 558, 5, 0, 4, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #558 = V6_vgathermhwq_pseudo
4189 { 559, 4, 0, 4, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #559 = V6_vgathermw_pseudo
4190 { 560, 5, 0, 4, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #560 = V6_vgathermwq_pseudo
4191 { 561, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #561 = V6_vlsrh_alt
4192 { 562, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #562 = V6_vlsrhv_alt
4193 { 563, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #563 = V6_vlsrw_alt
4194 { 564, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #564 = V6_vlsrwv_alt
4195 { 565, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #565 = V6_vmaxb_alt
4196 { 566, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #566 = V6_vmaxh_alt
4197 { 567, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #567 = V6_vmaxub_alt
4198 { 568, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #568 = V6_vmaxuh_alt
4199 { 569, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #569 = V6_vmaxw_alt
4200 { 570, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #570 = V6_vminb_alt
4201 { 571, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #571 = V6_vminh_alt
4202 { 572, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #572 = V6_vminub_alt
4203 { 573, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #573 = V6_vminuh_alt
4204 { 574, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #574 = V6_vminw_alt
4205 { 575, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #575 = V6_vmpabus_acc_alt
4206 { 576, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #576 = V6_vmpabus_alt
4207 { 577, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #577 = V6_vmpabusv_alt
4208 { 578, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #578 = V6_vmpabuu_acc_alt
4209 { 579, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #579 = V6_vmpabuu_alt
4210 { 580, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #580 = V6_vmpabuuv_alt
4211 { 581, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #581 = V6_vmpahb_acc_alt
4212 { 582, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #582 = V6_vmpahb_alt
4213 { 583, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #583 = V6_vmpauhb_acc_alt
4214 { 584, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #584 = V6_vmpauhb_alt
4215 { 585, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #585 = V6_vmpybus_acc_alt
4216 { 586, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #586 = V6_vmpybus_alt
4217 { 587, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #587 = V6_vmpybusv_acc_alt
4218 { 588, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #588 = V6_vmpybusv_alt
4219 { 589, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #589 = V6_vmpybv_acc_alt
4220 { 590, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #590 = V6_vmpybv_alt
4221 { 591, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #591 = V6_vmpyewuh_alt
4222 { 592, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #592 = V6_vmpyh_acc_alt
4223 { 593, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #593 = V6_vmpyh_alt
4224 { 594, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #594 = V6_vmpyhsat_acc_alt
4225 { 595, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #595 = V6_vmpyhsrs_alt
4226 { 596, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #596 = V6_vmpyhss_alt
4227 { 597, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #597 = V6_vmpyhus_acc_alt
4228 { 598, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #598 = V6_vmpyhus_alt
4229 { 599, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #599 = V6_vmpyhv_acc_alt
4230 { 600, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #600 = V6_vmpyhv_alt
4231 { 601, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #601 = V6_vmpyhvsrs_alt
4232 { 602, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #602 = V6_vmpyiewh_acc_alt
4233 { 603, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #603 = V6_vmpyiewuh_acc_alt
4234 { 604, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #604 = V6_vmpyiewuh_alt
4235 { 605, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #605 = V6_vmpyih_acc_alt
4236 { 606, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #606 = V6_vmpyih_alt
4237 { 607, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #607 = V6_vmpyihb_acc_alt
4238 { 608, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #608 = V6_vmpyihb_alt
4239 { 609, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #609 = V6_vmpyiowh_alt
4240 { 610, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #610 = V6_vmpyiwb_acc_alt
4241 { 611, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #611 = V6_vmpyiwb_alt
4242 { 612, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #612 = V6_vmpyiwh_acc_alt
4243 { 613, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #613 = V6_vmpyiwh_alt
4244 { 614, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #614 = V6_vmpyiwub_acc_alt
4245 { 615, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #615 = V6_vmpyiwub_alt
4246 { 616, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #616 = V6_vmpyowh_alt
4247 { 617, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #617 = V6_vmpyowh_rnd_alt
4248 { 618, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #618 = V6_vmpyowh_rnd_sacc_alt
4249 { 619, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #619 = V6_vmpyowh_sacc_alt
4250 { 620, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #620 = V6_vmpyub_acc_alt
4251 { 621, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #621 = V6_vmpyub_alt
4252 { 622, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #622 = V6_vmpyubv_acc_alt
4253 { 623, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #623 = V6_vmpyubv_alt
4254 { 624, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #624 = V6_vmpyuh_acc_alt
4255 { 625, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #625 = V6_vmpyuh_alt
4256 { 626, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #626 = V6_vmpyuhv_acc_alt
4257 { 627, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #627 = V6_vmpyuhv_alt
4258 { 628, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #628 = V6_vnavgb_alt
4259 { 629, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #629 = V6_vnavgh_alt
4260 { 630, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #630 = V6_vnavgub_alt
4261 { 631, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #631 = V6_vnavgw_alt
4262 { 632, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #632 = V6_vnormamth_alt
4263 { 633, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #633 = V6_vnormamtw_alt
4264 { 634, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #634 = V6_vpackeb_alt
4265 { 635, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #635 = V6_vpackeh_alt
4266 { 636, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #636 = V6_vpackhb_sat_alt
4267 { 637, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #637 = V6_vpackhub_sat_alt
4268 { 638, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #638 = V6_vpackob_alt
4269 { 639, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #639 = V6_vpackoh_alt
4270 { 640, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #640 = V6_vpackwh_sat_alt
4271 { 641, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #641 = V6_vpackwuh_sat_alt
4272 { 642, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #642 = V6_vpopcounth_alt
4273 { 643, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #643 = V6_vrmpybub_rtt_acc_alt
4274 { 644, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #644 = V6_vrmpybub_rtt_alt
4275 { 645, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #645 = V6_vrmpybus_acc_alt
4276 { 646, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #646 = V6_vrmpybus_alt
4277 { 647, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #647 = V6_vrmpybusi_acc_alt
4278 { 648, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #648 = V6_vrmpybusi_alt
4279 { 649, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #649 = V6_vrmpybusv_acc_alt
4280 { 650, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #650 = V6_vrmpybusv_alt
4281 { 651, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #651 = V6_vrmpybv_acc_alt
4282 { 652, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #652 = V6_vrmpybv_alt
4283 { 653, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #653 = V6_vrmpyub_acc_alt
4284 { 654, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #654 = V6_vrmpyub_alt
4285 { 655, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #655 = V6_vrmpyub_rtt_acc_alt
4286 { 656, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #656 = V6_vrmpyub_rtt_alt
4287 { 657, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #657 = V6_vrmpyubi_acc_alt
4288 { 658, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #658 = V6_vrmpyubi_alt
4289 { 659, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #659 = V6_vrmpyubv_acc_alt
4290 { 660, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #660 = V6_vrmpyubv_alt
4291 { 661, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #661 = V6_vrotr_alt
4292 { 662, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #662 = V6_vroundhb_alt
4293 { 663, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #663 = V6_vroundhub_alt
4294 { 664, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #664 = V6_vrounduhub_alt
4295 { 665, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #665 = V6_vrounduwuh_alt
4296 { 666, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #666 = V6_vroundwh_alt
4297 { 667, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #667 = V6_vroundwuh_alt
4298 { 668, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #668 = V6_vrsadubi_acc_alt
4299 { 669, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #669 = V6_vrsadubi_alt
4300 { 670, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #670 = V6_vsathub_alt
4301 { 671, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #671 = V6_vsatuwuh_alt
4302 { 672, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #672 = V6_vsatwh_alt
4303 { 673, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #673 = V6_vsb_alt
4304 { 674, 4, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #674 = V6_vscattermh_add_alt
4305 { 675, 4, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #675 = V6_vscattermh_alt
4306 { 676, 5, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #676 = V6_vscattermhq_alt
4307 { 677, 4, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #677 = V6_vscattermw_add_alt
4308 { 678, 4, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #678 = V6_vscattermw_alt
4309 { 679, 4, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #679 = V6_vscattermwh_add_alt
4310 { 680, 4, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #680 = V6_vscattermwh_alt
4311 { 681, 5, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #681 = V6_vscattermwhq_alt
4312 { 682, 5, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #682 = V6_vscattermwq_alt
4313 { 683, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #683 = V6_vsh_alt
4314 { 684, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #684 = V6_vshufeh_alt
4315 { 685, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #685 = V6_vshuffb_alt
4316 { 686, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #686 = V6_vshuffeb_alt
4317 { 687, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #687 = V6_vshuffh_alt
4318 { 688, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #688 = V6_vshuffob_alt
4319 { 689, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #689 = V6_vshufoeb_alt
4320 { 690, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #690 = V6_vshufoeh_alt
4321 { 691, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #691 = V6_vshufoh_alt
4322 { 692, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #692 = V6_vsubb_alt
4323 { 693, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #693 = V6_vsubb_dv_alt
4324 { 694, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #694 = V6_vsubbnq_alt
4325 { 695, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #695 = V6_vsubbq_alt
4326 { 696, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #696 = V6_vsubbsat_alt
4327 { 697, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #697 = V6_vsubbsat_dv_alt
4328 { 698, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #698 = V6_vsubh_alt
4329 { 699, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #699 = V6_vsubh_dv_alt
4330 { 700, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #700 = V6_vsubhnq_alt
4331 { 701, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #701 = V6_vsubhq_alt
4332 { 702, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #702 = V6_vsubhsat_alt
4333 { 703, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #703 = V6_vsubhsat_dv_alt
4334 { 704, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #704 = V6_vsubhw_alt
4335 { 705, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #705 = V6_vsububh_alt
4336 { 706, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #706 = V6_vsububsat_alt
4337 { 707, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #707 = V6_vsububsat_dv_alt
4338 { 708, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #708 = V6_vsubuhsat_alt
4339 { 709, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #709 = V6_vsubuhsat_dv_alt
4340 { 710, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #710 = V6_vsubuhw_alt
4341 { 711, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #711 = V6_vsubuwsat_alt
4342 { 712, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #712 = V6_vsubuwsat_dv_alt
4343 { 713, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #713 = V6_vsubw_alt
4344 { 714, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #714 = V6_vsubw_dv_alt
4345 { 715, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #715 = V6_vsubwnq_alt
4346 { 716, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #716 = V6_vsubwq_alt
4347 { 717, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #717 = V6_vsubwsat_alt
4348 { 718, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #718 = V6_vsubwsat_dv_alt
4349 { 719, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #719 = V6_vtmpyb_acc_alt
4350 { 720, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #720 = V6_vtmpyb_alt
4351 { 721, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #721 = V6_vtmpybus_acc_alt
4352 { 722, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #722 = V6_vtmpybus_alt
4353 { 723, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #723 = V6_vtmpyhb_acc_alt
4354 { 724, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #724 = V6_vtmpyhb_alt
4355 { 725, 5, 2, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x30000000008027ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #725 = V6_vtran2x2_map
4356 { 726, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #726 = V6_vunpackb_alt
4357 { 727, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #727 = V6_vunpackh_alt
4358 { 728, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #728 = V6_vunpackob_alt
4359 { 729, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000008027ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #729 = V6_vunpackoh_alt
4360 { 730, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #730 = V6_vunpackub_alt
4361 { 731, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #731 = V6_vunpackuh_alt
4362 { 732, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #732 = V6_vzb_alt
4363 { 733, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #733 = V6_vzh_alt
4364 { 734, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #734 = V6_zld0
4365 { 735, 2, 0, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #735 = V6_zldp0
4366 { 736, 1, 0, 4, 64, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x27ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #736 = Y2_dcfetch
gen/lib/Target/Lanai/LanaiGenInstrInfo.inc 370 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
371 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
372 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
373 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
374 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
375 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
376 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
377 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
378 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
379 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
380 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
381 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
382 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
383 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
384 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
385 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
386 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
387 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
388 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
389 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
390 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
391 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
392 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
393 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
394 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
395 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
396 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
397 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
398 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
399 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
400 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
401 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
402 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
403 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
404 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
405 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
406 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
407 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
408 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
409 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
410 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
411 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
412 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
413 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
414 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
415 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
416 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
417 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
418 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
419 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
420 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
421 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
422 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
423 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
424 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
425 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
426 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
427 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
428 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
429 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
430 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
431 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
432 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
433 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
434 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
435 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
436 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
437 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
438 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
439 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
440 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
441 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
442 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
443 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
444 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
445 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
446 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
447 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
448 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
449 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
450 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
451 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
452 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
453 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
454 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
455 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
456 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
457 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
458 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
459 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
460 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
461 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
462 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
463 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
464 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
465 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
466 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
467 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
468 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
469 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
470 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
471 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
472 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
473 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
474 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
475 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
476 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
477 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
478 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
479 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
480 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
481 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
482 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
483 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
484 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
485 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
486 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
487 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
488 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
489 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
490 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
491 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
492 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
493 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
494 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
495 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
496 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
497 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
498 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
499 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
500 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
501 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
502 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
503 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
504 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
505 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
506 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
507 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
508 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
509 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
510 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
511 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
512 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
513 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
514 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
515 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
516 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
517 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
518 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
519 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
520 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
521 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
522 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
523 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
524 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
525 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
526 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
527 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
528 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
529 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
530 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
531 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
532 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
533 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
534 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
535 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
536 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
537 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
538 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
539 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
540 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
541 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
542 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
543 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
544 { 174, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
545 { 175, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
546 { 176, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #176 = ADJDYNALLOC
547 { 177, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #177 = CALL
548 { 178, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo37, -1 ,nullptr }, // Inst #178 = CALLR
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 641 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
642 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
643 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
644 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
645 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
646 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
647 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
648 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
649 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
650 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
651 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
652 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
653 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
654 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
655 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
656 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
657 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
658 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
659 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
660 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
661 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
662 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
663 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
664 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
665 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
666 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
667 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
668 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
669 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
670 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
671 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
672 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
673 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
674 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
675 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
676 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
677 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
678 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
679 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
680 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
681 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
682 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
683 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
684 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
685 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
686 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
687 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
688 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
689 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
690 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
691 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
692 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
693 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
694 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
695 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
696 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
697 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
698 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
699 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
700 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
701 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
702 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
703 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
704 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
705 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
706 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
707 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
708 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
709 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
710 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
711 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
712 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
713 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
714 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
715 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
716 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
717 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
718 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
719 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
720 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
721 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
722 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
723 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
724 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
725 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
726 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
727 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
728 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
729 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
730 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
731 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
732 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
733 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
734 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
735 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
736 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
737 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
738 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
739 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
740 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
741 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
742 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
743 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
744 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
745 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
746 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
747 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
748 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
749 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
750 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
751 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
752 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
753 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
754 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
755 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
756 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
757 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
758 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
759 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
760 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
761 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
762 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
763 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
764 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
765 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
766 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
767 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
768 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
769 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
770 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
771 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
772 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
773 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
774 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
775 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
776 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
777 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
778 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
779 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
780 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
781 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
782 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
783 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
784 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
785 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
786 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
787 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
788 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
789 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
790 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
791 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
792 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
793 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
794 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
795 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
796 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
797 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
798 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
799 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
800 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
801 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
802 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
803 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
804 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
805 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
806 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
807 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
808 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
809 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
810 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
811 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
812 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
813 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
814 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4815 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
4816 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
4817 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
4818 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
4819 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
4820 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
4821 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
4822 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
4823 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
4824 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
4825 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
4826 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
4827 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
4828 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
4829 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
4830 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
4831 { 16, 2, 1, 0, 509, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
4832 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
4833 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
4834 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
4835 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
4836 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
4837 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
4838 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
4839 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
4840 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
4841 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
4842 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
4843 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
4844 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
4845 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
4846 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
4847 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
4848 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
4849 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
4850 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
4851 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
4852 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
4853 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
4854 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
4855 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
4856 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
4857 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
4858 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
4859 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
4860 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
4861 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
4862 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
4863 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
4864 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
4865 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
4866 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
4867 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
4868 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
4869 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
4870 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
4871 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
4872 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
4873 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
4874 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
4875 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
4876 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
4877 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
4878 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
4879 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
4880 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
4881 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
4882 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
4883 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
4884 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4885 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
4886 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
4887 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
4888 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
4889 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
4890 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
4891 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
4892 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
4893 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
4894 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
4895 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
4896 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
4897 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
4898 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
4899 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
4900 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
4901 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
4902 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
4903 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
4904 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
4905 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
4906 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
4907 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
4908 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
4909 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
4910 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
4911 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
4912 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
4913 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
4914 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
4915 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
4916 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
4917 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
4918 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
4919 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
4920 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
4921 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
4922 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
4923 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
4924 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
4925 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
4926 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
4927 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
4928 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
4929 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
4930 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
4931 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
4932 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
4933 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
4934 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
4935 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
4936 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
4937 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
4938 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
4939 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
4940 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
4941 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
4942 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
4943 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
4944 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
4945 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
4946 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
4947 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
4948 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
4949 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
4950 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
4951 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
4952 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
4953 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
4954 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
4955 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
4956 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
4957 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
4958 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
4959 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
4960 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
4961 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
4962 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
4963 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
4964 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
4965 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
4966 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
4967 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
4968 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
4969 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
4970 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
4971 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
4972 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
4973 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
4974 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
4975 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
4976 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
4977 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
4978 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
4979 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
4980 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
4981 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
4982 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
4983 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
4984 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
4985 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
4986 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
4987 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
4988 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
4989 { 174, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = ABSMacro
4990 { 175, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKDOWN
4991 { 176, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #176 = ADJCALLSTACKUP
4992 { 177, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #177 = AND_V_D_PSEUDO
4993 { 178, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = AND_V_H_PSEUDO
4994 { 179, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = AND_V_W_PSEUDO
4995 { 180, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #180 = ATOMIC_CMP_SWAP_I16
4996 { 181, 7, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #181 = ATOMIC_CMP_SWAP_I16_POSTRA
4997 { 182, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #182 = ATOMIC_CMP_SWAP_I32
4998 { 183, 4, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #183 = ATOMIC_CMP_SWAP_I32_POSTRA
4999 { 184, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #184 = ATOMIC_CMP_SWAP_I64
5000 { 185, 4, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #185 = ATOMIC_CMP_SWAP_I64_POSTRA
5001 { 186, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #186 = ATOMIC_CMP_SWAP_I8
5002 { 187, 7, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #187 = ATOMIC_CMP_SWAP_I8_POSTRA
5003 { 188, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #188 = ATOMIC_LOAD_ADD_I16
5004 { 189, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #189 = ATOMIC_LOAD_ADD_I16_POSTRA
5005 { 190, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #190 = ATOMIC_LOAD_ADD_I32
5006 { 191, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #191 = ATOMIC_LOAD_ADD_I32_POSTRA
5007 { 192, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #192 = ATOMIC_LOAD_ADD_I64
5008 { 193, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = ATOMIC_LOAD_ADD_I64_POSTRA
5009 { 194, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #194 = ATOMIC_LOAD_ADD_I8
5010 { 195, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #195 = ATOMIC_LOAD_ADD_I8_POSTRA
5011 { 196, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #196 = ATOMIC_LOAD_AND_I16
5012 { 197, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #197 = ATOMIC_LOAD_AND_I16_POSTRA
5013 { 198, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #198 = ATOMIC_LOAD_AND_I32
5014 { 199, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #199 = ATOMIC_LOAD_AND_I32_POSTRA
5015 { 200, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #200 = ATOMIC_LOAD_AND_I64
5016 { 201, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #201 = ATOMIC_LOAD_AND_I64_POSTRA
5017 { 202, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #202 = ATOMIC_LOAD_AND_I8
5018 { 203, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #203 = ATOMIC_LOAD_AND_I8_POSTRA
5019 { 204, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #204 = ATOMIC_LOAD_NAND_I16
5020 { 205, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #205 = ATOMIC_LOAD_NAND_I16_POSTRA
5021 { 206, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #206 = ATOMIC_LOAD_NAND_I32
5022 { 207, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #207 = ATOMIC_LOAD_NAND_I32_POSTRA
5023 { 208, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #208 = ATOMIC_LOAD_NAND_I64
5024 { 209, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #209 = ATOMIC_LOAD_NAND_I64_POSTRA
5025 { 210, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #210 = ATOMIC_LOAD_NAND_I8
5026 { 211, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #211 = ATOMIC_LOAD_NAND_I8_POSTRA
5027 { 212, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #212 = ATOMIC_LOAD_OR_I16
5028 { 213, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #213 = ATOMIC_LOAD_OR_I16_POSTRA
5029 { 214, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #214 = ATOMIC_LOAD_OR_I32
5030 { 215, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #215 = ATOMIC_LOAD_OR_I32_POSTRA
5031 { 216, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #216 = ATOMIC_LOAD_OR_I64
5032 { 217, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #217 = ATOMIC_LOAD_OR_I64_POSTRA
5033 { 218, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #218 = ATOMIC_LOAD_OR_I8
5034 { 219, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #219 = ATOMIC_LOAD_OR_I8_POSTRA
5035 { 220, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #220 = ATOMIC_LOAD_SUB_I16
5036 { 221, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #221 = ATOMIC_LOAD_SUB_I16_POSTRA
5037 { 222, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #222 = ATOMIC_LOAD_SUB_I32
5038 { 223, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #223 = ATOMIC_LOAD_SUB_I32_POSTRA
5039 { 224, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #224 = ATOMIC_LOAD_SUB_I64
5040 { 225, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #225 = ATOMIC_LOAD_SUB_I64_POSTRA
5041 { 226, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #226 = ATOMIC_LOAD_SUB_I8
5042 { 227, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #227 = ATOMIC_LOAD_SUB_I8_POSTRA
5043 { 228, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #228 = ATOMIC_LOAD_XOR_I16
5044 { 229, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #229 = ATOMIC_LOAD_XOR_I16_POSTRA
5045 { 230, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #230 = ATOMIC_LOAD_XOR_I32
5046 { 231, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #231 = ATOMIC_LOAD_XOR_I32_POSTRA
5047 { 232, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #232 = ATOMIC_LOAD_XOR_I64
5048 { 233, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #233 = ATOMIC_LOAD_XOR_I64_POSTRA
5049 { 234, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #234 = ATOMIC_LOAD_XOR_I8
5050 { 235, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #235 = ATOMIC_LOAD_XOR_I8_POSTRA
5051 { 236, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #236 = ATOMIC_SWAP_I16
5052 { 237, 6, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #237 = ATOMIC_SWAP_I16_POSTRA
5053 { 238, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #238 = ATOMIC_SWAP_I32
5054 { 239, 3, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #239 = ATOMIC_SWAP_I32_POSTRA
5055 { 240, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #240 = ATOMIC_SWAP_I64
5056 { 241, 3, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #241 = ATOMIC_SWAP_I64_POSTRA
5057 { 242, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #242 = ATOMIC_SWAP_I8
5058 { 243, 6, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #243 = ATOMIC_SWAP_I8_POSTRA
5059 { 244, 1, 0, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr }, // Inst #244 = B
5060 { 245, 1, 0, 4, 911, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #245 = BAL_BR
5061 { 246, 1, 0, 4, 938, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo46, -1 ,nullptr }, // Inst #246 = BAL_BR_MM
5062 { 247, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #247 = BEQLImmMacro
5063 { 248, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #248 = BGE
5064 { 249, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #249 = BGEImmMacro
5065 { 250, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #250 = BGEL
5066 { 251, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #251 = BGELImmMacro
5067 { 252, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #252 = BGEU
5068 { 253, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #253 = BGEUImmMacro
5069 { 254, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #254 = BGEUL
5070 { 255, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #255 = BGEULImmMacro
5071 { 256, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #256 = BGT
5072 { 257, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #257 = BGTImmMacro
5073 { 258, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #258 = BGTL
5074 { 259, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #259 = BGTLImmMacro
5075 { 260, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #260 = BGTU
5076 { 261, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #261 = BGTUImmMacro
5077 { 262, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #262 = BGTUL
5078 { 263, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #263 = BGTULImmMacro
5079 { 264, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #264 = BLE
5080 { 265, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #265 = BLEImmMacro
5081 { 266, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #266 = BLEL
5082 { 267, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #267 = BLELImmMacro
5083 { 268, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #268 = BLEU
5084 { 269, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #269 = BLEUImmMacro
5085 { 270, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #270 = BLEUL
5086 { 271, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #271 = BLEULImmMacro
5087 { 272, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #272 = BLT
5088 { 273, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #273 = BLTImmMacro
5089 { 274, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #274 = BLTL
5090 { 275, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #275 = BLTLImmMacro
5091 { 276, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #276 = BLTU
5092 { 277, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #277 = BLTUImmMacro
5093 { 278, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #278 = BLTUL
5094 { 279, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #279 = BLTULImmMacro
5095 { 280, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #280 = BNELImmMacro
5096 { 281, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #281 = BPOSGE32_PSEUDO
5097 { 282, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #282 = BSEL_D_PSEUDO
5098 { 283, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #283 = BSEL_FD_PSEUDO
5099 { 284, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #284 = BSEL_FW_PSEUDO
5100 { 285, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #285 = BSEL_H_PSEUDO
5101 { 286, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #286 = BSEL_W_PSEUDO
5102 { 287, 1, 0, 4, 937, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo46, -1 ,nullptr }, // Inst #287 = B_MM
5103 { 288, 1, 0, 4, 989, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #288 = B_MMR6_Pseudo
5104 { 289, 1, 0, 4, 948, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #289 = B_MM_Pseudo
5105 { 290, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #290 = BeqImm
5106 { 291, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #291 = BneImm
5107 { 292, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #292 = BteqzT8CmpX16
5108 { 293, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #293 = BteqzT8CmpiX16
5109 { 294, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #294 = BteqzT8SltX16
5110 { 295, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #295 = BteqzT8SltiX16
5111 { 296, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #296 = BteqzT8SltiuX16
5112 { 297, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #297 = BteqzT8SltuX16
5113 { 298, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #298 = BtnezT8CmpX16
5114 { 299, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #299 = BtnezT8CmpiX16
5115 { 300, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #300 = BtnezT8SltX16
5116 { 301, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #301 = BtnezT8SltiX16
5117 { 302, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #302 = BtnezT8SltiuX16
5118 { 303, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #303 = BtnezT8SltuX16
5119 { 304, 3, 1, 4, 678, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #304 = BuildPairF64
5120 { 305, 3, 1, 4, 678, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #305 = BuildPairF64_64
5121 { 306, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #306 = CFTC1
5122 { 307, 3, 0, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #307 = CONSTPOOL_ENTRY
5123 { 308, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #308 = COPY_FD_PSEUDO
5124 { 309, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #309 = COPY_FW_PSEUDO
5125 { 310, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #310 = CTTC1
5126 { 311, 1, 0, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #311 = Constant32
5127 { 312, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #312 = DMULImmMacro
5128 { 313, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #313 = DMULMacro
5129 { 314, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #314 = DMULOMacro
5130 { 315, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #315 = DMULOUMacro
5131 { 316, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #316 = DROL
5132 { 317, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #317 = DROLImm
5133 { 318, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #318 = DROR
5134 { 319, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #319 = DRORImm
5135 { 320, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #320 = DSDivIMacro
5136 { 321, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #321 = DSDivMacro
5137 { 322, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #322 = DSRemIMacro
5138 { 323, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #323 = DSRemMacro
5139 { 324, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #324 = DUDivIMacro
5140 { 325, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #325 = DUDivMacro
5141 { 326, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #326 = DURemIMacro
5142 { 327, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #327 = DURemMacro
5143 { 328, 0, 0, 4, 916, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #328 = ERet
5144 { 329, 3, 1, 4, 687, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #329 = ExtractElementF64
5145 { 330, 3, 1, 4, 687, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #330 = ExtractElementF64_64
5146 { 331, 2, 1, 4, 583, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #331 = FABS_D
5147 { 332, 2, 1, 4, 583, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #332 = FABS_W
5148 { 333, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #333 = FEXP2_D_1_PSEUDO
5149 { 334, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #334 = FEXP2_W_1_PSEUDO
5150 { 335, 2, 1, 4, 546, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #335 = FILL_FD_PSEUDO
5151 { 336, 2, 1, 4, 546, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #336 = FILL_FW_PSEUDO
5152 { 337, 4, 2, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #337 = GotPrologue16
5153 { 338, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #338 = INSERT_B_VIDX64_PSEUDO
5154 { 339, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #339 = INSERT_B_VIDX_PSEUDO
5155 { 340, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #340 = INSERT_D_VIDX64_PSEUDO
5156 { 341, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #341 = INSERT_D_VIDX_PSEUDO
5157 { 342, 4, 1, 4, 547, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #342 = INSERT_FD_PSEUDO
5158 { 343, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #343 = INSERT_FD_VIDX64_PSEUDO
5159 { 344, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #344 = INSERT_FD_VIDX_PSEUDO
5160 { 345, 4, 1, 4, 547, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #345 = INSERT_FW_PSEUDO
5161 { 346, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #346 = INSERT_FW_VIDX64_PSEUDO
5162 { 347, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #347 = INSERT_FW_VIDX_PSEUDO
5163 { 348, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #348 = INSERT_H_VIDX64_PSEUDO
5164 { 349, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #349 = INSERT_H_VIDX_PSEUDO
5165 { 350, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #350 = INSERT_W_VIDX64_PSEUDO
5166 { 351, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #351 = INSERT_W_VIDX_PSEUDO
5167 { 352, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo86, -1 ,nullptr }, // Inst #352 = JALR64Pseudo
5168 { 353, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo86, -1 ,nullptr }, // Inst #353 = JALRHB64Pseudo
5169 { 354, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #354 = JALRHBPseudo
5170 { 355, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo49, -1 ,nullptr }, // Inst #355 = JALRPseudo
5171 { 356, 1, 0, 4, 982, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #356 = JAL_MMR6
5172 { 357, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #357 = JalOneReg
5173 { 358, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #358 = JalTwoReg
5174 { 359, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #359 = LDMacro
5175 { 360, 3, 1, 4, 708, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #360 = LD_F16
5176 { 361, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #361 = LOAD_ACC128
5177 { 362, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #362 = LOAD_ACC64
5178 { 363, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #363 = LOAD_ACC64DSP
5179 { 364, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #364 = LOAD_CCOND_DSP
5180 { 365, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #365 = LONG_BRANCH_ADDiu
5181 { 366, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #366 = LONG_BRANCH_ADDiu2Op
5182 { 367, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #367 = LONG_BRANCH_DADDiu
5183 { 368, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #368 = LONG_BRANCH_DADDiu2Op
5184 { 369, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #369 = LONG_BRANCH_LUi
5185 { 370, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #370 = LONG_BRANCH_LUi2Op
5186 { 371, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #371 = LONG_BRANCH_LUi2Op_64
5187 { 372, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #372 = LWM_MM
5188 { 373, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #373 = LoadAddrImm32
5189 { 374, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #374 = LoadAddrImm64
5190 { 375, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #375 = LoadAddrReg32
5191 { 376, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #376 = LoadAddrReg64
5192 { 377, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #377 = LoadImm32
5193 { 378, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #378 = LoadImm64
5194 { 379, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #379 = LoadImmDoubleFGR
5195 { 380, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #380 = LoadImmDoubleFGR_32
5196 { 381, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #381 = LoadImmDoubleGPR
5197 { 382, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #382 = LoadImmSingleFGR
5198 { 383, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #383 = LoadImmSingleGPR
5199 { 384, 3, 1, 2, 729, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #384 = LwConstant32
5200 { 385, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #385 = MFTACX
5201 { 386, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #386 = MFTC0
5202 { 387, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #387 = MFTC1
5203 { 388, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #388 = MFTDSP
5204 { 389, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #389 = MFTGPR
5205 { 390, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #390 = MFTHC1
5206 { 391, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #391 = MFTHI
5207 { 392, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #392 = MFTLO
5208 { 393, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #393 = MIPSeh_return32
5209 { 394, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #394 = MIPSeh_return64
5210 { 395, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #395 = MSA_FP_EXTEND_D_PSEUDO
5211 { 396, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #396 = MSA_FP_EXTEND_W_PSEUDO
5212 { 397, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #397 = MSA_FP_ROUND_D_PSEUDO
5213 { 398, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #398 = MSA_FP_ROUND_W_PSEUDO
5214 { 399, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #399 = MTTACX
5215 { 400, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #400 = MTTC0
5216 { 401, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #401 = MTTC1
5217 { 402, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #402 = MTTDSP
5218 { 403, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #403 = MTTGPR
5219 { 404, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #404 = MTTHC1
5220 { 405, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #405 = MTTHI
5221 { 406, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #406 = MTTLO
5222 { 407, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #407 = MULImmMacro
5223 { 408, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #408 = MULOMacro
5224 { 409, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #409 = MULOUMacro
5225 { 410, 2, 0, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo119, -1 ,nullptr }, // Inst #410 = MultRxRy16
5226 { 411, 3, 1, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo120, -1 ,nullptr }, // Inst #411 = MultRxRyRz16
5227 { 412, 2, 0, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo119, -1 ,nullptr }, // Inst #412 = MultuRxRy16
5228 { 413, 3, 1, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo120, -1 ,nullptr }, // Inst #413 = MultuRxRyRz16
5229 { 414, 0, 0, 4, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #414 = NOP
5230 { 415, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #415 = NORImm
5231 { 416, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #416 = NORImm64
5232 { 417, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #417 = NOR_V_D_PSEUDO
5233 { 418, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #418 = NOR_V_H_PSEUDO
5234 { 419, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #419 = NOR_V_W_PSEUDO
5235 { 420, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #420 = OR_V_D_PSEUDO
5236 { 421, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #421 = OR_V_H_PSEUDO
5237 { 422, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #422 = OR_V_W_PSEUDO
5238 { 423, 3, 1, 4, 1446, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #423 = PseudoCMPU_EQ_QB
5239 { 424, 3, 1, 4, 1446, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #424 = PseudoCMPU_LE_QB
5240 { 425, 3, 1, 4, 1446, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #425 = PseudoCMPU_LT_QB
5241 { 426, 3, 1, 4, 1446, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #426 = PseudoCMP_EQ_PH
5242 { 427, 3, 1, 4, 1446, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #427 = PseudoCMP_LE_PH
5243 { 428, 3, 1, 4, 1446, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #428 = PseudoCMP_LT_PH
5244 { 429, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #429 = PseudoCVT_D32_W
5245 { 430, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #430 = PseudoCVT_D64_L
5246 { 431, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #431 = PseudoCVT_D64_W
5247 { 432, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #432 = PseudoCVT_S_L
5248 { 433, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #433 = PseudoCVT_S_W
5249 { 434, 3, 1, 4, 894, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #434 = PseudoDMULT
5250 { 435, 3, 1, 4, 895, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #435 = PseudoDMULTu
5251 { 436, 3, 1, 4, 896, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #436 = PseudoDSDIV
5252 { 437, 3, 1, 4, 897, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #437 = PseudoDUDIV
5253 { 438, 7, 2, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #438 = PseudoD_SELECT_I
5254 { 439, 7, 2, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #439 = PseudoD_SELECT_I64
5255 { 440, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #440 = PseudoIndirectBranch
5256 { 441, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #441 = PseudoIndirectBranch64
5257 { 442, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #442 = PseudoIndirectBranch64R6
5258 { 443, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #443 = PseudoIndirectBranchR6
5259 { 444, 1, 0, 4, 957, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #444 = PseudoIndirectBranch_MM
5260 { 445, 1, 0, 4, 990, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #445 = PseudoIndirectBranch_MMR6
5261 { 446, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #446 = PseudoIndirectHazardBranch
5262 { 447, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #447 = PseudoIndirectHazardBranch64
5263 { 448, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #448 = PseudoIndrectHazardBranch64R6
5264 { 449, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #449 = PseudoIndrectHazardBranchR6
5265 { 450, 4, 1, 4, 484, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #450 = PseudoMADD
5266 { 451, 4, 1, 4, 485, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #451 = PseudoMADDU
5267 { 452, 4, 1, 4, 850, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #452 = PseudoMADDU_MM
5268 { 453, 4, 1, 4, 849, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #453 = PseudoMADD_MM
5269 { 454, 2, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #454 = PseudoMFHI
5270 { 455, 2, 1, 4, 898, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #455 = PseudoMFHI64
5271 { 456, 2, 1, 4, 859, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #456 = PseudoMFHI_MM
5272 { 457, 2, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #457 = PseudoMFLO
5273 { 458, 2, 1, 4, 898, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #458 = PseudoMFLO64
5274 { 459, 2, 1, 4, 859, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #459 = PseudoMFLO_MM
5275 { 460, 4, 1, 4, 486, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #460 = PseudoMSUB
5276 { 461, 4, 1, 4, 487, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #461 = PseudoMSUBU
5277 { 462, 4, 1, 4, 852, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #462 = PseudoMSUBU_MM
5278 { 463, 4, 1, 4, 851, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #463 = PseudoMSUB_MM
5279 { 464, 3, 1, 4, 488, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #464 = PseudoMTLOHI
5280 { 465, 3, 1, 4, 899, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #465 = PseudoMTLOHI64
5281 { 466, 3, 1, 4, 1332, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #466 = PseudoMTLOHI_DSP
5282 { 467, 3, 1, 4, 860, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #467 = PseudoMTLOHI_MM
5283 { 468, 3, 1, 4, 855, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #468 = PseudoMULT
5284 { 469, 3, 1, 4, 853, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #469 = PseudoMULT_MM
5285 { 470, 3, 1, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #470 = PseudoMULTu
5286 { 471, 3, 1, 4, 854, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #471 = PseudoMULTu_MM
5287 { 472, 4, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #472 = PseudoPICK_PH
5288 { 473, 4, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #473 = PseudoPICK_QB
5289 { 474, 1, 0, 4, 383, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #474 = PseudoReturn
5290 { 475, 1, 0, 4, 1008, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #475 = PseudoReturn64
5291 { 476, 3, 1, 4, 857, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #476 = PseudoSDIV
5292 { 477, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #477 = PseudoSELECTFP_F_D32
5293 { 478, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #478 = PseudoSELECTFP_F_D64
5294 { 479, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #479 = PseudoSELECTFP_F_I
5295 { 480, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #480 = PseudoSELECTFP_F_I64
5296 { 481, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #481 = PseudoSELECTFP_F_S
5297 { 482, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #482 = PseudoSELECTFP_T_D32
5298 { 483, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #483 = PseudoSELECTFP_T_D64
5299 { 484, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #484 = PseudoSELECTFP_T_I
5300 { 485, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #485 = PseudoSELECTFP_T_I64
5301 { 486, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #486 = PseudoSELECTFP_T_S
5302 { 487, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #487 = PseudoSELECT_D32
5303 { 488, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #488 = PseudoSELECT_D64
5304 { 489, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #489 = PseudoSELECT_I
5305 { 490, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #490 = PseudoSELECT_I64
5306 { 491, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #491 = PseudoSELECT_S
5307 { 492, 3, 1, 4, 1202, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #492 = PseudoTRUNC_W_D
5308 { 493, 3, 1, 4, 1202, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #493 = PseudoTRUNC_W_D32
5309 { 494, 3, 1, 4, 1202, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #494 = PseudoTRUNC_W_S
5310 { 495, 3, 1, 4, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #495 = PseudoUDIV
5311 { 496, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #496 = ROL
5312 { 497, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #497 = ROLImm
5313 { 498, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #498 = ROR
5314 { 499, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #499 = RORImm
5315 { 500, 0, 0, 4, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #500 = RetRA
5316 { 501, 0, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #501 = RetRA16
5317 { 502, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #502 = SDC1_M1
5318 { 503, 3, 1, 4, 877, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #503 = SDIV_MM_Pseudo
5319 { 504, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #504 = SDMacro
5320 { 505, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #505 = SDivIMacro
5321 { 506, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #506 = SDivMacro
5322 { 507, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #507 = SEQIMacro
5323 { 508, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #508 = SEQMacro
5324 { 509, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #509 = SGE
5325 { 510, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #510 = SGEImm
5326 { 511, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #511 = SGEImm64
5327 { 512, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #512 = SGEU
5328 { 513, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #513 = SGEUImm
5329 { 514, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #514 = SGEUImm64
5330 { 515, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #515 = SGTImm
5331 { 516, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #516 = SGTImm64
5332 { 517, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #517 = SGTUImm
5333 { 518, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #518 = SGTUImm64
5334 { 519, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #519 = SLTImm64
5335 { 520, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #520 = SLTUImm64
5336 { 521, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #521 = SNZ_B_PSEUDO
5337 { 522, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #522 = SNZ_D_PSEUDO
5338 { 523, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #523 = SNZ_H_PSEUDO
5339 { 524, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #524 = SNZ_V_PSEUDO
5340 { 525, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #525 = SNZ_W_PSEUDO
5341 { 526, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #526 = SRemIMacro
5342 { 527, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #527 = SRemMacro
5343 { 528, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #528 = STORE_ACC128
5344 { 529, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #529 = STORE_ACC64
5345 { 530, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #530 = STORE_ACC64DSP
5346 { 531, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #531 = STORE_CCOND_DSP
5347 { 532, 3, 0, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #532 = ST_F16
5348 { 533, 3, 0, 4, 1128, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #533 = SWM_MM
5349 { 534, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #534 = SZ_B_PSEUDO
5350 { 535, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #535 = SZ_D_PSEUDO
5351 { 536, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #536 = SZ_H_PSEUDO
5352 { 537, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #537 = SZ_V_PSEUDO
5353 { 538, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #538 = SZ_W_PSEUDO
5354 { 539, 4, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #539 = SelBeqZ
5355 { 540, 4, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #540 = SelBneZ
5356 { 541, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #541 = SelTBteqZCmp
5357 { 542, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #542 = SelTBteqZCmpi
5358 { 543, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #543 = SelTBteqZSlt
5359 { 544, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #544 = SelTBteqZSlti
5360 { 545, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #545 = SelTBteqZSltiu
5361 { 546, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #546 = SelTBteqZSltu
5362 { 547, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #547 = SelTBtneZCmp
5363 { 548, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #548 = SelTBtneZCmpi
5364 { 549, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #549 = SelTBtneZSlt
5365 { 550, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #550 = SelTBtneZSlti
5366 { 551, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #551 = SelTBtneZSltiu
5367 { 552, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #552 = SelTBtneZSltu
5368 { 553, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #553 = SltCCRxRy16
5369 { 554, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #554 = SltiCCRxImmX16
5370 { 555, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #555 = SltiuCCRxImmX16
5371 { 556, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #556 = SltuCCRxRy16
5372 { 557, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo120, -1 ,nullptr }, // Inst #557 = SltuRxRyRz16
5373 { 558, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #558 = TAILCALL
5374 { 559, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #559 = TAILCALL64R6REG
5375 { 560, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #560 = TAILCALLHB64R6REG
5376 { 561, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #561 = TAILCALLHBR6REG
5377 { 562, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #562 = TAILCALLR6REG
5378 { 563, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #563 = TAILCALLREG
5379 { 564, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #564 = TAILCALLREG64
5380 { 565, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #565 = TAILCALLREGHB
5381 { 566, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #566 = TAILCALLREGHB64
5382 { 567, 1, 0, 4, 955, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #567 = TAILCALLREG_MM
5383 { 568, 1, 0, 4, 997, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #568 = TAILCALLREG_MMR6
5384 { 569, 1, 0, 4, 956, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #569 = TAILCALL_MM
5385 { 570, 1, 0, 4, 998, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #570 = TAILCALL_MMR6
5386 { 571, 0, 0, 4, 397, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #571 = TRAP
5387 { 572, 0, 0, 4, 973, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #572 = TRAP_MM
5388 { 573, 3, 1, 4, 878, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #573 = UDIV_MM_Pseudo
5389 { 574, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #574 = UDivIMacro
5390 { 575, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #575 = UDivMacro
5391 { 576, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #576 = URemIMacro
5392 { 577, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #577 = URemMacro
5393 { 578, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #578 = Ulh
5394 { 579, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #579 = Ulhu
5395 { 580, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #580 = Ulw
5396 { 581, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #581 = Ush
5397 { 582, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #582 = Usw
5398 { 583, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #583 = XOR_V_D_PSEUDO
5399 { 584, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #584 = XOR_V_H_PSEUDO
5400 { 585, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #585 = XOR_V_W_PSEUDO
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 6631 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
6632 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
6633 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
6634 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
6635 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
6636 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
6637 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
6638 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
6639 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
6640 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
6641 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
6642 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
6643 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
6644 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
6645 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
6646 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
6647 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
6648 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
6649 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
6650 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
6651 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
6652 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
6653 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
6654 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
6655 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
6656 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
6657 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
6658 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
6659 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
6660 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
6661 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
6662 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
6663 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
6664 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
6665 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
6666 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
6667 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
6668 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
6669 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
6670 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
6671 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
6672 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
6673 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
6674 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
6675 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
6676 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
6677 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
6678 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
6679 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
6680 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
6681 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
6682 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
6683 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
6684 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
6685 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
6686 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
6687 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
6688 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
6689 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
6690 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
6691 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
6692 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
6693 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
6694 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
6695 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
6696 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
6697 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
6698 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
6699 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
6700 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
6701 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
6702 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
6703 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
6704 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
6705 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
6706 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
6707 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
6708 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
6709 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
6710 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
6711 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
6712 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
6713 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
6714 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
6715 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
6716 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
6717 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
6718 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
6719 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
6720 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
6721 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
6722 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
6723 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
6724 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
6725 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
6726 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
6727 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
6728 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
6729 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
6730 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
6731 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
6732 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
6733 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
6734 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
6735 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
6736 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
6737 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
6738 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
6739 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
6740 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
6741 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
6742 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
6743 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
6744 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
6745 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
6746 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
6747 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
6748 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
6749 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
6750 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
6751 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
6752 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
6753 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
6754 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
6755 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
6756 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
6757 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
6758 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
6759 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
6760 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
6761 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
6762 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
6763 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
6764 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
6765 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
6766 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
6767 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
6768 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
6769 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
6770 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
6771 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
6772 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
6773 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
6774 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
6775 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
6776 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
6777 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
6778 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
6779 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
6780 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
6781 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
6782 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
6783 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
6784 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
6785 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
6786 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
6787 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
6788 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
6789 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
6790 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
6791 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
6792 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
6793 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
6794 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
6795 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
6796 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
6797 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
6798 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
6799 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
6800 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
6801 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
6802 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
6803 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
6804 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
6805 { 174, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = ProxyRegF16
6806 { 175, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #175 = ProxyRegF16x2
6807 { 176, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #176 = ProxyRegF32
6808 { 177, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #177 = ProxyRegF64
6809 { 178, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #178 = ProxyRegI1
6810 { 179, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #179 = ProxyRegI16
6811 { 180, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #180 = ProxyRegI32
6812 { 181, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #181 = ProxyRegI64
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2908 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
2909 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
2910 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
2911 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
2912 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
2913 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
2914 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
2915 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
2916 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
2917 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
2918 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
2919 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
2920 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
2921 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
2922 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
2923 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
2924 { 16, 2, 1, 0, 117, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
2925 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
2926 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
2927 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
2928 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
2929 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
2930 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
2931 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
2932 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
2933 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
2934 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
2935 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
2936 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
2937 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
2938 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
2939 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
2940 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
2941 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
2942 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
2943 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
2944 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
2945 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
2946 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
2947 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
2948 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
2949 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
2950 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
2951 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
2952 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
2953 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
2954 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
2955 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
2956 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
2957 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
2958 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
2959 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
2960 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
2961 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
2962 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
2963 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
2964 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
2965 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
2966 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
2967 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
2968 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
2969 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
2970 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
2971 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
2972 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
2973 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
2974 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
2975 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
2976 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
2977 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
2978 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
2979 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
2980 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
2981 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
2982 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
2983 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
2984 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
2985 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
2986 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
2987 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
2988 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
2989 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
2990 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
2991 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
2992 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
2993 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
2994 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
2995 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
2996 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
2997 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
2998 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
2999 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
3000 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
3001 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
3002 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
3003 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
3004 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
3005 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
3006 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
3007 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
3008 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
3009 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
3010 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
3011 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
3012 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
3013 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
3014 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
3015 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
3016 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
3017 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
3018 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
3019 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
3020 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
3021 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
3022 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
3023 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
3024 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
3025 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
3026 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
3027 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
3028 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
3029 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
3030 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
3031 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
3032 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
3033 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
3034 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
3035 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
3036 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
3037 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
3038 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
3039 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
3040 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
3041 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
3042 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
3043 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
3044 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
3045 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
3046 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
3047 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
3048 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
3049 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
3050 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
3051 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
3052 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
3053 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
3054 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
3055 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
3056 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
3057 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
3058 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
3059 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
3060 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
3061 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
3062 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
3063 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
3064 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
3065 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
3066 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
3067 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
3068 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
3069 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
3070 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
3071 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
3072 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
3073 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
3074 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
3075 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
3076 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
3077 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
3078 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
3079 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
3080 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
3081 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
3082 { 174, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = CFENCE8
3083 { 175, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #175 = CLRLSLDI
3084 { 176, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #176 = CLRLSLDIo
3085 { 177, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #177 = CLRLSLWI
3086 { 178, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = CLRLSLWIo
3087 { 179, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = CLRRDI
3088 { 180, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = CLRRDIo
3089 { 181, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #181 = CLRRWI
3090 { 182, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #182 = CLRRWIo
3091 { 183, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #183 = CP_COPY_FIRST
3092 { 184, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #184 = CP_COPYx
3093 { 185, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #185 = CP_PASTE_LAST
3094 { 186, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #186 = CP_PASTEx
3095 { 187, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #187 = DCBFL
3096 { 188, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #188 = DCBFLP
3097 { 189, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #189 = DCBFx
3098 { 190, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #190 = DCBTCT
3099 { 191, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #191 = DCBTDS
3100 { 192, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #192 = DCBTSTCT
3101 { 193, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #193 = DCBTSTDS
3102 { 194, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #194 = DCBTSTT
3103 { 195, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #195 = DCBTSTx
3104 { 196, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #196 = DCBTT
3105 { 197, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #197 = DCBTx
3106 { 198, 3, 1, 4, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #198 = DFLOADf32
3107 { 199, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #199 = DFLOADf64
3108 { 200, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #200 = DFSTOREf32
3109 { 201, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #201 = DFSTOREf64
3110 { 202, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #202 = EXTLDI
3111 { 203, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #203 = EXTLDIo
3112 { 204, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #204 = EXTLWI
3113 { 205, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #205 = EXTLWIo
3114 { 206, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #206 = EXTRDI
3115 { 207, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #207 = EXTRDIo
3116 { 208, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #208 = EXTRWI
3117 { 209, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #209 = EXTRWIo
3118 { 210, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #210 = INSLWI
3119 { 211, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #211 = INSLWIo
3120 { 212, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #212 = INSRDI
3121 { 213, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #213 = INSRDIo
3122 { 214, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #214 = INSRWI
3123 { 215, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #215 = INSRWIo
3124 { 216, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #216 = LAx
3125 { 217, 3, 1, 4, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #217 = LIWAX
3126 { 218, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #218 = LIWZX
3127 { 219, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #219 = RLWIMIbm
3128 { 220, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #220 = RLWIMIobm
3129 { 221, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #221 = RLWINMbm
3130 { 222, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #222 = RLWINMobm
3131 { 223, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #223 = RLWNMbm
3132 { 224, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #224 = RLWNMobm
3133 { 225, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #225 = ROTRDI
3134 { 226, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #226 = ROTRDIo
3135 { 227, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #227 = ROTRWI
3136 { 228, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #228 = ROTRWIo
3137 { 229, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #229 = SLDI
3138 { 230, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #230 = SLDIo
3139 { 231, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #231 = SLWI
3140 { 232, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #232 = SLWIo
3141 { 233, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #233 = SPILLTOVSR_LD
3142 { 234, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #234 = SPILLTOVSR_LDX
3143 { 235, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #235 = SPILLTOVSR_ST
3144 { 236, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #236 = SPILLTOVSR_STX
3145 { 237, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #237 = SRDI
3146 { 238, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #238 = SRDIo
3147 { 239, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #239 = SRWI
3148 { 240, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #240 = SRWIo
3149 { 241, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #241 = STIWX
3150 { 242, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #242 = SUBI
3151 { 243, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #243 = SUBIC
3152 { 244, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #244 = SUBICo
3153 { 245, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #245 = SUBIS
3154 { 246, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #246 = SUBPCIS
3155 { 247, 3, 1, 4, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #247 = XFLOADf32
3156 { 248, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #248 = XFLOADf64
3157 { 249, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #249 = XFSTOREf32
3158 { 250, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList2, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #250 = XFSTOREf64
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 662 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
663 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
664 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
665 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
666 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
667 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
668 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
669 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
670 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
671 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
672 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
673 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
674 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
675 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
676 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
677 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
678 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
679 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
680 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
681 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
682 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
683 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
684 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
685 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
686 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
687 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
688 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
689 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
690 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
691 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
692 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
693 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
694 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
695 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
696 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
697 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
698 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
699 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
700 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
701 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
702 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
703 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
704 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
705 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
706 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
707 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
708 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
709 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
710 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
711 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
712 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
713 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
714 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
715 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
716 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
717 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
718 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
719 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
720 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
721 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
722 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
723 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
724 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
725 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
726 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
727 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
728 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
729 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
730 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
731 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
732 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
733 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
734 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
735 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
736 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
737 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
738 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
739 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
740 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
741 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
742 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
743 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
744 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
745 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
746 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
747 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
748 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
749 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
750 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
751 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
752 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
753 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
754 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
755 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
756 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
757 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
758 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
759 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
760 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
761 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
762 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
763 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
764 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
765 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
766 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
767 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
768 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
769 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
770 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
771 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
772 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
773 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
774 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
775 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
776 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
777 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
778 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
779 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
780 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
781 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
782 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
783 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
784 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
785 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
786 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
787 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
788 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
789 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
790 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
791 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
792 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
793 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
794 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
795 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
796 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
797 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
798 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
799 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
800 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
801 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
802 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
803 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
804 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
805 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
806 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
807 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
808 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
809 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
810 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
811 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
812 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
813 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
814 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
815 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
816 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
817 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
818 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
819 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
820 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
821 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
822 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
823 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
824 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
825 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
826 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
827 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
828 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
829 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
830 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
831 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
832 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
833 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
834 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
835 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
836 { 174, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
837 { 175, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
838 { 176, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BuildPairF64Pseudo
839 { 177, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #177 = PseudoAddTPRel
840 { 178, 5, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = PseudoAtomicLoadNand32
841 { 179, 5, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #179 = PseudoAtomicLoadNand64
842 { 180, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = PseudoBR
843 { 181, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList2, OperandInfo40, -1 ,nullptr }, // Inst #181 = PseudoBRIND
844 { 182, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #182 = PseudoCALL
845 { 183, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #183 = PseudoCALLIndirect
846 { 184, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #184 = PseudoCALLReg
847 { 185, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #185 = PseudoCmpXchg32
848 { 186, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #186 = PseudoCmpXchg64
849 { 187, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #187 = PseudoFLD
850 { 188, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #188 = PseudoFLW
851 { 189, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #189 = PseudoFSD
852 { 190, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #190 = PseudoFSW
853 { 191, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #191 = PseudoLA
854 { 192, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #192 = PseudoLA_TLS_GD
855 { 193, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #193 = PseudoLA_TLS_IE
856 { 194, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #194 = PseudoLB
857 { 195, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #195 = PseudoLBU
858 { 196, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #196 = PseudoLD
859 { 197, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #197 = PseudoLH
860 { 198, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #198 = PseudoLHU
861 { 199, 2, 1, 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #199 = PseudoLI
862 { 200, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #200 = PseudoLLA
863 { 201, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #201 = PseudoLW
864 { 202, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #202 = PseudoLWU
865 { 203, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #203 = PseudoMaskedAtomicLoadAdd32
866 { 204, 8, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #204 = PseudoMaskedAtomicLoadMax32
867 { 205, 8, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #205 = PseudoMaskedAtomicLoadMin32
868 { 206, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #206 = PseudoMaskedAtomicLoadNand32
869 { 207, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #207 = PseudoMaskedAtomicLoadSub32
870 { 208, 7, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #208 = PseudoMaskedAtomicLoadUMax32
871 { 209, 7, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #209 = PseudoMaskedAtomicLoadUMin32
872 { 210, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #210 = PseudoMaskedAtomicSwap32
873 { 211, 7, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #211 = PseudoMaskedCmpXchg32
874 { 212, 0, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #212 = PseudoRET
875 { 213, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #213 = PseudoSB
876 { 214, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #214 = PseudoSD
877 { 215, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #215 = PseudoSH
878 { 216, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #216 = PseudoSW
879 { 217, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #217 = PseudoTAIL
880 { 218, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #218 = PseudoTAILIndirect
881 { 219, 2, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #219 = ReadCycleWide
882 { 220, 6, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #220 = Select_FPR32_Using_CC_GPR
883 { 221, 6, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #221 = Select_FPR64_Using_CC_GPR
884 { 222, 6, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #222 = Select_GPR_Using_CC_GPR
885 { 223, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #223 = SplitF64Pseudo
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 930 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
931 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
932 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
933 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
934 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
935 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
936 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
937 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
938 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
939 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
940 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
941 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
942 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
943 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
944 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
945 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
946 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
947 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
948 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
949 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
950 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
951 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
952 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
953 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
954 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
955 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
956 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
957 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
958 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
959 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
960 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
961 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
962 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
963 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
964 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
965 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
966 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
967 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
968 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
969 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
970 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
971 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
972 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
973 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
974 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
975 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
976 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
977 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
978 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
979 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
980 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
981 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
982 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
983 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
984 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
985 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
986 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
987 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
988 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
989 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
990 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
991 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
992 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
993 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
994 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
995 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
996 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
997 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
998 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
999 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1000 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
1001 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
1002 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
1003 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
1004 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
1005 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
1006 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
1007 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
1008 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
1009 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
1010 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
1011 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
1012 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
1013 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
1014 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
1015 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
1016 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
1017 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
1018 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
1019 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
1020 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
1021 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
1022 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
1023 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
1024 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
1025 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
1026 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
1027 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
1028 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
1029 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
1030 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
1031 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
1032 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
1033 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
1034 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
1035 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
1036 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
1037 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
1038 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
1039 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
1040 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
1041 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
1042 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
1043 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
1044 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
1045 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
1046 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
1047 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
1048 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
1049 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
1050 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
1051 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
1052 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
1053 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
1054 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
1055 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
1056 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
1057 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
1058 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
1059 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
1060 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
1061 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
1062 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
1063 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
1064 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
1065 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
1066 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
1067 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
1068 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
1069 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
1070 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
1071 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
1072 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
1073 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
1074 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
1075 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
1076 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
1077 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
1078 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
1079 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
1080 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
1081 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
1082 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
1083 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
1084 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
1085 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
1086 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
1087 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
1088 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
1089 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
1090 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
1091 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
1092 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
1093 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
1094 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
1095 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
1096 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
1097 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
1098 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
1099 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
1100 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
1101 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
1102 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
1103 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
1104 { 174, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
1105 { 175, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
1106 { 176, 1, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #176 = GETPCX
1107 { 177, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #177 = SELECT_CC_DFP_FCC
1108 { 178, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #178 = SELECT_CC_DFP_ICC
1109 { 179, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #179 = SELECT_CC_FP_FCC
1110 { 180, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #180 = SELECT_CC_FP_ICC
1111 { 181, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #181 = SELECT_CC_Int_FCC
1112 { 182, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #182 = SELECT_CC_Int_ICC
1113 { 183, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #183 = SELECT_CC_QFP_FCC
1114 { 184, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #184 = SELECT_CC_QFP_ICC
1115 { 185, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #185 = SET
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4320 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
4321 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
4322 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
4323 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
4324 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
4325 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
4326 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
4327 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
4328 { 8, 3, 1, 0, 30, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
4329 { 9, 4, 1, 0, 31, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
4330 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
4331 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
4332 { 12, 3, 1, 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
4333 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
4334 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
4335 { 15, 2, 1, 0, 32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
4336 { 16, 2, 1, 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
4337 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
4338 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
4339 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
4340 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
4341 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
4342 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
4343 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
4344 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
4345 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
4346 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
4347 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
4348 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
4349 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
4350 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
4351 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
4352 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
4353 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
4354 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
4355 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
4356 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
4357 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
4358 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
4359 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
4360 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
4361 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
4362 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
4363 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
4364 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
4365 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
4366 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
4367 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
4368 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
4369 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
4370 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
4371 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
4372 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
4373 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
4374 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
4375 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
4376 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
4377 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
4378 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
4379 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
4380 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
4381 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
4382 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
4383 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
4384 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
4385 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
4386 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
4387 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
4388 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
4389 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4390 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
4391 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
4392 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
4393 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
4394 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
4395 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
4396 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
4397 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
4398 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
4399 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
4400 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
4401 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
4402 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
4403 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
4404 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
4405 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
4406 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
4407 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
4408 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
4409 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
4410 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
4411 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
4412 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
4413 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
4414 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
4415 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
4416 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
4417 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
4418 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
4419 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
4420 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
4421 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
4422 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
4423 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
4424 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
4425 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
4426 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
4427 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
4428 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
4429 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
4430 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
4431 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
4432 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
4433 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
4434 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
4435 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
4436 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
4437 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
4438 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
4439 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
4440 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
4441 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
4442 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
4443 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
4444 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
4445 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
4446 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
4447 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
4448 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
4449 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
4450 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
4451 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
4452 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
4453 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
4454 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
4455 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
4456 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
4457 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
4458 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
4459 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
4460 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
4461 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
4462 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
4463 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
4464 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
4465 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
4466 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
4467 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
4468 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
4469 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
4470 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
4471 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
4472 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
4473 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
4474 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
4475 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
4476 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
4477 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
4478 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
4479 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
4480 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
4481 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
4482 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
4483 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
4484 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
4485 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
4486 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
4487 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
4488 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
4489 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
4490 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
4491 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
4492 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
4493 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
4494 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
4495 { 175, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
4496 { 176, 4, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = ADJDYNALLOC
4497 { 177, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #177 = AEXT128
4498 { 178, 3, 1, 0, 106, 0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #178 = AFIMux
4499 { 179, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23d0cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #179 = AG_MemFoldPseudo
4500 { 180, 3, 1, 0, 112, 0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #180 = AHIMux
4501 { 181, 3, 1, 0, 112, 0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #181 = AHIMuxK
4502 { 182, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #182 = ALG_MemFoldPseudo
4503 { 183, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #183 = AL_MemFoldPseudo
4504 { 184, 8, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #184 = ATOMIC_CMP_SWAPW
4505 { 185, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #185 = ATOMIC_LOADW_AFI
4506 { 186, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #186 = ATOMIC_LOADW_AR
4507 { 187, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #187 = ATOMIC_LOADW_MAX
4508 { 188, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #188 = ATOMIC_LOADW_MIN
4509 { 189, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #189 = ATOMIC_LOADW_NILH
4510 { 190, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #190 = ATOMIC_LOADW_NILHi
4511 { 191, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #191 = ATOMIC_LOADW_NR
4512 { 192, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #192 = ATOMIC_LOADW_NRi
4513 { 193, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #193 = ATOMIC_LOADW_OILH
4514 { 194, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #194 = ATOMIC_LOADW_OR
4515 { 195, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #195 = ATOMIC_LOADW_SR
4516 { 196, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #196 = ATOMIC_LOADW_UMAX
4517 { 197, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #197 = ATOMIC_LOADW_UMIN
4518 { 198, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #198 = ATOMIC_LOADW_XILF
4519 { 199, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #199 = ATOMIC_LOADW_XR
4520 { 200, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #200 = ATOMIC_LOAD_AFI
4521 { 201, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #201 = ATOMIC_LOAD_AGFI
4522 { 202, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #202 = ATOMIC_LOAD_AGHI
4523 { 203, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #203 = ATOMIC_LOAD_AGR
4524 { 204, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #204 = ATOMIC_LOAD_AHI
4525 { 205, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #205 = ATOMIC_LOAD_AR
4526 { 206, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #206 = ATOMIC_LOAD_MAX_32
4527 { 207, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #207 = ATOMIC_LOAD_MAX_64
4528 { 208, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #208 = ATOMIC_LOAD_MIN_32
4529 { 209, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #209 = ATOMIC_LOAD_MIN_64
4530 { 210, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #210 = ATOMIC_LOAD_NGR
4531 { 211, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #211 = ATOMIC_LOAD_NGRi
4532 { 212, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #212 = ATOMIC_LOAD_NIHF64
4533 { 213, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #213 = ATOMIC_LOAD_NIHF64i
4534 { 214, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #214 = ATOMIC_LOAD_NIHH64
4535 { 215, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #215 = ATOMIC_LOAD_NIHH64i
4536 { 216, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #216 = ATOMIC_LOAD_NIHL64
4537 { 217, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #217 = ATOMIC_LOAD_NIHL64i
4538 { 218, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #218 = ATOMIC_LOAD_NILF
4539 { 219, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #219 = ATOMIC_LOAD_NILF64
4540 { 220, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #220 = ATOMIC_LOAD_NILF64i
4541 { 221, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #221 = ATOMIC_LOAD_NILFi
4542 { 222, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #222 = ATOMIC_LOAD_NILH
4543 { 223, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #223 = ATOMIC_LOAD_NILH64
4544 { 224, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #224 = ATOMIC_LOAD_NILH64i
4545 { 225, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #225 = ATOMIC_LOAD_NILHi
4546 { 226, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #226 = ATOMIC_LOAD_NILL
4547 { 227, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #227 = ATOMIC_LOAD_NILL64
4548 { 228, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #228 = ATOMIC_LOAD_NILL64i
4549 { 229, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #229 = ATOMIC_LOAD_NILLi
4550 { 230, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #230 = ATOMIC_LOAD_NR
4551 { 231, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #231 = ATOMIC_LOAD_NRi
4552 { 232, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #232 = ATOMIC_LOAD_OGR
4553 { 233, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #233 = ATOMIC_LOAD_OIHF64
4554 { 234, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #234 = ATOMIC_LOAD_OIHH64
4555 { 235, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #235 = ATOMIC_LOAD_OIHL64
4556 { 236, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #236 = ATOMIC_LOAD_OILF
4557 { 237, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #237 = ATOMIC_LOAD_OILF64
4558 { 238, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #238 = ATOMIC_LOAD_OILH
4559 { 239, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #239 = ATOMIC_LOAD_OILH64
4560 { 240, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #240 = ATOMIC_LOAD_OILL
4561 { 241, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #241 = ATOMIC_LOAD_OILL64
4562 { 242, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #242 = ATOMIC_LOAD_OR
4563 { 243, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #243 = ATOMIC_LOAD_SGR
4564 { 244, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #244 = ATOMIC_LOAD_SR
4565 { 245, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #245 = ATOMIC_LOAD_UMAX_32
4566 { 246, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #246 = ATOMIC_LOAD_UMAX_64
4567 { 247, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #247 = ATOMIC_LOAD_UMIN_32
4568 { 248, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #248 = ATOMIC_LOAD_UMIN_64
4569 { 249, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #249 = ATOMIC_LOAD_XGR
4570 { 250, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #250 = ATOMIC_LOAD_XIHF64
4571 { 251, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #251 = ATOMIC_LOAD_XILF
4572 { 252, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #252 = ATOMIC_LOAD_XILF64
4573 { 253, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #253 = ATOMIC_LOAD_XR
4574 { 254, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #254 = ATOMIC_SWAPW
4575 { 255, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #255 = ATOMIC_SWAP_32
4576 { 256, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #256 = ATOMIC_SWAP_64
4577 { 257, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23c88ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #257 = A_MemFoldPseudo
4578 { 258, 2, 0, 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #258 = CFIMux
4579 { 259, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #259 = CGIBCall
4580 { 260, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #260 = CGIBReturn
4581 { 261, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #261 = CGRBCall
4582 { 262, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #262 = CGRBReturn
4583 { 263, 2, 0, 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #263 = CHIMux
4584 { 264, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #264 = CIBCall
4585 { 265, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #265 = CIBReturn
4586 { 266, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr }, // Inst #266 = CLCLoop
4587 { 267, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr }, // Inst #267 = CLCSequence
4588 { 268, 2, 0, 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #268 = CLFIMux
4589 { 269, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #269 = CLGIBCall
4590 { 270, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #270 = CLGIBReturn
4591 { 271, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #271 = CLGRBCall
4592 { 272, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #272 = CLGRBReturn
4593 { 273, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #273 = CLIBCall
4594 { 274, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #274 = CLIBReturn
4595 { 275, 4, 0, 0, 227, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr }, // Inst #275 = CLMux
4596 { 276, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #276 = CLRBCall
4597 { 277, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #277 = CLRBReturn
4598 { 278, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr }, // Inst #278 = CLSTLoop
4599 { 279, 4, 0, 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr }, // Inst #279 = CMux
4600 { 280, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #280 = CRBCall
4601 { 281, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #281 = CRBReturn
4602 { 282, 1, 0, 2, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList3, ImplicitList4, OperandInfo58, -1 ,nullptr }, // Inst #282 = CallBASR
4603 { 283, 2, 0, 2, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #283 = CallBCR
4604 { 284, 0, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #284 = CallBR
4605 { 285, 1, 0, 6, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList3, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #285 = CallBRASL
4606 { 286, 3, 0, 6, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #286 = CallBRCL
4607 { 287, 1, 0, 6, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #287 = CallJG
4608 { 288, 2, 0, 2, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #288 = CondReturn
4609 { 289, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #289 = CondStore16
4610 { 290, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #290 = CondStore16Inv
4611 { 291, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #291 = CondStore16Mux
4612 { 292, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #292 = CondStore16MuxInv
4613 { 293, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #293 = CondStore32
4614 { 294, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #294 = CondStore32Inv
4615 { 295, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #295 = CondStore32Mux
4616 { 296, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #296 = CondStore32MuxInv
4617 { 297, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #297 = CondStore64
4618 { 298, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #298 = CondStore64Inv
4619 { 299, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #299 = CondStore8
4620 { 300, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #300 = CondStore8Inv
4621 { 301, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #301 = CondStore8Mux
4622 { 302, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #302 = CondStore8MuxInv
4623 { 303, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #303 = CondStoreF32
4624 { 304, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #304 = CondStoreF32Inv
4625 { 305, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #305 = CondStoreF64
4626 { 306, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #306 = CondStoreF64Inv
4627 { 307, 2, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #307 = CondTrap
4628 { 308, 1, 1, 6, 87, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #308 = GOT
4629 { 309, 2, 1, 0, 96, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #309 = IIFMux
4630 { 310, 3, 1, 6, 97, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #310 = IIHF64
4631 { 311, 3, 1, 4, 98, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #311 = IIHH64
4632 { 312, 3, 1, 4, 99, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #312 = IIHL64
4633 { 313, 3, 1, 0, 96, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #313 = IIHMux
4634 { 314, 3, 1, 6, 100, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #314 = IILF64
4635 { 315, 3, 1, 4, 101, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #315 = IILH64
4636 { 316, 3, 1, 4, 102, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #316 = IILL64
4637 { 317, 3, 1, 0, 96, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #317 = IILMux
4638 { 318, 4, 1, 0, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #318 = L128
4639 { 319, 4, 1, 0, 61, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #319 = LBMux
4640 { 320, 2, 1, 6, 722, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #320 = LEFR
4641 { 321, 2, 1, 6, 723, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #321 = LFER
4642 { 322, 2, 1, 0, 40, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #322 = LHIMux
4643 { 323, 4, 1, 0, 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #323 = LHMux
4644 { 324, 4, 1, 0, 69, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #324 = LLCMux
4645 { 325, 2, 1, 0, 66, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #325 = LLCRMux
4646 { 326, 4, 1, 0, 70, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #326 = LLHMux
4647 { 327, 2, 1, 0, 67, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #327 = LLHRMux
4648 { 328, 4, 1, 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #328 = LMux
4649 { 329, 5, 1, 0, 52, 0|(1ULL<<MCID::Pseudo), 0x80000ULL, ImplicitList1, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #329 = LOCHIMux
4650 { 330, 6, 1, 0, 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80080ULL, ImplicitList1, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #330 = LOCMux
4651 { 331, 5, 1, 0, 50, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x80000ULL, ImplicitList1, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #331 = LOCRMux
4652 { 332, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo74, -1 ,nullptr }, // Inst #332 = LTDBRCompare_VecPseudo
4653 { 333, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo75, -1 ,nullptr }, // Inst #333 = LTEBRCompare_VecPseudo
4654 { 334, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #334 = LTXBRCompare_VecPseudo
4655 { 335, 4, 1, 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #335 = LX
4656 { 336, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr }, // Inst #336 = MVCLoop
4657 { 337, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr }, // Inst #337 = MVCSequence
4658 { 338, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr }, // Inst #338 = MVSTLoop
4659 { 339, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #339 = MemBarrier
4660 { 340, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr }, // Inst #340 = NCLoop
4661 { 341, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr }, // Inst #341 = NCSequence
4662 { 342, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2310cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #342 = NG_MemFoldPseudo
4663 { 343, 3, 1, 0, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #343 = NIFMux
4664 { 344, 3, 1, 6, 148, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #344 = NIHF64
4665 { 345, 3, 1, 4, 149, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #345 = NIHH64
4666 { 346, 3, 1, 4, 150, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #346 = NIHL64
4667 { 347, 3, 1, 0, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #347 = NIHMux
4668 { 348, 3, 1, 6, 151, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #348 = NILF64
4669 { 349, 3, 1, 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #349 = NILH64
4670 { 350, 3, 1, 4, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #350 = NILL64
4671 { 351, 3, 1, 0, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #351 = NILMux
4672 { 352, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23088ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #352 = N_MemFoldPseudo
4673 { 353, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr }, // Inst #353 = OCLoop
4674 { 354, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr }, // Inst #354 = OCSequence
4675 { 355, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2310cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #355 = OG_MemFoldPseudo
4676 { 356, 3, 1, 0, 159, 0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #356 = OIFMux
4677 { 357, 3, 1, 6, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #357 = OIHF64
4678 { 358, 3, 1, 4, 161, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #358 = OIHH64
4679 { 359, 3, 1, 4, 162, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #359 = OIHL64
4680 { 360, 3, 1, 0, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #360 = OIHMux
4681 { 361, 3, 1, 6, 163, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #361 = OILF64
4682 { 362, 3, 1, 4, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #362 = OILH64
4683 { 363, 3, 1, 4, 165, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #363 = OILL64
4684 { 364, 3, 1, 0, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #364 = OILMux
4685 { 365, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23088ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #365 = O_MemFoldPseudo
4686 { 366, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #366 = PAIR128
4687 { 367, 6, 1, 6, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #367 = RISBHH
4688 { 368, 6, 1, 6, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #368 = RISBHL
4689 { 369, 6, 1, 6, 215, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #369 = RISBLH
4690 { 370, 6, 1, 6, 215, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #370 = RISBLL
4691 { 371, 6, 1, 0, 216, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #371 = RISBMux
4692 { 372, 0, 0, 2, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #372 = Return
4693 { 373, 5, 1, 0, 55, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x80000ULL, ImplicitList1, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #373 = SELRMux
4694 { 374, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23d0cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #374 = SG_MemFoldPseudo
4695 { 375, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #375 = SLG_MemFoldPseudo
4696 { 376, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #376 = SL_MemFoldPseudo
4697 { 377, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr }, // Inst #377 = SRSTLoop
4698 { 378, 4, 0, 0, 47, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #378 = ST128
4699 { 379, 4, 0, 0, 76, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #379 = STCMux
4700 { 380, 4, 0, 0, 77, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #380 = STHMux
4701 { 381, 4, 0, 0, 48, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #381 = STMux
4702 { 382, 5, 0, 0, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80080ULL, ImplicitList1, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #382 = STOCMux
4703 { 383, 4, 0, 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #383 = STX
4704 { 384, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23c88ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #384 = S_MemFoldPseudo
4705 { 385, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #385 = Select32
4706 { 386, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #386 = Select64
4707 { 387, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #387 = SelectF128
4708 { 388, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #388 = SelectF32
4709 { 389, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #389 = SelectF64
4710 { 390, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #390 = SelectVR128
4711 { 391, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #391 = SelectVR32
4712 { 392, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #392 = SelectVR64
4713 { 393, 0, 0, 2, 267, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #393 = Serialize
4714 { 394, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #394 = TBEGIN_nofloat
4715 { 395, 1, 0, 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #395 = TLS_GDCALL
4716 { 396, 1, 0, 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #396 = TLS_LDCALL
4717 { 397, 2, 0, 4, 258, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #397 = TMHH64
4718 { 398, 2, 0, 4, 259, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #398 = TMHL64
4719 { 399, 2, 0, 0, 257, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #399 = TMHMux
4720 { 400, 2, 0, 4, 260, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #400 = TMLH64
4721 { 401, 2, 0, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #401 = TMLL64
4722 { 402, 2, 0, 0, 257, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #402 = TMLMux
4723 { 403, 0, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #403 = Trap
4724 { 404, 4, 1, 6, 531, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #404 = VL32
4725 { 405, 4, 1, 6, 531, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #405 = VL64
4726 { 406, 2, 1, 6, 519, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #406 = VLR32
4727 { 407, 2, 1, 6, 519, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #407 = VLR64
4728 { 408, 3, 1, 6, 522, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #408 = VLVGP32
4729 { 409, 4, 0, 6, 538, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #409 = VST32
4730 { 410, 4, 0, 6, 538, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #410 = VST64
4731 { 411, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr }, // Inst #411 = XCLoop
4732 { 412, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr }, // Inst #412 = XCSequence
4733 { 413, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2310cULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #413 = XG_MemFoldPseudo
4734 { 414, 3, 1, 0, 170, 0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #414 = XIFMux
4735 { 415, 3, 1, 6, 172, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #415 = XIHF64
4736 { 416, 3, 1, 6, 173, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #416 = XILF64
4737 { 417, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x23088ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #417 = X_MemFoldPseudo
4738 { 418, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #418 = ZEXT128
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 1555 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
1556 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
1557 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
1558 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
1559 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
1560 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
1561 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
1562 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
1563 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
1564 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
1565 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
1566 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
1567 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
1568 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
1569 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
1570 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
1571 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
1572 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
1573 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
1574 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
1575 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
1576 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
1577 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
1578 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
1579 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
1580 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
1581 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
1582 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
1583 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
1584 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
1585 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
1586 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
1587 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
1588 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
1589 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
1590 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
1591 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
1592 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
1593 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
1594 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
1595 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
1596 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
1597 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
1598 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
1599 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
1600 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
1601 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
1602 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
1603 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
1604 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
1605 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
1606 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
1607 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
1608 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
1609 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
1610 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
1611 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
1612 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
1613 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
1614 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
1615 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
1616 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
1617 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
1618 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
1619 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
1620 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
1621 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
1622 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
1623 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
1624 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1625 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
1626 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
1627 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
1628 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
1629 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
1630 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
1631 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
1632 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
1633 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
1634 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
1635 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
1636 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
1637 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
1638 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
1639 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
1640 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
1641 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
1642 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
1643 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
1644 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
1645 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
1646 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
1647 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
1648 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
1649 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
1650 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
1651 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
1652 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
1653 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
1654 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
1655 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
1656 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
1657 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
1658 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
1659 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
1660 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
1661 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
1662 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
1663 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
1664 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
1665 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
1666 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
1667 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
1668 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
1669 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
1670 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
1671 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
1672 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
1673 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
1674 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
1675 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
1676 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
1677 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
1678 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
1679 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
1680 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
1681 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
1682 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
1683 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
1684 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
1685 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
1686 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
1687 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
1688 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
1689 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
1690 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
1691 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
1692 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
1693 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
1694 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
1695 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
1696 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
1697 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
1698 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
1699 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
1700 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
1701 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
1702 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
1703 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
1704 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
1705 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
1706 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
1707 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
1708 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
1709 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
1710 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
1711 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
1712 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
1713 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
1714 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
1715 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
1716 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
1717 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
1718 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
1719 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
1720 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
1721 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
1722 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
1723 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
1724 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
1725 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
1726 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
1727 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
1728 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
1729 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = CATCHRET
1730 { 175, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = CATCHRET_S
1731 { 176, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #176 = CLEANUPRET
1732 { 177, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #177 = CLEANUPRET_S
1733 { 178, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #178 = COMPILER_FENCE
1734 { 179, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #179 = COMPILER_FENCE_S
1735 { 180, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #180 = RETHROW_IN_CATCH
1736 { 181, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #181 = RETHROW_IN_CATCH_S
gen/lib/Target/X86/X86GenInstrInfo.inc17688 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
17689 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
17690 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
17691 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
17692 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
17693 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
17694 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
17695 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
17696 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
17697 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
17698 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
17699 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
17700 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
17701 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
17702 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
17703 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
17704 { 16, 2, 1, 0, 579, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
17705 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
17706 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
17707 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
17708 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
17709 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
17710 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
17711 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
17712 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
17713 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
17714 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
17715 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
17716 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
17717 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
17718 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
17719 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
17720 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
17721 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
17722 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
17723 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
17724 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
17725 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
17726 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
17727 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
17728 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
17729 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
17730 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
17731 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
17732 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
17733 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
17734 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
17735 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
17736 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
17737 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
17738 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
17739 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
17740 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
17741 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
17742 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
17743 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
17744 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
17745 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
17746 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
17747 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
17748 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
17749 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
17750 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
17751 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
17752 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
17753 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
17754 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
17755 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
17756 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
17757 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
17758 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
17759 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
17760 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
17761 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
17762 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
17763 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
17764 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
17765 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
17766 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
17767 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
17768 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
17769 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
17770 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
17771 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
17772 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
17773 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
17774 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
17775 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
17776 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
17777 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
17778 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
17779 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
17780 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
17781 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
17782 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
17783 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
17784 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
17785 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
17786 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
17787 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
17788 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
17789 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
17790 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
17791 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
17792 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
17793 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
17794 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
17795 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
17796 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
17797 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
17798 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
17799 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
17800 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
17801 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
17802 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
17803 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
17804 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
17805 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
17806 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
17807 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
17808 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
17809 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
17810 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
17811 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
17812 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
17813 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
17814 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
17815 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
17816 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
17817 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
17818 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
17819 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
17820 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
17821 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
17822 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
17823 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
17824 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
17825 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
17826 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
17827 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
17828 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
17829 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
17830 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
17831 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
17832 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
17833 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
17834 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
17835 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
17836 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
17837 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
17838 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
17839 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
17840 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
17841 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
17842 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
17843 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
17844 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
17845 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
17846 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
17847 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
17848 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
17849 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
17850 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
17851 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
17852 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
17853 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
17854 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
17855 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
17856 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
17857 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
17858 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
17859 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
17860 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
17861 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
17862 { 174, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ADD16ri8_DB
17863 { 175, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = ADD16ri_DB
17864 { 176, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #176 = ADD16rr_DB
17865 { 177, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #177 = ADD32ri8_DB
17866 { 178, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #178 = ADD32ri_DB
17867 { 179, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #179 = ADD32rr_DB
17868 { 180, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #180 = ADD64ri32_DB
17869 { 181, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #181 = ADD64ri8_DB
17870 { 182, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #182 = ADD64rr_DB
17871 { 183, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #183 = ADD8ri_DB
17872 { 184, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #184 = ADD8rr_DB
17873 { 185, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #185 = AVX1_SETALLONES
17874 { 186, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #186 = AVX2_SETALLONES
17875 { 187, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #187 = AVX512_128_SET0
17876 { 188, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #188 = AVX512_256_SET0
17877 { 189, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #189 = AVX512_512_SET0
17878 { 190, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #190 = AVX512_512_SETALLONES
17879 { 191, 2, 1, 0, 3, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #191 = AVX512_512_SEXT_MASK_32
17880 { 192, 2, 1, 0, 3, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #192 = AVX512_512_SEXT_MASK_64
17881 { 193, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = AVX512_FsFLD0F128
17882 { 194, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #194 = AVX512_FsFLD0SD
17883 { 195, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #195 = AVX512_FsFLD0SS
17884 { 196, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #196 = AVX_SET0
17885 { 197, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #197 = FsFLD0F128
17886 { 198, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #198 = FsFLD0SD
17887 { 199, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #199 = FsFLD0SS
17888 { 200, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #200 = KSET0D
17889 { 201, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #201 = KSET0Q
17890 { 202, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #202 = KSET0W
17891 { 203, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #203 = KSET1D
17892 { 204, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #204 = KSET1Q
17893 { 205, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #205 = KSET1W
17894 { 206, 8, 1, 0, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo58, -1 ,nullptr }, // Inst #206 = LCMPXCHG16B_SAVE_RBX
17895 { 207, 8, 1, 0, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, ImplicitList5, OperandInfo59, -1 ,nullptr }, // Inst #207 = LCMPXCHG8B_SAVE_EBX
17896 { 208, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #208 = MMX_SET0
17897 { 209, 0, 0, 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #209 = MORESTACK_RET
17898 { 210, 0, 0, 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #210 = MORESTACK_RET_RESTORE_R10
17899 { 211, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #211 = MOV32ImmSExti8
17900 { 212, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #212 = MOV32r0
17901 { 213, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #213 = MOV32r1
17902 { 214, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #214 = MOV32r_1
17903 { 215, 2, 1, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #215 = MOV32ri64
17904 { 216, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #216 = MOV64ImmSExti8
17905 { 217, 1, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #217 = RETPOLINE_CALL32
17906 { 218, 1, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #218 = RETPOLINE_CALL64
17907 { 219, 2, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #219 = RETPOLINE_TCRETURN32
17908 { 220, 2, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #220 = RETPOLINE_TCRETURN64
17909 { 221, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #221 = SEH_EndPrologue
17910 { 222, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #222 = SEH_Epilogue
17911 { 223, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #223 = SEH_PushFrame
17912 { 224, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #224 = SEH_PushReg
17913 { 225, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #225 = SEH_SaveReg
17914 { 226, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #226 = SEH_SaveXMM
17915 { 227, 2, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #227 = SEH_SetFrame
17916 { 228, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #228 = SEH_StackAlign
17917 { 229, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #229 = SEH_StackAlloc
17918 { 230, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #230 = SETB_C16r
17919 { 231, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #231 = SETB_C32r
17920 { 232, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo64, -1 ,nullptr }, // Inst #232 = SETB_C64r
17921 { 233, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #233 = SETB_C8r
17922 { 234, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #234 = SHLDROT32ri
17923 { 235, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #235 = SHLDROT64ri
17924 { 236, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #236 = SHRDROT32ri
17925 { 237, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #237 = SHRDROT64ri
17926 { 238, 6, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #238 = VMOVAPSZ128mr_NOVLX
17927 { 239, 6, 1, 0, 1159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #239 = VMOVAPSZ128rm_NOVLX
17928 { 240, 6, 0, 0, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #240 = VMOVAPSZ256mr_NOVLX
17929 { 241, 6, 1, 0, 1185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #241 = VMOVAPSZ256rm_NOVLX
17930 { 242, 6, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #242 = VMOVUPSZ128mr_NOVLX
17931 { 243, 6, 1, 0, 1159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #243 = VMOVUPSZ128rm_NOVLX
17932 { 244, 6, 0, 0, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #244 = VMOVUPSZ256mr_NOVLX
17933 { 245, 6, 1, 0, 1185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #245 = VMOVUPSZ256rm_NOVLX
17934 { 246, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #246 = V_SET0
17935 { 247, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #247 = V_SETALLONES
17936 { 248, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #248 = XABORT_DEF
17937 { 249, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #249 = XOR32_FP
17938 { 250, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #250 = XOR64_FP
gen/lib/Target/XCore/XCoreGenInstrInfo.inc 499 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
500 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
501 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
502 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
503 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
504 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
505 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
506 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
507 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
508 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
509 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
510 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
511 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
512 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
513 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
514 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
515 { 16, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
516 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
517 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
518 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
519 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
520 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
521 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
522 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
523 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
524 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
525 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
526 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
527 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
528 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
529 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
530 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
531 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
532 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
533 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
534 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD
535 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB
536 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL
537 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV
538 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV
539 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM
540 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM
541 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND
542 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR
543 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR
544 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
545 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI
546 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
547 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
548 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT
549 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
550 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT
551 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
552 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
553 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
554 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
555 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
556 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
557 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST
558 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
559 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
560 { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD
561 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD
562 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD
563 { 64, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #64 = G_INDEXED_LOAD
564 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_INDEXED_SEXTLOAD
565 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #66 = G_INDEXED_ZEXTLOAD
566 { 67, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #67 = G_STORE
567 { 68, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_INDEXED_STORE
568 { 69, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
569 { 70, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG
570 { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_XCHG
571 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_ADD
572 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_SUB
573 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_AND
574 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_NAND
575 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_OR
576 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_XOR
577 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_MAX
578 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MIN
579 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_UMAX
580 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMIN
581 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_FADD
582 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FSUB
583 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
584 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_BRCOND
585 { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_BRINDIRECT
586 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
587 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
588 { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ANYEXT
589 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #90 = G_TRUNC
590 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #91 = G_CONSTANT
591 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #92 = G_FCONSTANT
592 { 93, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #93 = G_VASTART
593 { 94, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #94 = G_VAARG
594 { 95, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_SEXT
595 { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #96 = G_SEXT_INREG
596 { 97, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #97 = G_ZEXT
597 { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #98 = G_SHL
598 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #99 = G_LSHR
599 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #100 = G_ASHR
600 { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ICMP
601 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #102 = G_FCMP
602 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #103 = G_SELECT
603 { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #104 = G_UADDO
604 { 105, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #105 = G_UADDE
605 { 106, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #106 = G_USUBO
606 { 107, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #107 = G_USUBE
607 { 108, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #108 = G_SADDO
608 { 109, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #109 = G_SADDE
609 { 110, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #110 = G_SSUBO
610 { 111, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #111 = G_SSUBE
611 { 112, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #112 = G_UMULO
612 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #113 = G_SMULO
613 { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_UMULH
614 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #115 = G_SMULH
615 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #116 = G_FADD
616 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #117 = G_FSUB
617 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #118 = G_FMUL
618 { 119, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #119 = G_FMA
619 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #120 = G_FMAD
620 { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #121 = G_FDIV
621 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #122 = G_FREM
622 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #123 = G_FPOW
623 { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #124 = G_FEXP
624 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #125 = G_FEXP2
625 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #126 = G_FLOG
626 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FLOG2
627 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FLOG10
628 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_FNEG
629 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #130 = G_FPEXT
630 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #131 = G_FPTRUNC
631 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #132 = G_FPTOSI
632 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #133 = G_FPTOUI
633 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #134 = G_SITOFP
634 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_UITOFP
635 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #136 = G_FABS
636 { 137, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #137 = G_FCOPYSIGN
637 { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #138 = G_FCANONICALIZE
638 { 139, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #139 = G_FMINNUM
639 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #140 = G_FMAXNUM
640 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #141 = G_FMINNUM_IEEE
641 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #142 = G_FMAXNUM_IEEE
642 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #143 = G_FMINIMUM
643 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #144 = G_FMAXIMUM
644 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #145 = G_GEP
645 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #146 = G_PTR_MASK
646 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #147 = G_SMIN
647 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #148 = G_SMAX
648 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #149 = G_UMIN
649 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #150 = G_UMAX
650 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
651 { 152, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #152 = G_BRJT
652 { 153, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_INSERT_VECTOR_ELT
653 { 154, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_EXTRACT_VECTOR_ELT
654 { 155, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_SHUFFLE_VECTOR
655 { 156, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #156 = G_CTTZ
656 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #157 = G_CTTZ_ZERO_UNDEF
657 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #158 = G_CTLZ
658 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #159 = G_CTLZ_ZERO_UNDEF
659 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #160 = G_CTPOP
660 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #161 = G_BSWAP
661 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #162 = G_BITREVERSE
662 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #163 = G_FCEIL
663 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #164 = G_FCOS
664 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #165 = G_FSIN
665 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #166 = G_FSQRT
666 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #167 = G_FFLOOR
667 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #168 = G_FRINT
668 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #169 = G_FNEARBYINT
669 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #170 = G_ADDRSPACE_CAST
670 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #171 = G_BLOCK_ADDR
671 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #172 = G_JUMP_TABLE
672 { 173, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #173 = G_DYN_STACKALLOC
673 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
674 { 175, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
675 { 176, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #176 = BR_JT
676 { 177, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #177 = BR_JT32
677 { 178, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = EH_RETURN
678 { 179, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #179 = FRAME_TO_ARGS_OFFSET
679 { 180, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #180 = Int_MemBarrier
680 { 181, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #181 = LDAWFI
681 { 182, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #182 = LDWFI
682 { 183, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #183 = SELECT_CC
683 { 184, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #184 = STWFI
include/llvm/CodeGen/MachineInstr.h 669 return hasProperty(MCID::Pseudo, Type);
include/llvm/MC/MCInstrDesc.h 262 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }