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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6876 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
6878 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
7021 { 174, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = CATCHRET
7022 { 175, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #175 = CLEANUPRET
7669 { 822, 0, 0, 4, 682, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #822 = DRPS
7734 { 887, 0, 0, 4, 685, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #887 = ERET
7735 { 888, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #888 = ERETAA
7736 { 889, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #889 = ERETAB
9858 { 3011, 1, 0, 4, 620, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #3011 = RET
9859 { 3012, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3012 = RETAA
9860 { 3013, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3013 = RETAB
9861 { 3014, 0, 0, 0, 622, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3014 = RET_ReallyLR
11395 { 4548, 2, 0, 0, 619, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #4548 = TCRETURNdi
11396 { 4549, 2, 0, 0, 622, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo439, -1 ,nullptr }, // Inst #4549 = TCRETURNri
11397 { 4550, 2, 0, 0, 11, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #4550 = TCRETURNriALL
11398 { 4551, 2, 0, 0, 11, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo440, -1 ,nullptr }, // Inst #4551 = TCRETURNriBTI
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16091 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
16093 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
17687 { 1625, 0, 0, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1625 = SI_RETURN
17688 { 1626, 0, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x11000000001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1626 = SI_RETURN_TO_EPILOG
17731 { 1669, 3, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Convergent), 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1669 = SI_TCRETURN
18126 { 2064, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2064 = S_SETPC_B64_return
27407 { 11345, 0, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11345 = S_CODE_END
27432 { 11370, 1, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #11370 = S_ENDPGM
27433 { 11371, 0, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11371 = S_ENDPGM_ORDERED_PS_DONE
27434 { 11372, 0, 0, 4, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x41ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11372 = S_ENDPGM_SAVED
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 667 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
669 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
866 { 228, 0, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #228 = RETURN
gen/lib/Target/ARC/ARCGenInstrInfo.inc 672 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
674 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
918 { 275, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #275 = GEN_JEQ_S
921 { 278, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #278 = GEN_JNE_S
924 { 281, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #281 = GEN_J_S_D_BLINK
952 { 309, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #309 = J_S_BLINK
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5862 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
5864 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
6044 { 211, 5, 1, 4, 419, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #211 = LDMIA_RET
6113 { 280, 3, 0, 4, 850, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #280 = SUBS_PC_LR
6118 { 285, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #285 = TAILJMPd
6119 { 286, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #286 = TAILJMPr
6120 { 287, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #287 = TAILJMPr4
6121 { 288, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #288 = TCRETURNdi
6122 { 289, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #289 = TCRETURNri
6355 { 522, 5, 1, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #522 = t2LDMIA_RET
6406 { 573, 2, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #573 = tBX_RET
6407 { 574, 3, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #574 = tBX_RET_vararg
6419 { 586, 3, 0, 2, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #586 = tPOP_RET
6425 { 592, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #592 = tTAILJMPd
6426 { 593, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #593 = tTAILJMPdND
6427 { 594, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #594 = tTAILJMPr
6462 { 629, 2, 0, 4, 851, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #629 = BX_RET
6493 { 660, 2, 0, 4, 841, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList10, OperandInfo116, -1 ,nullptr }, // Inst #660 = ERET
6584 { 751, 2, 0, 4, 880, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #751 = MOVPCLR
9773 { 3940, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3940 = t2RFEDB
9774 { 3941, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3941 = t2RFEDBW
9775 { 3942, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3942 = t2RFEIA
9776 { 3943, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3943 = t2RFEIAW
9899 { 4066, 3, 0, 4, 849, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, ImplicitList10, OperandInfo142, -1 ,nullptr }, // Inst #4066 = t2SUBS_PC_LR
gen/lib/Target/AVR/AVRGenInstrInfo.inc 512 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
514 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
800 { 317, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #317 = RET
801 { 318, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #318 = RETI
gen/lib/Target/BPF/BPFGenInstrInfo.inc 449 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
451 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
698 { 278, 0, 0, 8, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #278 = RET
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3659 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
3661 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
3948 { 318, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #318 = PS_tailcall_i
3949 { 319, 1, 0, 4, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #319 = PS_tailcall_r
4707 { 1077, 1, 0, 4, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000024ULL, ImplicitList22, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #1077 = EH_RETURN_JMPR
5166 { 1536, 2, 1, 4, 28, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x2809000000025ULL, ImplicitList34, ImplicitList36, OperandInfo51, -1 ,nullptr }, // Inst #1536 = L4_return
5167 { 1537, 3, 1, 4, 23, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000000c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1537 = L4_return_f
5168 { 1538, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1538 = L4_return_fnew_pnt
5169 { 1539, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000001c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1539 = L4_return_fnew_pt
5170 { 1540, 3, 1, 4, 23, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000000425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1540 = L4_return_t
5171 { 1541, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1541 = L4_return_tnew_pnt
5172 { 1542, 3, 1, 4, 24, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000001425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr }, // Inst #1542 = L4_return_tnew_pt
5500 { 1870, 1, 0, 4, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr }, // Inst #1870 = PS_jmpret
5501 { 1871, 2, 0, 4, 16, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1871 = PS_jmpretf
5502 { 1872, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1872 = PS_jmpretfnew
5503 { 1873, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x2001000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1873 = PS_jmpretfnewpt
5504 { 1874, 2, 0, 4, 16, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1874 = PS_jmprett
5505 { 1875, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1875 = PS_jmprettnew
5506 { 1876, 2, 0, 4, 108, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x2001000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr }, // Inst #1876 = PS_jmprettnewpt
5525 { 1895, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1895 = RESTORE_DEALLOC_RET_JMP_V4
5526 { 1896, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1896 = RESTORE_DEALLOC_RET_JMP_V4_EXT
5527 { 1897, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1897 = RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
5528 { 1898, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1898 = RESTORE_DEALLOC_RET_JMP_V4_PIC
6014 { 2384, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000002bULL, ImplicitList46, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2384 = SL2_jumpr31
6015 { 2385, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c2bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2385 = SL2_jumpr31_f
6016 { 2386, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c2bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2386 = SL2_jumpr31_fnew
6017 { 2387, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000042bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2387 = SL2_jumpr31_t
6018 { 2388, 0, 0, 4, 178, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000142bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr }, // Inst #2388 = SL2_jumpr31_tnew
6024 { 2394, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000002bULL, ImplicitList44, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2394 = SL2_return
6025 { 2395, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000000c2bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2395 = SL2_return_f
6026 { 2396, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001c2bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2396 = SL2_return_fnew
6027 { 2397, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000042bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2397 = SL2_return_t
6028 { 2398, 0, 0, 4, 179, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000142bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #2398 = SL2_return_tnew
gen/lib/Target/Lanai/LanaiGenInstrInfo.inc 399 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
401 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
600 { 230, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #230 = RET
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 670 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
672 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
1049 { 408, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #408 = RET
1050 { 409, 0, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #409 = RETI
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4844 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
4846 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
5143 { 328, 0, 0, 4, 916, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #328 = ERet
5208 { 393, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #393 = MIPSeh_return32
5209 { 394, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #394 = MIPSeh_return64
5289 { 474, 1, 0, 4, 383, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #474 = PseudoReturn
5290 { 475, 1, 0, 4, 1008, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #475 = PseudoReturn64
5315 { 500, 0, 0, 4, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #500 = RetRA
5316 { 501, 0, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #501 = RetRA16
5373 { 558, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #558 = TAILCALL
5374 { 559, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #559 = TAILCALL64R6REG
5375 { 560, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #560 = TAILCALLHB64R6REG
5376 { 561, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #561 = TAILCALLHBR6REG
5377 { 562, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #562 = TAILCALLR6REG
5378 { 563, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #563 = TAILCALLREG
5379 { 564, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #564 = TAILCALLREG64
5380 { 565, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #565 = TAILCALLREGHB
5381 { 566, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo86, -1 ,nullptr }, // Inst #566 = TAILCALLREGHB64
5382 { 567, 1, 0, 4, 955, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #567 = TAILCALLREG_MM
5383 { 568, 1, 0, 4, 997, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo49, -1 ,nullptr }, // Inst #568 = TAILCALLREG_MMR6
5384 { 569, 1, 0, 4, 956, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #569 = TAILCALL_MM
5385 { 570, 1, 0, 4, 998, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #570 = TAILCALL_MMR6
6497 { 1682, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1682 = JrRa16
6498 { 1683, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1683 = JrcRa16
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 6660 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
6662 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
8327 { 1696, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1696 = Return
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2937 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
2939 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
3286 { 378, 2, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList15, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #378 = BCCLR
3310 { 402, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList15, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #402 = BCLR
3331 { 423, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #423 = BDNZLR
3332 { 424, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList10, nullptr, -1 ,nullptr }, // Inst #424 = BDNZLR8
3336 { 428, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #428 = BDNZLRm
3337 { 429, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #429 = BDNZLRp
3351 { 443, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #443 = BDZLR
3352 { 444, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList10, nullptr, -1 ,nullptr }, // Inst #444 = BDZLR8
3356 { 448, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #448 = BDZLRm
3357 { 449, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #449 = BDZLRp
3371 { 463, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList15, nullptr, nullptr, -1 ,nullptr }, // Inst #463 = BLR
3372 { 464, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList20, nullptr, nullptr, -1 ,nullptr }, // Inst #464 = BLR8
4527 { 1619, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1619 = TAILB
4528 { 1620, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1620 = TAILB8
4529 { 1621, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1621 = TAILBA
4530 { 1622, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1622 = TAILBA8
4531 { 1623, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, nullptr, nullptr, -1 ,nullptr }, // Inst #1623 = TAILBCTR
4532 { 1624, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, nullptr, -1 ,nullptr }, // Inst #1624 = TAILBCTR8
4537 { 1629, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1629 = TCRETURNai
4538 { 1630, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1630 = TCRETURNai8
4539 { 1631, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1631 = TCRETURNdi
4540 { 1632, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1632 = TCRETURNdi8
4541 { 1633, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1633 = TCRETURNri
4542 { 1634, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1634 = TCRETURNri8
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 691 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
693 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
874 { 212, 0, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #212 = PseudoRET
879 { 217, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #217 = PseudoTAIL
880 { 218, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #218 = PseudoTAILIndirect
1121 { 459, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #459 = MRET
1157 { 495, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #495 = SRET
1166 { 504, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #504 = URET
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 959 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
961 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
1479 { 549, 1, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #549 = RET
1480 { 550, 1, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #550 = RETL
1481 { 551, 2, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #551 = RETTri
1482 { 552, 2, 0, 4, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #552 = RETTrr
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4349 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
4351 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
4579 { 259, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #259 = CGIBCall
4580 { 260, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #260 = CGIBReturn
4581 { 261, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #261 = CGRBCall
4582 { 262, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #262 = CGRBReturn
4584 { 264, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #264 = CIBCall
4585 { 265, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #265 = CIBReturn
4589 { 269, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #269 = CLGIBCall
4590 { 270, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #270 = CLGIBReturn
4591 { 271, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #271 = CLGRBCall
4592 { 272, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #272 = CLGRBReturn
4593 { 273, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #273 = CLIBCall
4594 { 274, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #274 = CLIBReturn
4596 { 276, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #276 = CLRBCall
4597 { 277, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #277 = CLRBReturn
4600 { 280, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #280 = CRBCall
4601 { 281, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #281 = CRBReturn
4603 { 283, 2, 0, 2, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #283 = CallBCR
4604 { 284, 0, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #284 = CallBR
4606 { 286, 3, 0, 6, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #286 = CallBRCL
4607 { 287, 1, 0, 6, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #287 = CallJG
4608 { 288, 2, 0, 2, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #288 = CondReturn
4692 { 372, 0, 0, 2, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #372 = Return
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 1584 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
1586 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
2201 { 646, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #646 = FALLTHROUGH_RETURN
2202 { 647, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #647 = FALLTHROUGH_RETURN_S
2641 { 1086, 1, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr }, // Inst #1086 = PRET_CALL_INDIRECT
2642 { 1087, 1, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr }, // Inst #1087 = PRET_CALL_INDIRECT_S
2673 { 1118, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1118 = RETURN
2674 { 1119, 0, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #1119 = RETURN_S
2675 { 1120, 1, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1120 = RET_CALL
2676 { 1121, 2, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1121 = RET_CALL_INDIRECT
2677 { 1122, 2, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1122 = RET_CALL_INDIRECT_S
2678 { 1123, 1, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1123 = RET_CALL_S
gen/lib/Target/X86/X86GenInstrInfo.inc17717 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
17719 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
17907 { 219, 2, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #219 = RETPOLINE_TCRETURN32
17908 { 220, 2, 0, 0, 7, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #220 = RETPOLINE_TCRETURN64
18293 { 605, 2, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #605 = CATCHRET
18305 { 617, 0, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #617 = CLEANUPRET
18610 { 922, 1, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x30c0000001ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #922 = EH_RETURN
18611 { 923, 1, 0, 0, 8, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x30c0000001ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #923 = EH_RETURN64
18803 { 1115, 1, 0, 0, 596, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0xe00000ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1115 = IRET
18804 { 1116, 0, 0, 0, 953, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x33c0e00081ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1116 = IRET16
18805 { 1117, 0, 0, 0, 953, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x33c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1117 = IRET32
18806 { 1118, 0, 0, 0, 953, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x33c0e10001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1118 = IRET64
19058 { 1370, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1370 = LRETIL
19059 { 1371, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e90001ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1371 = LRETIQ
19060 { 1372, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e80081ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1372 = LRETIW
19061 { 1373, 0, 0, 0, 952, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x32c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1373 = LRETL
19062 { 1374, 0, 0, 0, 928, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x32c0e10001ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1374 = LRETQ
19063 { 1375, 0, 0, 0, 952, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x32c0e00081ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1375 = LRETW
20124 { 2436, 1, 0, 0, 693, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0xe00000ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2436 = RET
20125 { 2437, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2437 = RETIL
20126 { 2438, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2438 = RETIQ
20127 { 2439, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80081ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2439 = RETIW
20128 { 2440, 0, 0, 0, 847, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x30c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2440 = RETL
20129 { 2441, 0, 0, 0, 713, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x30c0e00101ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2441 = RETQ
20130 { 2442, 0, 0, 0, 952, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x30c0e00081ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2442 = RETW
20547 { 2859, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #2859 = TAILJMPd
20548 { 2860, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #2860 = TAILJMPd64
20549 { 2861, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList19, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2861 = TAILJMPd64_CC
20550 { 2862, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2862 = TAILJMPd_CC
20551 { 2863, 5, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2863 = TAILJMPm
20552 { 2864, 5, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2864 = TAILJMPm64
20553 { 2865, 5, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, ImplicitList6, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2865 = TAILJMPm64_REX
20554 { 2866, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2866 = TAILJMPr
20555 { 2867, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2867 = TAILJMPr64
20556 { 2868, 1, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, ImplicitList6, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2868 = TAILJMPr64_REX
20557 { 2869, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList17, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2869 = TCRETURNdi
20558 { 2870, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList6, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2870 = TCRETURNdi64
20559 { 2871, 3, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList19, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2871 = TCRETURNdi64cc
20560 { 2872, 3, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2872 = TCRETURNdicc
20561 { 2873, 6, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList17, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2873 = TCRETURNmi
20562 { 2874, 6, 0, 0, 5, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList6, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2874 = TCRETURNmi64
20563 { 2875, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList17, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2875 = TCRETURNri
20564 { 2876, 2, 0, 0, 7, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList6, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2876 = TCRETURNri64
gen/lib/Target/XCore/XCoreGenInstrInfo.inc 528 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
530 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
677 { 178, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = EH_RETURN
841 { 342, 1, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #342 = RETSP_lu6
842 { 343, 1, 0, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #343 = RETSP_u6
include/llvm/CodeGen/MachineInstr.h 673 return hasProperty(MCID::Return, Type);
include/llvm/MC/MCInstrDesc.h 265 bool isReturn() const { return Flags & (1ULL << MCID::Return); }