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|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARC/ARCGenDAGISel.inc 1206 return isInt<12>(N->getSExtValue());
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72561 return isInt<4>(V >> L);
gen/lib/Target/Mips/MipsGenDAGISel.inc30171 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
30261 return isInt<10>(Imm);
30363 return isInt<10>(N->getSExtValue());
30404 return isInt<6>(Imm);
gen/lib/Target/Mips/MipsGenFastISel.inc 18 return isInt<6>(Imm);
gen/lib/Target/Mips/MipsGenGlobalISel.inc 415 return isInt<10>(Imm);
420 return isInt<6>(Imm);
534 return isInt<6>(Imm);
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44478 return Imm && isInt<5>(Imm);
gen/lib/Target/PowerPC/PPCGenFastISel.inc 26 return Imm && isInt<5>(Imm);
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 2835 return isInt<12>(Imm);
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 32 return (Imm != 0) && isInt<6>(Imm);
40 return isInt<6>(Imm);
915 return isInt<12>(Imm);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13814 return isInt<12>(Imm);
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 162 return isInt<12>(Imm);
182 return isInt<6>(Imm);
187 return (Imm != 0) && isInt<6>(Imm);
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3493 return isInt<13>(N->getSExtValue());
3566 return isInt<11>(N->getSExtValue());
3588 return Imm < 0 && isInt<33>(Imm);
include/llvm/ADT/PointerEmbeddedInt.h 64 assert((std::is_signed<IntT>::value ? isInt<Bits>(I) : isUInt<Bits>(I)) &&
include/llvm/Support/MathExtras.h 355 return isInt<N + S>(x) && (x % (UINT64_C(1) << S) == 0);
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp 419 assert(isInt<28>(BranchImm));
441 assert(isInt<33>(Result) && "overflow check failed for relocation");
1044 if (!isInt<28>(Address + Value.Addend - SourceAddress))
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h 196 assert(isInt<28>(Addend) && "Branch target is out of range.");
210 assert(isInt<33>(Addend) && "Invalid page reloc value.");
lib/MC/MachObjectWriter.cpp 633 assert(isInt<24>(Index));
lib/Target/AArch64/AArch64CompressJumpTables.cpp 114 if (!isInt<21>(MinOffset - Offset)) {
lib/Target/AArch64/AArch64FastISel.cpp 1035 if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
lib/Target/AArch64/AArch64ISelLowering.cpp 9149 if (isInt<9>(Offset))
11871 if (!isInt<9>(RHSC))
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 177 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
182 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
lib/Target/AMDGPU/SIISelLowering.cpp 1088 return isInt<13>(AM.BaseOffs) && AM.Scale == 0;
lib/Target/AMDGPU/SIInstrInfo.cpp 6293 return (Signed && isInt<12>(Offset)) ||
6297 return (Signed && isInt<13>(Offset)) ||
lib/Target/ARC/ARCBranchFinalize.cpp 171 isInt<9>(MaxSize) ? replaceWithBRcc(P.first) : replaceWithCmpBcc(P.first);
lib/Target/ARC/ARCFrameLowering.cpp 67 else if (isInt<12>(AbsAmount))
141 else if (isInt<12>(VarArgsBytes))
286 else if (isInt<12>(MoveAmount))
301 else if (isInt<12>(4 * StackSlotsUsedByFunclet))
328 else if (isInt<12>(VarArgsBytes))
459 else if (isInt<12>(NumBytes))
lib/Target/ARC/ARCISelDAGToDAG.cpp 111 if (!isInt<9>(RHSC))
174 isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm,
lib/Target/ARC/ARCInstrInfo.cpp 362 if (isInt<12>(Value)) {
lib/Target/ARC/ARCOptAddrMode.cpp 116 static bool isValidLoadStoreOffset(int64_t Off) { return isInt<9>(Off); }
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 551 if (!isInt<25>(Value)) {
575 if (!isInt<21>(Value)) {
592 if (!isInt<25>(Value - 4) ||
596 !isInt<23>(Value - 4))) {
lib/Target/BPF/AsmParser/BPFAsmParser.cpp 138 return (isConstantImm() && isInt<12>(getConstantImm()));
lib/Target/Hexagon/HexagonBitSimplify.cpp 2121 if (isInt<10>(Imm))
lib/Target/Hexagon/HexagonCopyToCombine.cpp 176 return !Op.isImm() || !isInt<N>(Op.getImm());
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 587 if (isInt<9>(ValConst)) {
608 if (isInt<9>(-ValConst)) {
lib/Target/Hexagon/HexagonISelLowering.cpp 3076 if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
lib/Target/Hexagon/HexagonInstrInfo.cpp 2274 return isInt<11>(offset);
2283 return isInt<24>(offset);
2292 return isInt<17>(offset);
2301 return isInt<9>(offset);
2307 return isInt<11>(offset);
2656 return isInt<4>(Count);
2666 return isInt<3>(Count);
2701 return isInt<4>(Offset >> Log2_32(VectorSize));
3953 isInt<7>(MI.getOperand(2).getImm()))
lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp 372 return isInt<10>(Value);
lib/Target/Lanai/LanaiISelDAGToDAG.cpp 96 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
142 if (isInt<10>(CN->getSExtValue())) {
174 (!RiMode && isInt<10>(CN->getSExtValue()))) {
lib/Target/Lanai/LanaiMemAluCombiner.cpp 314 ((IsSpls && isInt<10>(Op2.getImm())) ||
lib/Target/Lanai/LanaiRegisterInfo.cpp 170 if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) ||
lib/Target/Lanai/LanaiTargetTransformInfo.h 58 if (isInt<21>(Imm.getZExtValue()))
lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp 230 assert(isInt<SizeInBits>(OffsetOp.getImm()) && "Constant value truncated");
lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp 272 assert(isInt<10>(Op2.getImm()) &&
lib/Target/MSP430/MSP430BranchSelector.cpp 76 return isInt<10>(Words);
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1263 return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm();
1271 return isConstantImm() ? (isInt<Bits>(getConstantImm()) ||
1277 return isConstantImm() && isInt<Bits>(getConstantImm() - Offset);
1345 return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
1946 if (!isInt<10>(Imm))
2115 if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
2225 if ((Imm % 4 != 0) || !isInt<25>(Imm))
3502 if (isInt<11>(Offset.getImm())) {
3508 if (!isInt<17>(Offset.getImm()))
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp 91 if (!isInt<19>(Value)) {
130 if (!isInt<7>(Value)) {
140 if (!isInt<10>(Value)) {
159 if (!isInt<18>(Value)) {
172 if (!isInt<18>(Value)) {
181 if (!isInt<21>(Value)) {
190 if (!isInt<26>(Value)) {
199 if (!isInt<26>(Value)) {
208 if (!isInt<21>(Value)) {
lib/Target/Mips/Mips16FrameLowering.cpp 159 return isInt<15>(MFI.getMaxCallFrameSize()) && !MFI.hasVarSizedObjects();
lib/Target/Mips/Mips16InstrInfo.cpp 492 return isInt<15>(Amount);
lib/Target/Mips/Mips16InstrInfo.h 95 return ((offset & 7) == 0) && isInt<11>(offset);
lib/Target/Mips/MipsISelLowering.cpp 4088 if ((isInt<15>(Val))) {
lib/Target/Mips/MipsInstrInfo.cpp 304 return isInt<18>(BrOffset);
320 return isInt<17>(BrOffset);
324 return isInt<11>(BrOffset);
333 return isInt<28>(BrOffset);
357 return isInt<18>(BrOffset);
361 return isInt<23>(BrOffset);
365 return isInt<11>(BrOffset);
373 return isInt<27>(BrOffset);
387 return isInt<17>(BrOffset);
399 return isInt<18>(BrOffset);
403 return isInt<23>(BrOffset);
407 return isInt<18>(BrOffset);
410 return isInt<17>(BrOffset);
417 return isInt<18>(BrOffset);
430 return isInt<18>(BrOffset);
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 315 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
365 return isInt<17>(getImmS16Context());
379 if (isInt<26>(getImm()))
383 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 109 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
114 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 430 return IsConstantImm && isInt<6>(Imm) &&
440 return IsConstantImm && isInt<6>(Imm) && (Imm != 0) &&
517 IsValid = isInt<12>(Imm);
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp 211 if (!isInt<21>(Value))
228 if (!isInt<13>(Value))
lib/Target/RISCV/RISCVFrameLowering.cpp 73 if (isInt<12>(Val)) {
212 if (isInt<12>(-(int)MaxAlignment)) {
424 if (!isInt<11>(MFI.estimateStackSize(MF))) {
491 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
lib/Target/RISCV/RISCVISelLowering.cpp 261 if (!isInt<12>(AM.BaseOffs))
279 return isInt<12>(Imm);
283 return isInt<12>(Imm);
2693 if (isInt<12>(CVal))
lib/Target/RISCV/RISCVInstrInfo.cpp 517 Ok = isInt<12>(Imm);
lib/Target/RISCV/RISCVRegisterInfo.cpp 127 if (!isInt<12>(Offset)) {
lib/Target/Sparc/DelaySlotFiller.cpp 459 if (!isInt<3>(imm))
lib/Target/Sparc/SparcISelDAGToDAG.cpp 90 if (isInt<13>(CN->getSExtValue())) {
129 if (isInt<13>(CN->getSExtValue()))
lib/Target/Sparc/SparcISelLowering.cpp 3212 if (isInt<13>(C->getSExtValue()))
3238 if (isInt<13>(C->getSExtValue())) {
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp 198 assert(isUInt<4>(Base) && isInt<20>(Disp));
220 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 391 return isInt<20>(Val);
394 return isInt<20>(Val) && isInt<20>(Val + 8);
394 return isInt<20>(Val) && isInt<20>(Val + 8);
lib/Target/SystemZ/SystemZISelLowering.cpp 913 if (!isInt<20>(AM.BaseOffs))
1039 if (isInt<20>(C->getSExtValue()))
1181 if (isInt<20>(C->getSExtValue()))
lib/Target/SystemZ/SystemZInstrInfo.cpp 1515 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1515 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
lib/Target/SystemZ/SystemZTargetTransformInfo.cpp 220 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
225 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
lib/Target/X86/X86ISelDAGToDAG.cpp 1342 return isInt<31>(Val);
lib/Target/X86/X86TargetTransformInfo.cpp 3080 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
3085 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
tools/lld/COFF/Chunks.cpp 163 if (!isInt<21>(v))
173 if (!isInt<25>(v))
275 if (!isInt<28>(v))
281 if (!isInt<21>(v))
tools/lld/COFF/Writer.cpp 341 return isInt<21>(diff);
344 return isInt<25>(diff);
352 return isInt<28>(diff);
354 return isInt<21>(diff);
tools/lld/ELF/Arch/Mips.cpp 640 if (isInt<18>(val)) {
tools/lld/ELF/Arch/PPC.cpp 187 return isInt<26>(offset);
tools/lld/ELF/Arch/PPC64.cpp 935 return isInt<26>(offset);
tools/lld/ELF/Arch/RISCV.cpp 332 if (isInt<20>(hi)) {
tools/lld/ELF/Thunks.cpp 402 mayUseShortThunk = llvm::isInt<26>(offset);
440 mayUseShortThunk = llvm::isInt<25>(offset);