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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc114906 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
115443 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD ||
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc78791 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/AMDGPU/R600GenDAGISel.inc12354 L->getExtensionType() == ISD::EXTLOAD;
gen/lib/Target/ARC/ARCGenDAGISel.inc 1166 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/ARM/ARMGenDAGISel.inc54283 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
54830 return ScalarVT.isInteger() && Ld->getExtensionType() == ISD::EXTLOAD;
gen/lib/Target/BPF/BPFGenDAGISel.inc 2011 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72298 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1410 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4835 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/Mips/MipsGenDAGISel.inc30104 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44374 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13857 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3531 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc30059 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
30068 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
30378 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc21293 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
gen/lib/Target/X86/X86GenDAGISel.inc253617 return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD ||
253638 if (ExtType == ISD::EXTLOAD)
253652 if (ExtType == ISD::EXTLOAD)
254227 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
254238 if (ExtType != ISD::EXTLOAD)
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2335 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
include/llvm/CodeGen/BasicTTIImpl.h 891 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
include/llvm/CodeGen/SelectionDAGNodes.h 2606 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1106 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1340 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
5192 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
5205 if (Load->getExtensionType() == ISD::EXTLOAD) {
10010 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
10018 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
13090 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
13092 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
13918 case ISD::EXTLOAD:
15885 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValTy, StoreTy) &&
15983 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, LoadDL, ExtendedTy,
16688 ISD::NON_EXTLOAD : ISD::EXTLOAD;
16729 : ISD::EXTLOAD;
19781 LLD->getExtensionType() != ISD::EXTLOAD &&
19782 RLD->getExtensionType() != ISD::EXTLOAD) ||
19884 LLD->getExtensionType() == ISD::EXTLOAD ? RLD->getExtensionType()
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 319 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
334 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
882 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
926 assert(ExtType != ISD::EXTLOAD &&
930 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1341 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1481 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1780 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
2443 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 578 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
596 N->getMemOperand(), ISD::EXTLOAD);
2684 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
4042 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 676 DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
725 case ISD::EXTLOAD:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 2273 ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 332 case ISD::EXTLOAD:
5892 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 649 case ISD::EXTLOAD: OS << ", anyext"; break;
681 case ISD::EXTLOAD: OS << ", anyext"; break;
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6537 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
6696 ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
lib/Target/AArch64/AArch64ISelLowering.cpp 538 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
539 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
540 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
541 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
776 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
857 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
3293 ExtType = ISD::EXTLOAD;
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 109 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
128 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
129 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
130 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
135 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
138 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
141 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
154 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand);
155 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
156 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand);
158 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
160 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
161 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
162 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
163 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
165 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
166 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
168 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
lib/Target/AMDGPU/R600ISelLowering.cpp 83 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
84 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
89 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
93 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1506 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
lib/Target/AMDGPU/SIISelLowering.cpp 1541 ExtType = ISD::EXTLOAD;
7241 case ISD::EXTLOAD:
7301 assert(Ld->getExtensionType() == ISD::EXTLOAD);
7339 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
lib/Target/ARM/ARMISelLowering.cpp 239 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
914 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
985 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
986 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
8948 ISD::EXTLOAD, dl, MVT::i32, LD->getChain(), LD->getBasePtr(),
lib/Target/AVR/AVRISelLowering.cpp 59 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
lib/Target/BPF/BPFISelLowering.cpp 124 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 77 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
133 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
lib/Target/Hexagon/HexagonISelLowering.cpp 1393 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1399 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1450 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1469 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1472 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
lib/Target/Lanai/LanaiISelLowering.cpp 136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
lib/Target/MSP430/MSP430ISelLowering.cpp 61 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
lib/Target/Mips/MipsISelLowering.cpp 316 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
324 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
325 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
332 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
494 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
2596 (ExtType == ISD::EXTLOAD))
lib/Target/Mips/MipsSEISelLowering.cpp 79 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 449 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
450 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
451 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
452 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
453 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
454 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
455 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
456 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
457 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
lib/Target/PowerPC/PPCISelLowering.cpp 666 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
890 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
942 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
5936 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
6486 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
7123 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
9785 ISD::EXTLOAD, dl, MVT::i32, LoadChain, Idx,
12613 return LD->getExtensionType() == ISD::EXTLOAD &&
12731 IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
12754 if (IsRoundOfExtLoad && LD2->getExtensionType() != ISD::EXTLOAD)
lib/Target/RISCV/RISCVISelLowering.cpp 80 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
162 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
177 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
181 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1444 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1448 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1470 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1471 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 993 (Load->getExtensionType() == ISD::EXTLOAD ||
lib/Target/SystemZ/SystemZISelLowering.cpp 280 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
314 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
580 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
584 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
585 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
3645 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 106 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand);
232 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
235 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
243 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
250 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
lib/Target/X86/X86ISelDAGToDAG.cpp 1033 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
1092 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
lib/Target/X86/X86ISelLowering.cpp 386 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
527 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
705 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
706 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
707 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f80, Expand);
795 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
800 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
18887 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
lib/Target/XCore/XCoreISelLowering.cpp 123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
452 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr,
954 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
960 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),