|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/AArch64/AArch64A53Fix835769.cpp 179 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 209 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
222 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
282 BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX))
302 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
315 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
363 BuildMI(LoopBB, DL, TII->get(OpCode))
370 BuildMI(LoopBB, DL, TII->get(AArch64::SUBXri))
375 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
lib/Target/AArch64/AArch64ISelLowering.cpp 1358 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
1359 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
lib/Target/AArch64/AArch64InstrInfo.cpp 376 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
381 BuildMI(&MBB, DL, get(Cond[1].getImm())).add(Cond[2]);
396 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
408 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 401 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
473 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount);
485 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount);
lib/Target/AMDGPU/R600InstrInfo.cpp 767 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
775 BuildMI(&MBB, DL, get(R600::JUMP_COND))
790 BuildMI(&MBB, DL, get(R600::JUMP_COND))
793 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
lib/Target/AMDGPU/SIInsertSkips.cpp 162 BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
lib/Target/AMDGPU/SIInstrInfo.cpp 1813 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2052 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2060 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
2074 BuildMI(&MBB, DL, get(Opcode))
2088 BuildMI(&MBB, DL, get(Opcode))
2090 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
lib/Target/ARC/ARCInstrInfo.cpp 383 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB);
387 MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(BccOpc));
399 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB);
lib/Target/ARM/ARMBaseInstrInfo.cpp 452 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
454 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
456 BuildMI(&MBB, DL, get(BccOpc))
464 BuildMI(&MBB, DL, get(BccOpc))
469 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
471 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
lib/Target/ARM/ARMConstantIslandPass.cpp 911 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
913 BuildMI(OrigBB, DebugLoc(), TII->get(Opc))
1297 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1299 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr))
1524 U.CPEMI = BuildMI(NewIsland, DebugLoc(), CPEMI->getDesc())
1717 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1722 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr))
1726 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1750 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
2437 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B))
2441 BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB))
lib/Target/ARM/ARMExpandPseudoInsts.cpp 975 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
980 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
999 BuildMI(StoreBB, DL, TII->get(CMPri))
1003 BuildMI(StoreBB, DL, TII->get(Bcc))
1085 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1090 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1095 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1101 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1119 BuildMI(StoreBB, DL, TII->get(CMPri))
1123 BuildMI(StoreBB, DL, TII->get(Bcc))
lib/Target/ARM/ARMFrameLowering.cpp 2352 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
2357 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
2369 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2373 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2377 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2450 BuildMI(GetMBB, DL, TII.get(Opcode))
2457 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2495 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
2499 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2510 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2514 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2519 BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
2523 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2530 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2537 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2545 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2557 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2562 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2572 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2576 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
2581 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
2586 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2596 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2603 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2607 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/ARM/ARMISelLowering.cpp 9538 BuildMI(TrapBB, dl, TII->get(trap_opcode));
9558 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
9580 BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
9599 BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
9605 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
9623 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
9636 BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
9652 BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
9656 BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
9662 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
9706 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
9718 BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
9737 BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
9753 BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
9758 BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
9764 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
9791 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
9796 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
10344 BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0));
10513 BuildMI(BB, dl, TII->get(ARM::tBcc))
10552 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
10556 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
10562 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
10566 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
10576 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
10579 BuildMI(BB, dl, TII->get(ARM::t2B))
10583 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
10644 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
10650 BuildMI(BB, dl,
lib/Target/AVR/AVRISelLowering.cpp 1529 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1530 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1555 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1643 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1663 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1664 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1669 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
lib/Target/AVR/AVRInstrInfo.cpp 413 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
422 auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
429 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
568 auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
lib/Target/BPF/BPFISelLowering.cpp 723 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
728 BuildMI(BB, DL, TII.get(NewCC))
lib/Target/BPF/BPFInstrInfo.cpp 233 BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
lib/Target/Hexagon/HexagonInstrInfo.cpp 612 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
624 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
666 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
672 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
lib/Target/Lanai/LanaiInstrInfo.cpp 673 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
681 BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
688 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
lib/Target/MSP430/MSP430ISelLowering.cpp 1496 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1498 BuildMI(BB, dl, TII.get(MSP430::JCC))
1525 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1584 BuildMI(BB, dl, TII.get(MSP430::JCC))
lib/Target/MSP430/MSP430InstrInfo.cpp 280 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
286 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
291 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
lib/Target/Mips/Mips16ISelLowering.cpp 546 BuildMI(BB, DL, TII->get(Opc))
609 BuildMI(BB, DL, TII->get(Opc2))
612 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
675 BuildMI(BB, DL, TII->get(Opc2))
678 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
lib/Target/Mips/MipsConstantIslandPass.cpp 866 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB);
1239 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1388 U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
1618 BuildMI(MBB, DebugLoc(), TII->get(OppositeBranchOpcode))
1622 BuildMI(MBB, DebugLoc(), TII->get(OppositeBranchOpcode))
1627 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
lib/Target/Mips/MipsExpandPseudo.cpp 149 BuildMI(loop1MBB, DL, TII->get(BNE))
167 BuildMI(loop2MBB, DL, TII->get(BEQ))
279 BuildMI(loop1MBB, DL, TII->get(BNE))
289 BuildMI(loop2MBB, DL, TII->get(BEQ))
444 BuildMI(loopMBB, DL, TII->get(BEQ))
608 BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
lib/Target/Mips/MipsISelLowering.cpp 1696 BuildMI(BB, DL, TII->get(AtomicOp))
1883 BuildMI(BB, DL, TII->get(AtomicOp))
4457 BuildMI(BB, DL, TII->get(Opc))
4462 BuildMI(BB, DL, TII->get(Opc))
4532 BuildMI(BB, DL, TII->get(Mips::BNE))
lib/Target/Mips/MipsInstrInfo.cpp 110 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
141 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
148 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
lib/Target/Mips/MipsSEISelLowering.cpp 3062 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3064 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3131 BuildMI(BB, DL, TII->get(BranchOp))
lib/Target/NVPTX/NVPTXInstrInfo.cpp 196 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
205 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
lib/Target/PowerPC/PPCISelLowering.cpp10397 BuildMI(BB, dl, TII->get(PPC::BCC))
10403 BuildMI(BB, dl, TII->get(StoreMnemonic))
10405 BuildMI(BB, dl, TII->get(PPC::BCC))
10580 BuildMI(BB, dl, TII->get(PPC::BCC))
10589 BuildMI(BB, dl, TII->get(PPC::STWCX))
10593 BuildMI(BB, dl, TII->get(PPC::BCC))
10726 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
10731 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
10968 BuildMI(BB, dl, TII->get(PPC::BC))
10973 BuildMI(BB, dl, TII->get(PPC::BCC))
11037 BuildMI(BB, dl, TII->get(PPC::BCC))
11214 BuildMI(BB, dl, TII->get(PPC::BCC))
11222 BuildMI(BB, dl, TII->get(StoreMnemonic))
11226 BuildMI(BB, dl, TII->get(PPC::BCC))
11230 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
11235 BuildMI(BB, dl, TII->get(StoreMnemonic))
11391 BuildMI(BB, dl, TII->get(PPC::BCC))
11405 BuildMI(BB, dl, TII->get(PPC::STWCX))
11409 BuildMI(BB, dl, TII->get(PPC::BCC))
11413 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
11418 BuildMI(BB, dl, TII->get(PPC::STWCX))
lib/Target/PowerPC/PPCInstrInfo.cpp 719 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
721 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
725 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
727 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
729 BuildMI(&MBB, DL, get(PPC::BCC))
738 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
742 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
744 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
746 BuildMI(&MBB, DL, get(PPC::BCC))
750 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 267 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
352 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
470 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
478 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
485 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
491 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
511 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
566 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
576 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
591 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
607 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
lib/Target/RISCV/RISCVISelLowering.cpp 1138 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
1318 BuildMI(HeadMBB, DL, TII.get(Opcode))
lib/Target/RISCV/RISCVInstrInfo.cpp 348 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
357 *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
366 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
lib/Target/Sparc/SparcISelLowering.cpp 3153 BuildMI(ThisMBB, dl, TII.get(BROpcode))
lib/Target/Sparc/SparcInstrInfo.cpp 255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
269 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
lib/Target/SystemZ/SystemZISelLowering.cpp 6684 BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC))
6778 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
6787 BuildMI(MBB, DL, TII->get(StoreOpcode))
6909 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
6991 BuildMI(MBB, DL, TII->get(CompareOpcode))
6993 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7027 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7120 BuildMI(MBB, DL, TII->get(SystemZ::CR))
7122 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7147 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7296 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
7299 BuildMI(MBB, DL, TII->get(Opcode))
7303 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7328 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
7330 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7382 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7446 BuildMI(MBB, DL, TII->get(Opcode))
7449 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
lib/Target/SystemZ/SystemZInstrInfo.cpp 496 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
504 BuildMI(&MBB, DL, get(SystemZ::BRC))
510 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
lib/Target/SystemZ/SystemZPostRewrite.cpp 193 BuildMI(&MBB, DL, TII->get(SystemZ::BRC))
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 969 BuildMI(AppendixBB, DebugLoc(), TII.get(WebAssembly::RETHROW))
1077 BuildMI(EHPadLayoutPred, DL, TII.get(WebAssembly::BR)).addMBB(Cont);
1142 BuildMI(NestedEHPad, RangeEnd->getDebugLoc(), TII.get(WebAssembly::BR))
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 357 BuildMI(Dispatch, DebugLoc(), TII.get(WebAssembly::BR_TABLE_I32));
444 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::BR)).addMBB(Dispatch);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 411 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg);
413 BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR)).addMBB(DoneMBB);
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 188 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
202 BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
207 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
210 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
215 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 309 BuildMI(EHPad, DL, TII.get(WebAssembly::BR_ON_EXN))
313 BuildMI(EHPad, DL, TII.get(WebAssembly::BR)).addMBB(ElseMBB);
346 BuildMI(ElseMBB, DL, TII.get(WebAssembly::CALL_VOID))
349 BuildMI(ElseMBB, DL, TII.get(WebAssembly::UNREACHABLE));
352 BuildMI(ElseMBB, DL, TII.get(WebAssembly::RETHROW)).addReg(ExnReg);
lib/Target/X86/X86CmovConversion.cpp 691 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
lib/Target/X86/X86ExpandPseudo.cpp 170 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64))
lib/Target/X86/X86FrameLowering.cpp 635 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
639 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
676 BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
683 BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
701 BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
710 BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
713 BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
2381 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2410 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2435 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2440 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2453 BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2475 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2477 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2501 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2510 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2513 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2518 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2520 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2693 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2695 BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2698 BuildMI(incStackMBB, DL, TII.get(CALLop)).
2702 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2704 BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
lib/Target/X86/X86ISelLowering.cpp29221 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(fallMBB);
29228 BuildMI(mainMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
29235 BuildMI(fallMBB, DL, TII->get(X86::XABORT_DEF));
29390 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
29396 BuildMI(thisMBB, DL, TII->get(X86::JCC_1))
29433 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
29443 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
29489 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
29553 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
29554 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
29572 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
29836 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
29840 BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
29996 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
30075 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
30078 BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
30086 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
30094 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
30102 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
30110 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
30111 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
30123 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
30612 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
30689 BuildMI(checkSspMBB, DL, TII->get(XorRROpc))
30702 BuildMI(checkSspMBB, DL, TII->get(TestRROpc))
30705 BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30735 BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
30749 BuildMI(fixShadowMBB, DL, TII->get(IncsspOpc)).addReg(SspFirstShrReg);
30758 BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30786 BuildMI(fixShadowLoopMBB, DL, TII->get(IncsspOpc)).addReg(Value128InReg);
30793 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
30991 BuildMI(TrapBB, DL, TII->get(X86::TRAP));
31027 BuildMI(DispatchBB, DL, TII->get(X86::NOOP))
31035 BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
31038 BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
31060 BuildMI(DispContBB, DL, TII->get(X86::JMP64m))
31086 BuildMI(DispContBB, DL, TII->get(X86::JMP64r)).addReg(TReg);
31094 BuildMI(DispContBB, DL, TII->get(X86::JMP32m))
lib/Target/X86/X86InstrInfo.cpp 2784 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2797 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2799 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2810 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2812 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2816 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2822 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
lib/Target/X86/X86RetpolineThunks.cpp 233 addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(MovOpc)), SPReg, false, 0)
259 BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym);
274 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
275 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
276 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
285 BuildMI(CallTarget, DebugLoc(), TII->get(RetOpc));
lib/Target/X86/X86SpeculativeLoadHardening.cpp 254 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc);
lib/Target/XCore/XCoreISelLowering.cpp 1559 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
lib/Target/XCore/XCoreInstrInfo.cpp 286 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
301 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
tools/llvm-exegesis/lib/Assembler.cpp 96 MachineInstrBuilder Builder = BuildMI(MBB, DL, MCID);
127 BuildMI(MBB, DL, TII->get(TII->getReturnOpcode()));
tools/llvm-exegesis/lib/X86/Target.cpp 654 BuildMI(&MBB, DebugLoc(), MII.get(X86::ADD64ri8))
658 BuildMI(&MBB, DebugLoc(), MII.get(X86::JCC_1))