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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc78770 if (cast<MemSDNode>(N)->getAlignment() < 8)
78780 if (cast<MemSDNode>(N)->getAlignment() < 8)
79021 if (cast<MemSDNode>(N)->getAlignment() < 16)
79031 if (cast<MemSDNode>(N)->getAlignment() < 16)
79071 if (cast<MemSDNode>(N)->getAlignment() < 8)
79082 if (cast<MemSDNode>(N)->getAlignment() < 16)
gen/lib/Target/ARM/ARMGenDAGISel.inc54369 return cast<StoreSDNode>(N)->getAlignment() >= 4;
54387 return cast<StoreSDNode>(N)->getAlignment() == 2;
54395 return cast<StoreSDNode>(N)->getAlignment() == 1;
54403 return cast<StoreSDNode>(N)->getAlignment() < 4;
54413 return cast<StoreSDNode>(N)->getAlignment() >= 2;
54421 return cast<StoreSDNode>(N)->getAlignment() >= 8;
54429 return cast<StoreSDNode>(N)->getAlignment() == 4;
54517 return cast<LoadSDNode>(N)->getAlignment() >= 4;
54525 return cast<LoadSDNode>(N)->getAlignment() >= 2;
54533 return cast<LoadSDNode>(N)->getAlignment() == 2;
54541 return cast<LoadSDNode>(N)->getAlignment() == 1;
54549 return cast<LoadSDNode>(N)->getAlignment() < 4;
54587 return cast<LoadSDNode>(N)->getAlignment() >= 8;
54595 return cast<LoadSDNode>(N)->getAlignment() == 4;
54683 return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
54702 return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && St->getAlignment() >= 4;
54801 return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && Ld->getAlignment() >= 2;
54840 return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && Ld->getAlignment() >= 4;
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72578 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
72851 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44231 return cast<StoreSDNode>(N)->getAlignment() >= 4;
44239 return cast<StoreSDNode>(N)->getAlignment() < 4;
44384 return cast<LoadSDNode>(N)->getAlignment() >= 4;
44393 return cast<LoadSDNode>(N)->getAlignment() < 4;
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc30041 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
30256 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
gen/lib/Target/X86/X86GenDAGISel.inc253599 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
253639 return LD->getAlignment() >= 2 && LD->isSimple();
253653 return LD->getAlignment() >= 4 && LD->isSimple();
253794 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
253839 return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize();
253946 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
254243 return LD->getAlignment() >= 4 && LD->isSimple();
254253 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
254270 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
254439 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
254517 return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize();
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 6611 FirstStore->getPointerInfo(), FirstStore->getAlignment());
6765 FirstLoad->getPointerInfo(), FirstLoad->getAlignment());
9123 const unsigned Align = MinAlign(LN0->getAlignment(), Offset);
10309 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
10878 unsigned Align = LD1->getAlignment();
11011 LN0->getPointerInfo(), LN0->getAlignment(),
14102 if (Align > LD->getAlignment() && LD->getSrcValueOffset() % Align == 0) {
14303 unsigned Alignment = Origin->getAlignment();
14810 unsigned NewAlign = St->getAlignment();
14927 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
14985 unsigned LDAlign = LD->getAlignment();
14986 unsigned STAlign = ST->getAlignment();
15238 FirstInChain->getAlignment());
15250 FirstInChain->getAlignment(),
15587 unsigned FirstStoreAlign = FirstInChain->getAlignment();
15674 (StoreNodes[NumSkip].MemNode->getAlignment() <= FirstStoreAlign))
15707 unsigned FirstStoreAlign = FirstInChain->getAlignment();
15740 (StoreNodes[NumSkip].MemNode->getAlignment() <= FirstStoreAlign))
15805 StoreNodes[0].MemNode->getAlignment() >= RequiredAlignment) {
15812 unsigned FirstStoreAlign = FirstInChain->getAlignment();
15814 unsigned FirstLoadAlign = FirstLoad->getAlignment();
15922 (LoadNodes[NumSkip].MemNode->getAlignment() <= FirstLoadAlign) &&
15923 (StoreNodes[NumSkip].MemNode->getAlignment() <= FirstStoreAlign))
15990 JointMemOpVT, FirstInChain->getAlignment(),
16103 unsigned Alignment = ST->getAlignment();
16108 ST->getAlignment(), MMOFlags, AAInfo);
16145 ST->getPointerInfo(), ST->getAlignment(),
16157 if (Align > ST->getAlignment() && ST->getSrcValueOffset() % Align == 0) {
16471 unsigned Alignment = ST->getAlignment();
16484 ST->getAlignment(), MMOFlags, AAInfo);
16680 unsigned Align = OriginalLoad->getAlignment();
19870 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
19870 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 434 unsigned Alignment = ST->getAlignment();
488 unsigned Alignment = ST->getAlignment();
724 unsigned Alignment = LD->getAlignment();
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 730 L->getPointerInfo(), NVT, L->getAlignment(), MMOFlags,
742 L->getPointerInfo(), L->getMemoryVT(), L->getAlignment(),
2282 L->getAlignment(),
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 2657 unsigned Alignment = N->getAlignment();
3901 unsigned Alignment = N->getAlignment();
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 255 unsigned Alignment = LD->getAlignment();
466 unsigned Alignment = St->getAlignment();
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 667 MinAlign(LD->getAlignment(), Offset),
678 MinAlign(LD->getAlignment(), Offset),
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 777 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
4776 unsigned Align = LD->getAlignment();
4926 unsigned Align = LD->getAlignment();
4966 unsigned Align = ST->getAlignment();
5034 unsigned Align = ST->getAlignment();
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 6814 LD->getMemoryVT(), LD->getAlignment(), MMOFlags,
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3280 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
6371 SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
6432 ST->getAlignment(), ST->getMemOperand()->getFlags(),
6451 MemSclVT, MinAlign(ST->getAlignment(), Idx * Stride),
6520 MinAlign(LD->getAlignment(), Offset), LD->getMemOperand()->getFlags(),
6539 MinAlign(LD->getAlignment(), Offset),
6570 unsigned Alignment = LD->getAlignment();
6623 int Alignment = ST->getAlignment();
6680 MinAlign(ST->getAlignment(), Offset),
6702 MinAlign(ST->getAlignment(), Offset),
lib/Target/AArch64/AArch64ISelLowering.cpp 2945 unsigned Align = StoreNode->getAlignment();
9545 LN0->getPointerInfo(), LN0->getAlignment(),
10627 unsigned OrigAlignment = St.getAlignment();
10835 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
10836 S->getAlignment() <= 2)
10857 S->getAlignment(), S->getMemOperand()->getFlags());
10861 S->getPointerInfo(), S->getAlignment(),
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2684 return Ld->getAlignment() >= 4 &&
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 658 if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
1424 unsigned BaseAlign = Load->getAlignment();
1466 unsigned BaseAlign = Load->getAlignment();
1509 unsigned BaseAlign = Store->getAlignment();
2858 unsigned Align = LN->getAlignment();
2910 unsigned Align = SN->getAlignment();
lib/Target/AMDGPU/R600ISelLowering.cpp 1148 assert(Store->getAlignment() >= 1);
1151 assert(Store->getAlignment() >= 2);
1255 MemVT, StoreNode->getAlignment(),
1263 unsigned Align = StoreNode->getAlignment();
1283 assert(StoreNode->getAlignment() >= 2);
1390 assert(Load->getAlignment() >= MemVT.getStoreSize());
1507 LoadNode->getAlignment(), LoadNode->getMemOperand()->getFlags());
1813 if (LoadNode->getAlignment() < 4)
lib/Target/AMDGPU/SIISelLowering.cpp 7252 if (Ld->getAlignment() < 4 || Ld->isDivergent())
7281 Ld->getAlignment(),
7380 unsigned Alignment = Load->getAlignment();
7466 if (Subtarget->useDS128() && Load->getAlignment() >= 16 &&
7480 Load->getAlignment() < 8) {
7883 Store->getAlignment() < VT.getStoreSize() && VT.getSizeInBits() > 32) {
7921 if (Subtarget->useDS128() && Store->getAlignment() >= 16 &&
7935 Store->getAlignment() < 8) {
lib/Target/ARM/ARMISelDAGToDAG.cpp 1001 unsigned MMOAlign = MemN->getAlignment();
1009 Alignment = MemN->getAlignment();
1638 unsigned Align = LD->getAlignment();
lib/Target/ARM/ARMISelLowering.cpp 5084 Ld->getPointerInfo(), Ld->getAlignment(),
5104 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5107 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
8334 LD->getAlignment(), LD->getMemOperand()->getFlags());
8341 LD->getMemoryVT(), LD->getAlignment(),
12594 LD->getAlignment(), LD->getMemOperand()->getFlags());
12601 std::min(4U, LD->getAlignment()),
12990 unsigned Alignment = MemN->getAlignment();
13226 DAG.getConstant(LD->getAlignment(), SDLoc(N), MVT::i32) };
13327 St->getAlignment(), St->getMemOperand()->getFlags());
13421 BasePtr, St->getPointerInfo(), St->getAlignment(),
13429 std::min(4U, St->getAlignment() / 2),
13453 St->getPointerInfo(), St->getAlignment(),
15271 Align = LD->getAlignment();
15276 Align = ST->getAlignment();
15317 Align = LD->getAlignment();
15323 Align = ST->getAlignment();
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1563 return N->getAlignment() >= N->getMemoryVT().getStoreSize();
lib/Target/Hexagon/HexagonISelLowering.cpp 2632 unsigned ClaimAlign = LN->getAlignment();
2642 unsigned ClaimAlign = SN->getAlignment();
2660 unsigned HaveAlign = LN->getAlignment();
lib/Target/Mips/MipsISelDAGToDAG.cpp 300 cast<MemSDNode>(Node)->getAlignment()) &&
lib/Target/Mips/MipsISelLowering.cpp 2560 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2674 SD->getPointerInfo(), SD->getAlignment(),
2684 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
lib/Target/Mips/MipsSEISelLowering.cpp 1186 Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1192 std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1222 DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1228 std::min(Nd.getAlignment(), 4U),
lib/Target/NVPTX/NVPTXISelLowering.cpp 2256 LD->getPointerInfo(), LD->getAlignment(),
2322 unsigned Align = MemSD->getAlignment();
2421 ST->getAlignment(), ST->getMemOperand()->getFlags());
4812 unsigned Align = LD->getAlignment();
lib/Target/PowerPC/PPCISelLowering.cpp 2556 Alignment = LD->getAlignment();
2560 Alignment = ST->getAlignment();
7539 RLI.Alignment = LD->getAlignment();
9721 unsigned Alignment = LN->getAlignment();
9810 unsigned Alignment = SN->getAlignment();
12782 LD1->getAlignment());
12788 LDL->getAlignment());
13593 LD->getPointerInfo(), LD->getAlignment(),
13601 MinAlign(LD->getAlignment(), 4), MMOFlags, LD->getAAInfo());
13631 LD->getAlignment() >= ScalarABIAlignment)) &&
13632 LD->getAlignment() < ABIAlignment) {
lib/Target/Sparc/SparcISelLowering.cpp 2732 unsigned alignment = LdNode->getAlignment();
2799 unsigned alignment = StNode->getAlignment();
2831 St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo());
3397 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(),
lib/Target/SystemZ/SystemZISelLowering.cpp 2037 Load->getMemoryVT(), Load->getAlignment(),
lib/Target/X86/X86ISelDAGToDAG.cpp 492 if (N->getAlignment() < StoreSize)
lib/Target/X86/X86ISelLowering.cpp 7904 LDBase->getPointerInfo(), LDBase->getAlignment(), MMOFlags);
7928 if (LDBase->isNonTemporal() && LDBase->getAlignment() >= 32 &&
7988 LDBase->getAlignment(),
21783 unsigned Alignment = Store->getAlignment();
21812 unsigned Alignment = Store->getAlignment();
21852 St->getPointerInfo(), St->getAlignment(),
21891 St->getPointerInfo(), St->getAlignment(),
21926 Ld->getPointerInfo(), Ld->getAlignment(),
28526 Ld->getPointerInfo(), Ld->getAlignment(),
34244 LN->getAlignment(),
35154 unsigned Align = LN0->getAlignment();
36073 MemIntr->getAlignment(),
40216 unsigned Alignment = Ld->getAlignment();
40319 Alignment = MinAlign(MaskedOp->getAlignment(), EltVT.getStoreSize());
40494 unsigned Alignment = St->getAlignment();
40507 St->getPointerInfo(), St->getAlignment(),
40518 St->getAlignment(), St->getMemOperand()->getFlags());
40529 St->getPointerInfo(), St->getAlignment(),
40562 St->getPointerInfo(), St->getAlignment(),
40635 St->getPointerInfo(), St->getAlignment(),
40703 Ld->getPointerInfo(), Ld->getAlignment(),
40707 MinAlign(Ld->getAlignment(), 4),
40718 St->getAlignment(), St->getMemOperand()->getFlags());
40721 MinAlign(St->getAlignment(), 4),
40742 St->getPointerInfo(), St->getAlignment(),
42006 LN->getAlignment(),
42041 LN->getAlignment(),
44857 Ld->getPointerInfo(), MemVT, Ld->getAlignment(),
lib/Target/XCore/XCoreISelLowering.cpp 444 if (LD->getAlignment() == 2) {
500 if (ST->getAlignment() == 2) {
944 if (N->getAlignment() < 4)
948 N->getAlignment(), N->getMemOperand()->getFlags(),
952 if (N->getAlignment() < 2)
956 N->getAlignment(), N->getMemOperand()->getFlags(),
962 N->getAlignment(), N->getMemOperand()->getFlags(),
975 if (N->getAlignment() < 4)
978 N->getPointerInfo(), N->getAlignment(),
982 if (N->getAlignment() < 2)
986 N->getAlignment(), N->getMemOperand()->getFlags(),
992 N->getAlignment(), N->getMemOperand()->getFlags(),
1794 unsigned Alignment = ST->getAlignment();
1798 LD->getAlignment() == Alignment &&