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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/SelectionDAG.h 1381 switch (VT.getScalarType().getSimpleVT().SimpleTy) {
include/llvm/CodeGen/SelectionDAGNodes.h 169 return getValueType().getSimpleVT();
1021 return getValueType(ResNo).getSimpleVT();
include/llvm/CodeGen/TargetCallingConv.h 177 VT = vt.getSimpleVT();
216 VT = vt.getSimpleVT();
include/llvm/CodeGen/TargetLowering.h 414 MVT LoadMVT = LoadVT.getSimpleVT();
419 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
742 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
743 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
897 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
1098 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1099 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1123 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1124 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1158 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1159 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1176 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1177 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1279 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1296 assert((unsigned)VT.getSimpleVT().SimpleTy <
1298 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1324 assert((unsigned)VT.getSimpleVT().SimpleTy <
1326 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
include/llvm/CodeGen/ValueTypes.h 101 MVT EltTy = getSimpleVT().getVectorElementType();
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 3494 switch (NodeType.getSimpleVT().SimpleTy) {
3980 MVT Simple = VT.getSimpleVT();
4036 MVT Simple = VT.getSimpleVT();
4112 MVT Simple = VT.getSimpleVT();
4155 MVT Simple = VT.getSimpleVT();
14427 TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent());
14429 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT(),
lib/CodeGen/SelectionDAG/FastISel.cpp 371 MVT VT = RealVT.getSimpleVT();
375 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
434 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
519 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
524 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
614 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
615 CI->getZExtValue(), VT.getSimpleVT());
647 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
648 Op0IsKill, Imm, VT.getSimpleVT());
663 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
663 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
1513 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1513 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1540 MVT SrcVT = SrcEVT.getSimpleVT();
1541 MVT DstVT = DstEVT.getSimpleVT();
1716 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1716 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1731 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1731 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1737 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true,
1738 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1742 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1742 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1761 MVT VT = RealVT.getSimpleVT();
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 315 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
854 SrcVT.getSimpleVT())) {
885 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
909 EVT ILoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
2168 switch (Node->getOperand(0).getValueType().getSimpleVT().SimpleTy) {
2418 switch (SrcVT.getSimpleVT().SimpleTy) {
2469 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2510 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2606 switch (VT.getSimpleVT().getScalarType().SimpleTy) {
3792 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 144 CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) {
1039 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1056 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1073 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1090 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1593 switch (SrcVT.getSimpleVT().SimpleTy) {
1829 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1842 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1855 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1868 EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1815 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2590 EVT VT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
2618 EVT VT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
4292 MVT InVT = V0.getValueType().getSimpleVT();
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 876 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != nullptr;
877 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = nullptr;
1509 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >=
1511 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1);
1514 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
2097 if (!TLI->isCondCodeLegal(SwappedCond, OpVT.getSimpleVT()))
5326 assert(VT.getSimpleVT() <= N1.getSimpleValueType() &&
5336 if (VT.getSimpleVT() == N1.getSimpleValueType())
5544 if (VT.getSimpleVT() == N2.getSimpleValueType())
8879 assert(VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
8881 return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy];
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 2648 B.RegVT = VT.getSimpleVT();
8085 .getSimpleVT();
9759 MVT VT = ValueVTs[0].getSimpleVT();
lib/CodeGen/SelectionDAG/TargetLowering.cpp 202 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
229 isSafeMemOpType(NewVT.getSimpleVT()))
242 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1);
245 } while (!isSafeMemOpType(NewVT.getSimpleVT()));
3334 isCondCodeLegal(Cond, newVT.getSimpleVT()))) {
3510 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
3530 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
lib/CodeGen/TargetLoweringBase.cpp 829 MVT SVT = VT.getSimpleVT();
916 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
939 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1410 RegisterVT = RegisterEVT.getSimpleVT();
1663 return std::make_pair(Cost, MTy.getSimpleVT());
1670 return std::make_pair(Cost, MTy.getSimpleVT());
lib/Target/AArch64/AArch64FastISel.cpp 528 MVT VT = CEVT.getSimpleVT();
986 VT = evt.getSimpleVT();
1490 MVT VT = EVT.getSimpleVT();
2926 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2986 MVT VT = ArgVT.getSimpleVT().SimpleTy;
3906 MVT RVVT = RVEVT.getSimpleVT();
3952 MVT SrcVT = SrcEVT.getSimpleVT();
3953 MVT DestVT = DestEVT.getSimpleVT();
4637 MVT DestVT = DestEVT.getSimpleVT();
5002 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false);
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1354 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1370 MVT EltTy = VT.getVectorElementType().getSimpleVT();
lib/Target/AArch64/AArch64ISelLowering.cpp 821 MVT PromoteTo = EVT(VT).changeVectorElementTypeToInteger().getSimpleVT();
1102 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
2620 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
3166 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
3787 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
6224 MVT EltTy = VT.getVectorElementType().getSimpleVT();
6244 MVT EltTy = VT.getVectorElementType().getSimpleVT();
7086 switch (ElemVT.getSimpleVT().SimpleTy) {
9194 switch (VT.getSimpleVT().SimpleTy) {
9920 if (VT.getSimpleVT().getSizeInBits() != 64)
10035 MVT RHSTy = RHS.getValueType().getSimpleVT();
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 391 DstTy.getSimpleVT(),
392 SrcTy.getSimpleVT()))
613 SelCondTy.getSimpleVT(),
614 SelValTy.getSimpleVT()))
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 400 MVT VT = N->getValueType(0).getSimpleVT();
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 599 MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
1011 MemVT.getSimpleVT(),
lib/Target/AMDGPU/R600ISelLowering.cpp 977 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
982 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1011 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1018 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
lib/Target/AMDGPU/SIISelLowering.cpp 788 return ScalarVT.getSimpleVT();
835 RegisterVT = ScalarVT.getSimpleVT();
3919 switch (VT.getSimpleVT().SimpleTy) {
4965 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
5385 MVT LoadVT = ResultTypes[0].getSimpleVT();
5663 MVT LoadVT = VT.getSimpleVT();
7989 MVT SimpleVT = VT.getSimpleVT();
10184 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();
10324 MVT VT = Src0.getValueType().getSimpleVT();
10881 switch (VT.getScalarType().getSimpleVT().SimpleTy) {
lib/Target/ARC/ARCISelLowering.cpp 486 switch (RegVT.getSimpleVT().SimpleTy) {
489 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
lib/Target/ARM/ARMCallLowering.cpp 75 unsigned VTSize = VT.getSimpleVT().getSizeInBits();
lib/Target/ARM/ARMFastISel.cpp 647 MVT VT = CEVT.getSimpleVT();
694 VT = evt.getSimpleVT();
1355 MVT SrcVT = SrcEVT.getSimpleVT();
1550 MVT SrcVT = SrcEVT.getSimpleVT();
1792 MVT VT = FPVT.getSimpleVT();
2139 MVT RVVT = RVEVT.getSimpleVT();
2194 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2755 MVT SrcVT = SrcEVT.getSimpleVT();
2756 MVT DestVT = DestEVT.getSimpleVT();
3041 switch (ArgVT.getSimpleVT().SimpleTy) {
lib/Target/ARM/ARMISelDAGToDAG.cpp 1553 LoadedVT.getSimpleVT().SimpleTy != MVT::i32)
1588 switch (LoadedVT.getSimpleVT().SimpleTy) {
1941 switch (VT.getSimpleVT().SimpleTy) {
2083 switch (VT.getSimpleVT().SimpleTy) {
2250 switch (VT.getSimpleVT().SimpleTy) {
2534 switch (VT.getSimpleVT().SimpleTy) {
3471 switch (VT.getSimpleVT().SimpleTy) {
3494 switch (VT.getSimpleVT().SimpleTy) {
3517 switch (VT.getSimpleVT().SimpleTy) {
lib/Target/ARM/ARMISelLowering.cpp 4522 switch (VT.getSimpleVT().SimpleTy) {
6525 switch (VT.getSimpleVT().SimpleTy) {
7243 MVT FVT = VT.getVectorElementType().getSimpleVT();
7711 switch (VT.getSimpleVT().SimpleTy) {
8119 MVT ElType = getVectorTyFromPredicateVector(VT).getScalarType().getSimpleVT();
8194 MVT ElType = getVectorTyFromPredicateVector(VT).getScalarType().getSimpleVT();
8291 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
11124 switch (inputLaneType.getSimpleVT().SimpleTy) {
14578 auto Ty = VT.getSimpleVT().SimpleTy;
14701 switch (VT1.getSimpleVT().SimpleTy) {
14722 switch (VT.getSimpleVT().SimpleTy) {
14866 switch (VT.getSimpleVT().SimpleTy) {
14907 switch (VT.getSimpleVT().getVectorElementType().SimpleTy) {
14957 switch (VT.getSimpleVT().SimpleTy) {
14981 switch (VT.getSimpleVT().SimpleTy) {
15059 switch (VT.getSimpleVT().SimpleTy) {
15991 VT.getSimpleVT().SimpleTy);
16022 switch (N->getValueType(0).getSimpleVT().SimpleTy) {
16035 RTLIB::Libcall LC = getDivRemLibcall(N, N->getValueType(0).getSimpleVT().
lib/Target/ARM/ARMTargetTransformInfo.cpp 191 LoadConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
191 LoadConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
205 DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
205 DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
290 DstTy.getSimpleVT(),
291 SrcTy.getSimpleVT()))
320 DstTy.getSimpleVT(),
321 SrcTy.getSimpleVT()))
351 ISD, DstTy.getSimpleVT(),
352 SrcTy.getSimpleVT()))
376 ISD, DstTy.getSimpleVT(),
377 SrcTy.getSimpleVT()))
395 DstTy.getSimpleVT(),
396 SrcTy.getSimpleVT()))
458 SelCondTy.getSimpleVT(),
459 SelValTy.getSimpleVT()))
lib/Target/AVR/AVRISelDAGToDAG.cpp 107 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT();
124 MVT VT = LD->getMemoryVT().getSimpleVT();
371 MVT VT = LD->getMemoryVT().getSimpleVT();
lib/Target/AVR/AVRISelLowering.cpp 348 switch (VT.getSimpleVT().SimpleTy) {
1963 if (Ty.getSimpleVT() == MVT::i8) {
lib/Target/BPF/BPFISelLowering.cpp 230 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy;
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 81 switch (LoadedVT.getSimpleVT().SimpleTy) {
477 switch (StoredVT.getSimpleVT().SimpleTy) {
771 MVT ResTy = N->getValueType(0).getSimpleVT();
826 MVT OpTy = Op.getValueType().getSimpleVT();
833 MVT ResTy = N->getValueType(0).getSimpleVT();
841 MVT ResTy = N->getValueType(0).getSimpleVT();
850 MVT ResTy = N->getValueType(0).getSimpleVT();
852 MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
864 MVT ResTy = N->getValueType(0).getSimpleVT();
1163 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1)
1170 if (!UVT.isSimple() || !UVT.isInteger() || UVT.getSimpleVT() == MVT::i1)
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 672 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {}
1008 MVT OpTy = Op.getValueType().getSimpleVT();
1390 MVT LegalTy = Lower.getTypeToTransformTo(Ctx, ElemTy).getSimpleVT();
2006 MVT ResTy = N->getValueType(0).getSimpleVT();
2078 MVT Ty = N->getValueType(0).getSimpleVT();
lib/Target/Hexagon/HexagonISelLowering.cpp 558 Subtarget.isHVXVectorType(VT.getSimpleVT());
1847 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1847 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
2647 MVT StoreTy = SN->getMemoryVT().getSimpleVT();
3199 return Subtarget.isHVXVectorType(VT.getSimpleVT());
lib/Target/Hexagon/HexagonISelLowering.h 376 return Op.getValueType().getSimpleVT();
379 return { Ops.first.getValueType().getSimpleVT(),
380 Ops.second.getValueType().getSimpleVT() };
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 247 MVT CastTy = tyVector(Vec.getValueType().getSimpleVT(), ElemTy);
282 if (ElemIdx.getValueType().getSimpleVT() != MVT::i32)
1448 MVT Ty = typeSplit(N->getVT().getSimpleVT()).first;
1478 MVT MemTy = BN->getMemoryVT().getSimpleVT();
lib/Target/Hexagon/HexagonInstrInfo.cpp 2643 switch (VT.getSimpleVT().SimpleTy) {
lib/Target/Hexagon/HexagonTargetTransformInfo.cpp 56 if (ST.isHVXVectorType(VecVT.getSimpleVT()))
58 auto Action = TLI.getPreferredVectorAction(VecVT.getSimpleVT());
lib/Target/Lanai/LanaiISelLowering.cpp 461 switch (RegVT.getSimpleVT().SimpleTy) {
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 308 switch (VT.getSimpleVT().SimpleTy) {
333 MVT VT = LD->getMemoryVT().getSimpleVT();
362 MVT VT = LD->getMemoryVT().getSimpleVT();
lib/Target/MSP430/MSP430ISelLowering.cpp 628 switch (RegVT.getSimpleVT().SimpleTy) {
lib/Target/Mips/MipsFastISel.cpp 453 MVT VT = CEVT.getSimpleVT();
601 VT = evt.getSimpleVT();
1374 switch (ArgVT.getSimpleVT().SimpleTy) {
1743 MVT RVVT = RVEVT.getSimpleVT();
1822 MVT SrcVT = SrcEVT.getSimpleVT();
1823 MVT DestVT = DestEVT.getSimpleVT();
1923 MVT DestVT = DestEVT.getSimpleVT();
1984 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
2100 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 1188 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1255 MVT ResVecTySimple = ResVecTy.getSimpleVT();
lib/Target/Mips/MipsSEISelLowering.cpp 425 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
1235 MVT Src = Op.getOperand(0).getValueType().getSimpleVT();
1236 MVT Dest = Op.getValueType().getSimpleVT();
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 885 MVT SimpleVT = LoadedVT.getSimpleVT();
1023 MVT SimpleVT = LoadedVT.getSimpleVT();
1076 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1084 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_avar,
1103 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1111 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_asi,
1132 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_ari_64,
1140 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari_64,
1151 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1159 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari,
1180 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_areg_64,
1188 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_areg_64,
1200 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_areg,
1208 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_areg,
1298 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1308 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1320 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1331 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1343 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1352 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1374 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1384 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1396 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1407 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1419 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1428 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1444 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1454 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1466 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1477 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1489 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1498 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1520 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1530 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1542 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1553 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1565 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1574 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1590 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1600 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1612 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1623 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1635 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1644 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1682 unsigned CvtOpc = GetConvertOpcode(OrigType.getSimpleVT(),
1683 EltVT.getSimpleVT(), IsSigned);
1743 MVT SimpleVT = StoreVT.getSimpleVT();
1901 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
1954 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1962 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_avar,
1975 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
1983 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_asi,
1999 EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v2_ari_64,
2007 EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_ari_64,
2018 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
2026 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_ari,
2042 EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v2_areg_64,
2050 EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg_64,
2062 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v2_areg,
2070 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg,
2125 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy,
2133 pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, NVPTX::LoadParamMemV2I8,
2141 MemVT.getSimpleVT().SimpleTy, NVPTX::LoadParamMemV4I8,
2209 Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
2216 Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
2223 Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
2288 Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
2295 Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
2302 Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
lib/Target/NVPTX/NVPTXISelLowering.cpp 2299 switch (ValVT.getSimpleVT().SimpleTy) {
4790 switch (ResVT.getSimpleVT().SimpleTy) {
5022 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
lib/Target/PowerPC/PPCFastISel.cpp 279 VT = Evt.getSimpleVT();
828 MVT SrcVT = SrcEVT.getSimpleVT();
1078 MVT SrcVT = SrcEVT.getSimpleVT();
1750 MVT RVVT = RVEVT.getSimpleVT();
1914 MVT SrcVT = SrcEVT.getSimpleVT();
1915 MVT DestVT = DestEVT.getSimpleVT();
2246 MVT VT = CEVT.getSimpleVT();
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 641 switch (MemVT.getSimpleVT().SimpleTy) {
683 switch (MemVT.getSimpleVT().SimpleTy) {
4109 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
4494 switch (LoadedVT.getSimpleVT().SimpleTy) {
4506 switch (LoadedVT.getSimpleVT().SimpleTy) {
4531 switch (LoadedVT.getSimpleVT().SimpleTy) {
4546 switch (LoadedVT.getSimpleVT().SimpleTy) {
lib/Target/PowerPC/PPCISelLowering.cpp 2511 switch(MemVT.getSimpleVT().SimpleTy) {
3485 switch (ValVT.getSimpleVT().SimpleTy) {
3892 switch (ObjectVT.getSimpleVT().SimpleTy) {
4013 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
4021 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
4024 switch (ObjectVT.getSimpleVT().SimpleTy) {
4167 switch(ObjectVT.getSimpleVT().SimpleTy) {
4293 switch (ObjectVT.getSimpleVT().SimpleTy) {
5765 switch (ArgVT.getSimpleVT().SimpleTy) {
6219 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
6225 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
13030 if (Op.getOperand(0).getValueType().getSimpleVT() <= MVT(MVT::i1) ||
13031 Op.getOperand(0).getValueType().getSimpleVT() > MVT(MVT::i64))
13153 MVT VecTy = N->getValueType(0).getSimpleVT();
13224 MVT VecTy = Src.getValueType().getSimpleVT();
13493 MVT StoreVT = Op1VT.getSimpleVT();
13508 MVT LoadVT = VT.getSimpleVT();
13680 LDTy = MemVT.getSimpleVT();
14927 if (VT.getSimpleVT().isVector()) {
14952 switch (VT.getSimpleVT().SimpleTy) {
15086 switch(VT.getSimpleVT().SimpleTy) {
lib/Target/RISCV/RISCVISelLowering.cpp 1695 switch (LocVT.getSimpleVT().SimpleTy) {
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1157 if (VCI.VecVT == VT.getSimpleVT())
lib/Target/SystemZ/SystemZISelLowering.cpp 57 switch (VT.getSimpleVT().SimpleTy) {
652 switch (VT.getSimpleVT().SimpleTy) {
1324 switch (LocVT.getSimpleVT().SimpleTy) {
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 119 return VT.isSimple() ? VT.getSimpleVT().SimpleTy
1144 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
1144 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 754 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
755 Offset, VT.getSimpleVT(),
1266 .getSimpleVT();
lib/Target/X86/X86FastISel.cpp 297 VT = evt.getSimpleVT();
495 switch (VT.getSimpleVT().SimpleTy) {
667 switch (VT.getSimpleVT().SimpleTy) {
707 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
707 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1241 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
1241 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
1344 switch (VT.getSimpleVT().SimpleTy) {
1367 switch (VT.getSimpleVT().SimpleTy) {
1568 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
1614 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND,
2448 MVT DstVT = TLI.getValueType(DL, I->getType()).getSimpleVT();
3096 switch (ArgVT.getSimpleVT().SimpleTy) {
3853 MVT VT = CEVT.getSimpleVT();
lib/Target/X86/X86ISelDAGToDAG.cpp 2993 switch (MemVT.getSimpleVT().SimpleTy) {
lib/Target/X86/X86ISelLowering.cpp 2010 if (LegalVT.getSimpleVT().is512BitVector())
2013 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
2017 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
2798 switch (ValVT.getSimpleVT().SimpleTy) {
7220 SrcVT = MVT::getVectorVT(SrcVT.getSimpleVT().getScalarType(),
9304 IndicesVec = widenSubVector(IndicesVT.getSimpleVT(), IndicesVec, false,
9377 getZeroVector(IndicesVT.getSimpleVT(), Subtarget, DAG, DL),
18930 assert(DstTy.getSimpleVT() <= MVT::i64 &&
18931 DstTy.getSimpleVT() >= MVT::i16 &&
27978 MVT WidenVT = getTypeToTransformTo(*DAG.getContext(), VT).getSimpleVT();
27987 MVT InEltVT = InVT.getSimpleVT().getVectorElementType();
28146 MVT ConcatVT = MVT::getVectorVT(VT.getSimpleVT().getVectorElementType(),
28191 MVT VecInVT = MVT::getVectorVT(SrcVT.getSimpleVT(), NumElts);
29077 switch (VT1.getSimpleVT().SimpleTy) {
29112 switch (VT.getSimpleVT().SimpleTy) {
29137 if (VT.getSimpleVT().getScalarType() == MVT::i1)
29141 if (VT.getSimpleVT().getSizeInBits() == 64)
29146 return isTypeLegal(VT.getSimpleVT());
31621 if (getTargetShuffleMask(Op.getNode(), VT.getSimpleVT(), true, Ops, Mask,
31759 if (getTargetShuffleMask(Op.getNode(), VT.getSimpleVT(), true, Ops, Mask,
33842 !VT.getSimpleVT().isFloatingPoint())
34228 getZeroVector(VT.getSimpleVT(), Subtarget, DAG, dl),
34498 Src = widenSubVector(VT.getSimpleVT(), Src, false, Subtarget, TLO.DAG,
34628 MVT ExtVT = VT.getSimpleVT();
34676 Op, getZeroVector(VT.getSimpleVT(), Subtarget, TLO.DAG, SDLoc(Op)));
35029 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(Op));
35100 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(), true,
35247 switch (SrcVT.getSimpleVT().SimpleTy) {
38483 return getConstVector(Bits, Undefs, VT.getSimpleVT(), DAG, SDLoc(N));
38532 return getTargetVShiftByConstNode(X86Opc, SDLoc(N), VT.getSimpleVT(), N0,
38613 return getConstVector(EltBits, UndefElts, VT.getSimpleVT(), DAG, SDLoc(N));
38904 if (!SupportedVectorShiftWithImm(VT0.getSimpleVT(), Subtarget, ISD::SRL))
39832 switch (VT.getSimpleVT().SimpleTy) {
41122 MVT VT = N->getValueType(0).getSimpleVT();
41125 MVT InVT = In.getValueType().getSimpleVT();
44392 if (SDValue R = combineConcatVectorOps(SDLoc(N), VT.getSimpleVT(), Ops, DAG,
45197 if (is128BitLaneCrossingShuffleMask(SrcVT.getSimpleVT(), ShuffleMask))
lib/Target/X86/X86InstrInfo.cpp 5967 switch (VT.getSimpleVT().SimpleTy) {
lib/Target/X86/X86TargetTransformInfo.cpp 1643 MVT SimpleSrcTy = SrcTy.getSimpleVT();
1644 MVT SimpleDstTy = DstTy.getSimpleVT();
2486 if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
2596 MVT MTy = VT.getSimpleVT();
3579 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
3585 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
lib/Target/XCore/XCoreISelLowering.cpp 187 switch (VT1.getSimpleVT().SimpleTy) {
1302 switch (RegVT.getSimpleVT().SimpleTy) {