|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc79638 if (!Operands[i]->isDivergent() &&
gen/lib/Target/ARM/ARMGenDAGISel.inc54211 return !SDValue(N,0)->getValueType(0).isVector() &&
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 787 if (Op->hasOneUse() || Op->getNumValues() > 1)
787 if (Op->hasOneUse() || Op->getNumValues() > 1)
860 for (const SDValue &Op : N->op_values()) {
911 for (SDNode *Node : N0->uses()) {
946 if (N0->getFlags().hasVectorReduction())
1207 Replace0 &= !N0->hasOneUse();
1208 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1990 SelectOp->setFlags(BO->getFlags());
2015 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2405 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2484 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2767 SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
2897 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2897 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2900 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
4949 OuterShift = M->getOpcode();
4956 if (!isAllOnesConstant(M->getOperand(0)))
4958 Y = M->getOperand(1);
5233 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
5381 SDValue N00 = N0->getOperand(0);
5392 SDValue N10 = N1->getOperand(0);
6343 auto LHS = calculateByteProvider(Op->getOperand(0), Index, Depth + 1);
6346 auto RHS = calculateByteProvider(Op->getOperand(1), Index, Depth + 1);
6357 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1));
6368 : calculateByteProvider(Op->getOperand(0), Index - ByteShift,
6374 SDValue NarrowOp = Op->getOperand(0);
6387 return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1,
6968 if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) {
7273 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
7301 SDValue N00 = N0->getOperand(0);
7302 SDValue N01 = N0->getOperand(1);
7445 N0->getFlags().hasExact()) {
8036 return N0->getOperand(0);
8377 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
8377 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
8378 SDValue Cond0 = N0->getOperand(0);
8379 SDValue Cond1 = N0->getOperand(1);
8390 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
8390 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
8391 SDValue Cond0 = N0->getOperand(0);
8392 SDValue Cond1 = N0->getOperand(1);
8404 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
8404 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
8405 SDValue N1_0 = N1->getOperand(0);
8406 SDValue N1_1 = N1->getOperand(1);
8407 SDValue N1_2 = N1->getOperand(2);
8423 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
8423 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
8424 SDValue N2_0 = N2->getOperand(0);
8425 SDValue N2_1 = N2->getOperand(1);
8426 SDValue N2_2 = N2->getOperand(2);
8445 SelectOp->setFlags(Flags);
8500 SelectNode->setFlags(Flags);
8525 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
8525 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
8535 if (Cond->getOperand(i)->isUndef())
8535 if (Cond->getOperand(i)->isUndef())
8540 else if (Cond->getOperand(i).getNode() != BottomHalf)
8547 if (Cond->getOperand(i)->isUndef())
8547 if (Cond->getOperand(i)->isUndef())
8552 else if (Cond->getOperand(i).getNode() != TopHalf)
8561 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
8561 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
8562 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
8562 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
8815 } else if (SCC->isUndef()) {
8824 SelectOp->setFlags(SCC->getFlags());
8824 SelectOp->setFlags(SCC->getFlags());
8907 if (N0->getOpcode() == ISD::SELECT) {
8908 SDValue Op1 = N0->getOperand(1);
8909 SDValue Op2 = N0->getOperand(2);
8924 return DAG.getSelect(DL, VT, N0->getOperand(0),
8940 unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits();
9046 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
9081 if (N0->getOpcode() != ISD::LOAD)
9172 SDValue N1 = N0->getOperand(0);
9649 if (N->getOpcode() == ISD::TRUNCATE) {
9650 Op = N->getOperand(0);
9660 SDValue Op0 = N->getOperand(0);
9661 SDValue Op1 = N->getOperand(1);
10257 SDNode *Mask = *(SRL->use_begin());
10588 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
10599 SDValue EltNo = N0->getOperand(1);
10650 for (const SDValue &Op : N0->op_values()) {
10798 auto VTs = DAG.getVTList(VT, N0->getValueType(1));
10811 if (N00.getOperand(0)->getValueType(0).getVectorElementType() ==
10813 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT,
11157 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
11177 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
11178 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
11375 if (isContractableFMUL(N0) && (Aggressive || N0->hasOneUse())) {
11382 if (isContractableFMUL(N1) && (Aggressive || N1->hasOneUse())) {
11422 N0->hasOneUse() && N0.getOperand(2)->hasOneUse()) {
11422 N0->hasOneUse() && N0.getOperand(2)->hasOneUse()) {
11433 N1->getOpcode() == PreferredFusedOpcode &&
11435 N1->hasOneUse() && N1.getOperand(2)->hasOneUse()) {
11435 N1->hasOneUse() && N1.getOperand(2)->hasOneUse()) {
11581 if (isContractableFMUL(N0) && (Aggressive || N0->hasOneUse())) {
11589 if (isContractableFMUL(N1) && (Aggressive || N1->hasOneUse())) {
11598 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
11691 isContractableFMUL(N0.getOperand(2)) && N0->hasOneUse() &&
11692 N0.getOperand(2)->hasOneUse()) {
11865 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
11888 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) {
12153 if (N0 == N1->getOperand(0))
12154 return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(1), Flags);
12156 if (N0 == N1->getOperand(1))
12157 return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(0), Flags);
12473 if (!MinUses || (N1->use_size() * NumElts) < MinUses)
12479 for (auto *U : N1->uses()) {
12658 EVT N1VT = N1->getValueType(0);
12659 EVT N1Op0VT = N1->getOperand(0).getValueType();
13208 N0->getFlags());
13577 if (Val == Ptr || Ptr->isPredecessorOf(Val.getNode()))
14024 if (Val->use_empty())
14430 Use->getOperand(0)->isDivergent());
14688 assert(SliceInst->getOpcode() == ISD::LOAD &&
14708 if (V->getOpcode() != ISD::AND ||
14709 !isa<ConstantSDNode>(V->getOperand(1)) ||
14710 !ISD::isNormalLoad(V->getOperand(0).getNode()))
14714 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
14726 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
14757 else if (Chain->getOpcode() == ISD::TokenFactor &&
15034 for (SDNode *Use : ConstNode->uses()) {
16936 if (llvm::all_of(VecOp->uses(), [&](SDNode *Use) {
16942 for (SDNode *Use : VecOp->uses()) {
16982 !Index->hasPredecessor(VecOp.getNode())) {
17139 In = Cast->getOperand(0);
17863 SmallVector<SDValue, 4> Ops(In->op_begin(), In->op_end());
17863 SmallVector<SDValue, 4> Ops(In->op_begin(), In->op_end());
17884 if (Scalar->getOpcode() == ISD::TRUNCATE &&
17886 TLI.isTypeLegal(Scalar->getOperand(0).getValueType()))
17887 Scalar = Scalar->getOperand(0);
17946 Opnds.append(Op->op_begin(), Op->op_begin() + NumElts);
17946 Opnds.append(Op->op_begin(), Op->op_begin() + NumElts);
18065 BinOp->getFlags());
18127 BinOp.hasOneUse() && Extract->getOperand(0)->hasOneUse()) {
18284 return V->getOperand(Idx / NumElems);
18311 SDValue Src = V->getOperand(IdxVal);
18319 ExtractVT, SDLoc(N), V->ops().slice(IdxVal, NumElems));
18497 if (!N0->hasOneUse())
18503 if (!N1->hasOneUse())
19018 EVT InnerVT = BC0->getValueType(0);
19044 SDValue SV0 = BC0->getOperand(0);
19045 SDValue SV1 = BC0->getOperand(1);
19072 assert(N1->getOperand(0).getValueType() == VT &&
19075 SDValue SV0 = N1->getOperand(0);
19076 SDValue SV1 = N1->getOperand(1);
19198 SDValue InVec = InVal->getOperand(0);
19199 SDValue EltNo = InVal->getOperand(1);
19373 SmallVector<SDValue, 8> Ops(N0->op_begin(), N0->op_end());
19373 SmallVector<SDValue, 8> Ops(N0->op_begin(), N0->op_end());
19390 if (N0->getOpcode() == ISD::FP16_TO_FP)
19391 return N0->getOperand(0);
19400 if (N0->getOpcode() == ISD::AND) {
19565 count_if(N0->ops(), [](SDValue V) { return !V.isUndef(); }) == 1 &&
19566 count_if(N1->ops(), [](SDValue V) { return !V.isUndef(); }) == 1) {
19644 std::all_of(std::next(Concat->op_begin()), Concat->op_end(),
19644 std::all_of(std::next(Concat->op_begin()), Concat->op_end(),
19702 SelectNode->setFlags(Flags);
20068 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
20069 N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2) &&
20072 SDValue AndLHS = N0->getOperand(0);
20073 auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
20782 if (!SDValue(Chain, 0)->hasOneUse())
20844 return ST->getOperand(0) != NewChain;
20855 for (const SDValue &Op : TF->ops())
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 220 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
221 dbgs() << " with: "; New->dump(&DAG));
235 New[i]->dump(&DAG));
243 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
244 dbgs() << " with: "; New->dump(&DAG));
1350 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1351 NewLoad->op_end());
3434 Tmp1->setFlags(Node->getFlags());
3523 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3546 Tmp1->setFlags(Node->getFlags());
3583 Tmp1->setFlags(Node->getFlags());
3593 Tmp1->setFlags(Node->getFlags());
3620 Tmp1->setFlags(Node->getFlags());
4297 Tmp1->setFlags(Node->getFlags());
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 1934 EVT OpVT = Op->getValueType(0);
1937 EVT PromotedVT = Promoted->getValueType(0);
1969 if (VT == Op->getValueType(0))
2150 EVT VecVT = Vec->getValueType(0);
2263 EVT OpVT = Op->getValueType(0);
2299 return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 4281 V0->getValueType(0).getScalarType(), V0, V1);
4311 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
4312 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 694 Result->setFlags(Op->getFlags());
694 Result->setFlags(Op->getFlags());
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 516 std::tie(CL, CH) = DAG.SplitVector(Res->getOperand(0), dl);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 258 assert(Lowered->getNumValues() == Op->getNumValues() &&
258 assert(Lowered->getNumValues() == Op->getNumValues() &&
602 unsigned NewOpc = Op->getOpcode();
615 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
748 if (Scalarized->getOpcode() == ISD::MERGE_VALUES) {
771 switch (Op->getOpcode()) {
951 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
1400 SDValue ScalarOp = DAG.getNode(Op->getOpcode(), dl, ValueVTs, Opers);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 474 if (Cond->getOpcode() == ISD::SETCC) {
475 EVT OpVT = Cond->getOperand(0).getValueType();
2566 EVT InVT = InVec->getValueType(0);
3819 for (unsigned i = 1; i < N->getNumOperands(); ++i)
3820 if (!N->getOperand(i)->isUndef())
3820 if (!N->getOperand(i)->isUndef())
3850 for (unsigned i = 0, e = InMask->getNumOperands(); i < e; ++i)
3851 Ops.push_back(InMask->getOperand(i));
3852 SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3869 assert(Mask->getValueType(0).getScalarSizeInBits() ==
3874 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
3882 EVT SubVT = Mask->getValueType(0);
3888 assert((Mask->getValueType(0) == ToMaskVT) &&
3905 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3905 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3910 EVT CondVT = Cond->getValueType(0);
3929 EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3960 if (Cond->getOpcode() == ISD::SETCC) {
3963 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3964 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3965 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3967 SDValue SETCC0 = Cond->getOperand(0);
3968 SDValue SETCC1 = Cond->getOperand(1);
3994 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
4833 if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
4839 unsigned size = L->getValueSizeInBits(0);
4840 while (size < LdOp->getValueSizeInBits(0)) {
4841 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
4842 size += L->getValueSizeInBits(0);
4844 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1675 V = V->getOperand(0);
3387 if (llvm::all_of(Val->ops(), [BitWidth](SDValue E) {
3982 if (getTarget().Options.NoNaNsFPMath || Op->getFlags().hasNoNaNs())
4240 Elts.append(Op->op_begin(), Op->op_end());
4240 Elts.append(Op->op_begin(), Op->op_end());
4783 llvm::any_of(Divisor->op_values(),
4850 if (V1->getValueType(0).bitsGT(SVT))
4852 if (V2->getValueType(0).bitsGT(SVT))
4856 if (V1->getValueType(0) != SVT || V2->getValueType(0) != SVT)
4856 if (V1->getValueType(0) != SVT || V2->getValueType(0) != SVT)
8192 if (To->isDivergent() != From->isDivergent())
8295 To_IsDivergent |= ToOp->isDivergent();
8358 if (To->isDivergent() != From->isDivergent())
8358 if (To->isDivergent() != From->isDivergent())
8976 if (is_contained((*this)->ops(), Dest)) {
8990 return llvm::all_of((*this)->ops(), [=](SDValue Op) {
9034 SDNodeFlags Flags = Op->getFlags();
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 192 switch (Base->getOpcode()) {
195 if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1)))
196 if (DAG.MaskedValueIsZero(Base->getOperand(0), C->getAPIntValue())) {
198 Base = DAG.getTargetLoweringInfo().unwrapAddress(Base->getOperand(0));
203 if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1))) {
205 Base = DAG.getTargetLoweringInfo().unwrapAddress(Base->getOperand(0));
212 unsigned int IndexResNo = (Base->getOpcode() == ISD::LOAD) ? 1 : 0;
231 if (Base->getOpcode() == ISD::ADD) {
240 if (Base->getOperand(1)->getOpcode() == ISD::MUL)
240 if (Base->getOperand(1)->getOpcode() == ISD::MUL)
244 Index = Base->getOperand(1);
245 SDValue PotentialBase = Base->getOperand(0);
248 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
249 Index = Index->getOperand(0);
254 if (Index->getOpcode() != ISD::ADD ||
255 !isa<ConstantSDNode>(Index->getOperand(1)))
258 Offset += cast<ConstantSDNode>(Index->getOperand(1))->getSExtValue();
259 Index = Index->getOperand(0);
260 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
261 Index = Index->getOperand(0);
291 Base->print(OS);
294 Index->print(OS);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 1426 N->setDebugLoc(DebugLoc());
5410 for (SDValue Op : N->op_values())
7013 Result->setFlags(Flags);
8489 for (const SDValue &V : Val->op_values())
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 856 OS << Value->getOperationName(G) << ':';
857 Value->print_types(OS, G);
858 Value->print_details(OS, G);
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1138 if (Op->getOpcode() == ISD::TokenFactor)
1149 assert(Op->getNodeId() != -1 &&
2226 New->setNodeId(-1);
2240 New->setNodeId(-1);
2254 New->setNodeId(-1);
2311 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2358 if (V->getOpcode() == ISD::EntryToken)
2362 if (V->getOpcode() == ISD::TokenFactor) {
2363 for (const SDValue &Op : V->op_values())
2577 if (N->getOpcode() != ISD::AND) return false;
2579 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2590 if (N->getOpcode() != ISD::OR) return false;
2592 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2955 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2963 LLVM_DEBUG(dbgs() << "Expected MemSDNode "; N->dump(CurDAG);
2971 if (N->getNumOperands() != 0 &&
2972 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2972 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2973 InputGlue = N->getOperand(N->getNumOperands()-1);
2973 InputGlue = N->getOperand(N->getNumOperands()-1);
3237 if (Imm->getOpcode() == ISD::Constant) {
3241 } else if (Imm->getOpcode() == ISD::ConstantFP) {
lib/CodeGen/SelectionDAG/TargetLowering.cpp 90 if (Value->getOpcode() != ISD::CopyFromReg)
92 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
1388 if (Op->getFlags().hasExact())
1453 if (Op->getFlags().hasExact())
1473 Flags.setExact(Op->getFlags().hasExact());
2217 if (llvm::any_of(Op->op_values(),
2219 SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
2219 SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
2856 if (N0->getOpcode() != ISD::ADD)
2861 if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1))))
2864 SDValue X = N0->getOperand(0);
3148 DCI.isBeforeLegalize() && N0->hasOneUse()) {
3152 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
3154 MinBits = N0->getOperand(0).getValueSizeInBits();
3155 PreExt = N0->getOperand(0);
3156 } else if (N0->getOpcode() == ISD::AND) {
3158 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
3161 PreExt = N0->getOperand(0);
3163 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
3165 MinBits = N0->getOperand(0).getValueSizeInBits();
3166 PreExt = N0->getOperand(0);
3209 SDValue TopSetCC = N0->getOperand(0);
3210 unsigned N0Opc = N0->getOpcode();
3216 isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
5351 const SDNodeFlags Flags = Op->getFlags();
5374 if (llvm::any_of(Op->op_values(), [&](SDValue N) {
5383 return llvm::all_of(Op->op_values(), [&](SDValue N) {
5468 const SDNodeFlags Flags = Op->getFlags();
5478 for (SDValue C : Op->op_values()) {
6478 if (Scalarized->getOpcode() == ISD::MERGE_VALUES)
6859 assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 144 switch(N->getOpcode()) {
149 auto Opnd0 = N->getOperand(0);
676 Reg->getValueType(0).getSizeInBits() == 32 && isDef32(*Reg.getNode()))
698 for (auto Use : N->uses()) {
1304 EVT VT = N->getOperand(2)->getValueType(0);
1324 EVT VT = N->getOperand(2)->getValueType(0);
1402 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1432 RegSeq->getValueType(0), MVT::Other};
1454 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1474 EVT VT = N->getOperand(2)->getValueType(0);
1503 EVT VT = N->getOperand(2)->getValueType(0);
1589 VT = Opd0->getValueType(0);
1637 if (Op->getOpcode() == ISD::TRUNCATE) {
1638 Op = Op->getOperand(0);
1639 VT = Op->getValueType(0);
1735 TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
1776 EVT NarrowVT = N->getOperand(0)->getValueType(0);
2412 SDValue Src = And1->getOperand(0);
2413 SDValue Dst = And0->getOperand(0);
2529 if (ShiftAmt->getOpcode() == ISD::ZERO_EXTEND ||
2530 ShiftAmt->getOpcode() == ISD::ANY_EXTEND)
2531 ShiftAmt = ShiftAmt->getOperand(0);
2533 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
2533 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
2534 SDValue Add0 = ShiftAmt->getOperand(0);
2535 SDValue Add1 = ShiftAmt->getOperand(1);
2544 else if (ShiftAmt->getOpcode() == ISD::SUB &&
2549 EVT SubVT = ShiftAmt->getValueType(0);
2576 NewShiftAmt = ShiftAmt->getOperand(0);
2582 else if (VT == MVT::i64 && NewShiftAmt->getValueType(0) == MVT::i32) {
2604 !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
2608 dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
2826 if (IRG_SP->getOpcode() != ISD::INTRINSIC_W_CHAIN ||
2827 cast<ConstantSDNode>(IRG_SP->getOperand(1))->getZExtValue() !=
3363 VT = Node->getOperand(2)->getValueType(0);
lib/Target/AArch64/AArch64ISelLowering.cpp 1060 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1061 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1075 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
1753 unsigned Opcode = Val->getOpcode();
1755 if (Val->getOperand(0).getValueType() == MVT::f128)
1766 SDValue O0 = Val->getOperand(0);
1767 SDValue O1 = Val->getOperand(1);
1814 unsigned Opcode = Val->getOpcode();
1816 SDValue LHS = Val->getOperand(0);
1817 SDValue RHS = Val->getOperand(1);
1818 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1851 assert(Val->hasOneUse() && "Valid conjunction/disjunction tree");
1855 SDValue LHS = Val->getOperand(0);
1862 SDValue RHS = Val->getOperand(1);
2207 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
2218 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2218 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2246 if (!DAG.getTargetLoweringInfo().isTypeLegal(Sel->getValueType(0)))
2499 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2499 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2677 N->getOperand(0)->getValueType(0),
4710 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5217 SDValue CCVal = Op->getOperand(0);
5218 SDValue TVal = Op->getOperand(1);
5219 SDValue FVal = Op->getOperand(2);
5226 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
5244 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
6989 } else if (V2->isUndef() && isSingletonEXTMask(ShuffleMask, VT, Imm)) {
7418 LLVM_DEBUG(ResultSLI->dump(&DAG));
7480 for (SDValue Lane : Op->ops()) {
8232 assert(Op->getFlags().hasNoNaNs() && "fmax vector reduction needs NoNaN flag");
8239 assert(Op->getFlags().hasNoNaNs() && "fmin vector reduction needs NoNaN flag");
9228 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
9405 if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) ||
9489 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
9490 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
9490 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
9491 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
9499 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
9513 N->getOperand(0)->getOperand(0), MaskConst);
9576 SDValue ConstVec = Op->getOperand(1);
9627 Op->getOperand(0), DAG.getConstant(C, DL, MVT::i32));
9644 unsigned Opc = Op->getOpcode();
9718 ShiftAmount = N->getConstantOperandVal(1);
9719 Src = N->getOperand(0);
9791 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
9792 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
9809 N0->getOperand(1 - i), N1->getOperand(1 - j));
9809 N0->getOperand(1 - i), N1->getOperand(1 - j));
9926 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
9927 !(Op0->isMachineOpcode() &&
9928 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
9930 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
9931 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
9932 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
9934 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
9941 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
9941 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
9943 SDValue Source = Op0->getOperand(0)->getOperand(0);
9943 SDValue Source = Op0->getOperand(0)->getOperand(0);
9946 EVT SVT = Source->getValueType(0);
9988 N0->getOpcode() == ISD::TRUNCATE &&
9989 N1->getOpcode() == ISD::TRUNCATE) {
9990 SDValue N00 = N0->getOperand(0);
9991 SDValue N10 = N1->getOperand(0);
10032 if (N1->getOpcode() != ISD::BITCAST)
10034 SDValue RHS = N1->getOperand(0);
10144 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
10144 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
10237 isSetCC(Op->getOperand(0), Info));
10586 EVT SrcVT = Src->getValueType(0);
10644 if (BasePtr->getOpcode() == ISD::ADD &&
10645 isa<ConstantSDNode>(BasePtr->getOperand(1))) {
10646 BaseOffset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
10647 BasePtr = BasePtr->getOperand(0);
10709 int64_t Offset = St.getBasePtr()->getConstantOperandVal(1);
11423 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
11423 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
11464 if (!Op->hasOneUse())
11473 if (Op->getOpcode() == ISD::TRUNCATE &&
11474 Bit < Op->getValueType(0).getSizeInBits()) {
11475 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
11479 if (Op->getOpcode() == ISD::ANY_EXTEND &&
11480 Bit < Op->getOperand(0).getValueSizeInBits()) {
11481 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
11484 if (Op->getNumOperands() != 2)
11487 auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
11491 switch (Op->getOpcode()) {
11498 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
11504 (Bit - C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
11506 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
11513 if (Bit >= Op->getValueType(0).getSizeInBits())
11514 Bit = Op->getValueType(0).getSizeInBits() - 1;
11515 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
11519 if ((Bit + C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
11521 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
11529 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 511 if (N->getFlags().isDefined())
512 return N->getFlags().hasNoNaNs();
1363 if (N2->isDivergent()) {
1364 if (N3->isDivergent()) {
1380 } else if (N0->isDivergent()) {
1810 Addr->getFlags().hasNoUnsignedWrap()) &&
1916 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1965 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1129 Op->print(errs(), &DAG);
1240 for (const SDUse &U : Op->ops())
2303 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2304 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
3029 switch (LHS->getOpcode()) {
3035 SDValue X = LHS->getOperand(0);
3042 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
3674 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3695 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3754 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3764 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3764 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3766 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3796 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
lib/Target/AMDGPU/R600ISelLowering.cpp 1160 SDValue Chain = VectorTrunc ? OldChain->getOperand(0) : OldChain;
1310 Op->getVTList(), Args, MemVT,
1312 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) {
1955 return Arg->getOperand(Element);
1965 Arg->getOperand(0).getOperand(Element));
lib/Target/AMDGPU/SIISelLowering.cpp 3959 Op->getFlags());
3961 Op->getFlags());
3982 Op->getFlags());
3984 Op->getFlags());
4005 Op->getFlags());
4007 Op->getFlags());
5331 SmallVector<EVT, 3> ResultTypes(Op->value_begin(), Op->value_end());
5331 SmallVector<EVT, 3> ResultTypes(Op->value_begin(), Op->value_end());
5332 SmallVector<EVT, 3> OrigResultTypes(Op->value_begin(), Op->value_end());
5332 SmallVector<EVT, 3> OrigResultTypes(Op->value_begin(), Op->value_end());
5648 if (!Offset->isDivergent()) {
5988 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
6053 Op->getOperand(1), Op->getOperand(2)), 0);
6053 Op->getOperand(1), Op->getOperand(2)), 0);
6282 return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
6353 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6377 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6401 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6474 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
6548 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
6623 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
6652 Op->getVTList(), Ops, VT, M->getMemOperand());
6673 Op->getVTList(), Ops, VT, M->getMemOperand());
6695 Op->getVTList(), Ops, VT, M->getMemOperand());
6794 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
6819 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
6858 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6883 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6908 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6949 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6993 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
7040 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
7071 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
7087 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
7093 Op->getOperand(2), Chain), 0);
7400 if (!Op->isDivergent() && Alignment >= 4 && NumElements < 32) {
7416 if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&
7522 const SDNodeFlags Flags = Op->getFlags();
7570 if (GlueChain->getNumValues() <= 1) {
7574 assert(GlueChain->getNumValues() == 3);
7591 if (GlueChain->getNumValues() <= 1) {
7595 assert(GlueChain->getNumValues() == 3);
7995 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
8055 N0->hasOneUse())
8087 N0->getFlags().hasNoUnsignedWrap()));
8253 if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &&
8255 if (auto *CShift = dyn_cast<ConstantSDNode>(LHS->getOperand(1))) {
8262 LHS->getOperand(0),
9041 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
9042 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
9302 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags());
9442 if (!(Op0->isDivergent() ^ Op1->isDivergent()))
9442 if (!(Op0->isDivergent() ^ Op1->isDivergent()))
9445 if (Op0->isDivergent())
9453 if (!(Op1->isDivergent() ^ Op2->isDivergent()))
9453 if (!(Op1->isDivergent() ^ Op2->isDivergent()))
9456 if (Op1->isDivergent())
9551 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args);
9575 return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);
9720 FMA->getFlags().hasAllowContract())) {
lib/Target/ARC/ARCISelLowering.cpp 496 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
541 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
lib/Target/ARM/ARMISelDAGToDAG.cpp 2856 if (!And->hasOneUse())
2861 And->getOpcode() != ISD::AND)
3136 if (NewImm->getNodeId() == -1)
3338 uint64_t ID = cast<ConstantSDNode>(Int->getOperand(1))->getZExtValue();
4789 New->setNodeId(-1);
lib/Target/ARM/ARMISelLowering.cpp 2959 SDValue WriteValue = Op->getOperand(2);
2969 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2969 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
4167 } else if (Op->getOpcode() == ISD::BITCAST &&
4168 Op->getValueType(0) == MVT::f64) {
4171 SDValue BitcastOp = Op->getOperand(0);
4172 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4173 isNullConstant(BitcastOp->getOperand(0)))
4249 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4250 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4272 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4521 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4536 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4537 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4551 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4772 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4773 V2TmpReg = V2Tmp->getOperand(0);
5187 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5239 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
6095 if (ShAmt->getValueType(0).getSizeInBits() > 64 ||
6100 if (ShAmt->getValueType(0) != MVT::i32)
7057 std::all_of(std::next(Op->op_begin()), Op->op_end(),
7057 std::all_of(std::next(Op->op_begin()), Op->op_end(),
7207 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7208 (constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)))) {
7213 if (VT != Value->getOperand(0).getValueType()) {
7222 Value->getOperand(0), Value->getOperand(1));
7222 Value->getOperand(0), Value->getOperand(1));
7278 SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElts);
7278 SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElts);
7862 if (ST->hasNEON() && V2->isUndef() && isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
7907 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
7907 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
7908 SDValue SubV1 = V1->getOperand(0);
7909 SDValue SubV2 = V1->getOperand(1);
8004 DAG.getNode(ARMISD::PREDICATE_CAST, dl, MVT::i32, Op->getOperand(0));
8067 DAG.getNode(ARMISD::PREDICATE_CAST, dl, MVT::i32, Op->getOperand(0));
8151 EVT VT = Op->getValueType(0);
8354 N->getOperand(0)->getValueType(0),
8996 (PassThru->getOpcode() == ARMISD::VMOVIMM &&
8997 isNullConstant(PassThru->getOperand(0))));
9013 !IsZero(PassThru->getOperand(0))))
9105 MVT Ty = Val->getSimpleValueType(0);
11062 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11062 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11064 SDValue Vec = N0->getOperand(0)->getOperand(0);
11064 SDValue Vec = N0->getOperand(0)->getOperand(0);
11071 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
11072 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
11072 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
11073 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
11073 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
11075 SDValue ExtVec0 = N0->getOperand(i);
11076 SDValue ExtVec1 = N1->getOperand(i);
11079 if (V != ExtVec0->getOperand(0).getNode() ||
11080 V != ExtVec1->getOperand(0).getNode())
11084 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
11085 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
11138 if (V->getOpcode() == ISD::UMUL_LOHI ||
11139 V->getOpcode() == ISD::SMUL_LOHI)
11200 Op0 = Mul->getOperand(0).getOperand(0);
11201 Op1 = Mul->getOperand(1).getOperand(0);
11274 AddcSubcOp0->getOpcode() != ISD::UMUL_LOHI &&
11275 AddcSubcOp0->getOpcode() != ISD::SMUL_LOHI &&
11276 AddcSubcOp1->getOpcode() != ISD::UMUL_LOHI &&
11277 AddcSubcOp1->getOpcode() != ISD::SMUL_LOHI)
11299 unsigned Opc = MULOp->getOpcode();
11473 if (LHS->getOpcode() == ARMISD::ADDE &&
11474 isNullConstant(LHS->getOperand(0)) &&
11475 isNullConstant(LHS->getOperand(1)) && isOneConstant(RHS)) {
11476 return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
11519 } else if (N->getOperand(1)->getOpcode() == ISD::SMUL_LOHI) {
11598 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND &&
11598 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND &&
11599 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR)
11599 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR)
11601 if (auto *Const = dyn_cast<ConstantSDNode>(N1->getOperand(1))) {
11604 if (N1->getOpcode() == ISD::ADD && Const->getAPIntValue().slt(0) &&
11815 SDValue N00 = N0->getOperand(0);
11816 SDValue N01 = N0->getOperand(1);
12108 OpS16 = OpS16->getOperand(0);
12272 if (N0->getOpcode() == ARMISD::VCMP)
12273 CondCode0 = (ARMCC::CondCodes)cast<const ConstantSDNode>(N0->getOperand(2))
12275 else if (N0->getOpcode() == ARMISD::VCMPZ)
12276 CondCode0 = (ARMCC::CondCodes)cast<const ConstantSDNode>(N0->getOperand(1))
12278 if (N1->getOpcode() == ARMISD::VCMP)
12279 CondCode1 = (ARMCC::CondCodes)cast<const ConstantSDNode>(N1->getOperand(2))
12281 else if (N1->getOpcode() == ARMISD::VCMPZ)
12282 CondCode1 = (ARMCC::CondCodes)cast<const ConstantSDNode>(N1->getOperand(1))
12292 N0->getOperand(0)->getValueType(0).isFloatingPoint()) ||
12292 N0->getOperand(0)->getValueType(0).isFloatingPoint()) ||
12294 N1->getOperand(0)->getValueType(0).isFloatingPoint()))
12294 N1->getOperand(0)->getValueType(0).isFloatingPoint()))
12298 Ops0.push_back(N0->getOperand(0));
12299 if (N0->getOpcode() == ARMISD::VCMP)
12300 Ops0.push_back(N0->getOperand(1));
12303 Ops1.push_back(N1->getOperand(0));
12304 if (N1->getOpcode() == ARMISD::VCMP)
12305 Ops1.push_back(N1->getOperand(1));
12308 SDValue NewN0 = DCI.DAG.getNode(N0->getOpcode(), SDLoc(N0), VT, Ops0);
12309 SDValue NewN1 = DCI.DAG.getNode(N1->getOpcode(), SDLoc(N1), VT, Ops1);
12374 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
12375 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
12390 N0->getOperand(1),
12391 N0->getOperand(0),
12392 N1->getOperand(0));
12449 if (From->getOpcode() == ISD::SRL &&
12450 isa<ConstantSDNode>(From->getOperand(1))) {
12451 APInt Shift = cast<ConstantSDNode>(From->getOperand(1))->getAPIntValue();
12454 From = From->getOperand(0);
12720 if (Elt->getOpcode() == ISD::BITCAST) {
12722 if (Elt->getOperand(0).getValueType() == MVT::i32)
12754 V->getOperand(0).getValueType() == MVT::i32)
12778 if (Op->getOpcode() == ARMISD::PREDICATE_CAST) {
12780 if (Op->getOperand(0).getValueType() == VT)
12781 return Op->getOperand(0);
12783 Op->getOperand(0).getValueType(), Op->getOperand(0));
12783 Op->getOperand(0).getValueType(), Op->getOperand(0));
13343 if (Trunc->getOpcode() != ISD::TRUNCATE)
13345 EVT FromVT = Trunc->getOperand(0).getValueType();
13484 SDValue ConstVec = Op->getOperand(1);
13513 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0),
13760 N->getOperand(0)->getOpcode() == ISD::AND &&
13761 N->getOperand(0)->hasOneUse()) {
13773 ConstantSDNode *AndMaskNode = dyn_cast<ConstantSDNode>(N0->getOperand(1));
13784 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
13964 if (!isNullConstant(CmpZ->getOperand(1)))
13967 assert(CmpZ->getOpcode() == ARMISD::CMPZ);
13968 SDValue And = CmpZ->getOperand(0);
13969 if (And->getOpcode() != ISD::AND)
13971 const APInt *AndC = isPowerOf2Constant(And->getOperand(1));
13974 SDValue X = And->getOperand(0);
13984 if (Op1->getOpcode() != ISD::OR)
13987 ConstantSDNode *OrC = dyn_cast<ConstantSDNode>(Op1->getOperand(1));
13990 SDValue Y = Op1->getOperand(0);
14041 switch (N->getOpcode()) {
14063 return SearchLoopIntrinsic(N->getOperand(0), CC, Imm, Negate);
14144 unsigned IntOp = cast<ConstantSDNode>(Int->getOperand(1))->getZExtValue();
14218 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
14219 LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
14219 LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
14220 LHS->getOperand(0)->hasOneUse()) {
14220 LHS->getOperand(0)->hasOneUse()) {
14221 auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0));
14221 auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0));
14222 auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1));
14222 auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1));
14223 auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
14230 ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),
14230 ARMISD::BRCOND, dl, VT, Chain, BB, LHS->getOperand(0)->getOperand(2),
14231 LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
14231 LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
14231 LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
14231 LHS->getOperand(0)->getOperand(3), LHS->getOperand(0)->getOperand(4));
14293 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
14294 auto *LHS0C = dyn_cast<ConstantSDNode>(LHS->getOperand(0));
14295 auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
14301 LHS->getOperand(2), LHS->getOperand(3),
14301 LHS->getOperand(2), LHS->getOperand(3),
14302 LHS->getOperand(4));
14824 if (ExtVal->use_empty() ||
14825 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
14828 SDNode *U = *ExtVal->use_begin();
15396 if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) &&
15415 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
15962 unsigned Opcode = Op->getOpcode();
15966 EVT VT = Op->getValueType(0);
15977 if (hasDivide && Op->getValueType(0).isSimple() &&
15978 Op->getSimpleValueType(0) == MVT::i32) {
15980 const SDValue Dividend = Op->getOperand(0);
15981 const SDValue Divisor = Op->getOperand(1);
lib/Target/AVR/AVRISelDAGToDAG.cpp 224 if (Op->getOpcode() == ISD::FrameIndex) {
239 if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
239 if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
240 SDValue CopyFromRegOp = Op->getOperand(0);
241 SDValue ImmOp = Op->getOperand(1);
250 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) {
252 cast<RegisterSDNode>(CopyFromRegOp->getOperand(1));
lib/Target/AVR/AVRISelLowering.cpp 340 unsigned Opcode = Op->getOpcode();
344 EVT VT = Op->getValueType(0);
372 for (SDValue const &Value : Op->op_values()) {
734 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
lib/Target/BPF/BPFISelDAGToDAG.cpp 481 unsigned IntNo = cast<ConstantSDNode>(BaseV->getOperand(1))->getZExtValue();
lib/Target/BPF/BPFISelLowering.cpp 51 Val->print(OS);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 2021 Op1 = Child->getOperand(1);
2023 if (!NodeHeights.count(Op1) || !NodeHeights.count(Child->getOperand(0))) {
2028 Worklist.push_back(Child->getOperand(0));
2031 if (std::abs(NodeHeights[Op1] - NodeHeights[Child->getOperand(0)]) > 1)
2035 NodeHeights[Child->getOperand(0)]) + 1;
lib/Target/Hexagon/HexagonISelLowering.cpp 2949 if (Cond->getOpcode() == ISD::XOR) {
2951 if (C1->getOpcode() == HexagonISD::PTRUE) {
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 1595 if (Cond->getOpcode() == ISD::XOR) {
1597 if (C1->getOpcode() == HexagonISD::QTRUE) {
lib/Target/Lanai/LanaiISelLowering.cpp 884 EVT VT = Op->getValueType(0);
888 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
938 SDValue V = Op->getOperand(0);
1501 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1502 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
lib/Target/Mips/MipsISelLowering.cpp 927 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
939 EVT ValTy = N->getOperand(0)->getValueType(0);
944 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
955 And0->getOperand(0));
1014 SDValue MultLHS = Mult->getOperand(0);
1015 SDValue MultRHS = Mult->getOperand(1);
1017 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1018 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1019 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1020 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1043 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1044 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1205 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
2697 EVT ValTy = Op->getValueType(0);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 552 EVT EltTy = N->getValueType(0).getVectorElementType();
554 if (N->getOpcode() == ISD::BITCAST)
555 N = N->getOperand(0);
628 EVT EltTy = N->getValueType(0).getVectorElementType();
630 if (N->getOpcode() == ISD::BITCAST)
631 N = N->getOperand(0);
659 EVT EltTy = N->getValueType(0).getVectorElementType();
661 if (N->getOpcode() == ISD::BITCAST)
662 N = N->getOperand(0);
693 EVT EltTy = N->getValueType(0).getVectorElementType();
695 if (N->getOpcode() == ISD::BITCAST)
696 N = N->getOperand(0);
715 EVT EltTy = N->getValueType(0).getVectorElementType();
717 if (N->getOpcode() == ISD::BITCAST)
718 N = N->getOperand(0);
899 if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
900 Node->getOperand(2)->getOpcode() != ISD::Constant)
lib/Target/Mips/MipsSEISelLowering.cpp 412 EVT ResTy = Op->getValueType(0);
418 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
419 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
420 Op->getOperand(2));
489 unsigned Op0Opcode = Op0->getOpcode();
507 SDValue Op0Op2 = Op0->getOperand(2);
514 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
514 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
516 Op0->getVTList(),
517 makeArrayRef(Ops, Op0->getNumOperands()));
556 if (N->getOpcode() == ISD::BITCAST)
557 N = N->getOperand(0);
578 if (N->getOpcode() != ISD::XOR)
581 if (isVectorAllOnes(N->getOperand(0)))
582 return N->getOperand(1) == OfNode;
584 if (isVectorAllOnes(N->getOperand(1)))
585 return N->getOperand(0) == OfNode;
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
611 SDValue Op0Op0 = Op0->getOperand(0);
612 SDValue Op0Op1 = Op0->getOperand(1);
613 SDValue Op1Op0 = Op1->getOperand(0);
614 SDValue Op1Op1 = Op1->getOperand(1);
905 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
905 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
906 SDValue Op0Op0 = Op0->getOperand(0);
912 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
913 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
916 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
920 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
922 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
922 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
923 Op0Op0->getOperand(2) };
925 Op0Op0->getVTList(),
926 makeArrayRef(Ops, Op0Op0->getNumOperands()));
1016 if (NotOp->getOpcode() == ISD::OR)
1017 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1018 NotOp->getOperand(1));
1314 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1320 Ops.push_back(Op->getOperand(OpNo++));
1323 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1326 SDValue Opnd = Op->getOperand(++OpNo), In64;
1334 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1335 Ops.push_back(Op->getOperand(OpNo));
1344 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1344 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1355 assert(Val->getValueType(1) == MVT::Other);
1363 SDValue Vec = Op->getOperand(1);
1364 SDValue Idx = Op->getOperand(2);
1365 EVT ResTy = Op->getValueType(0);
1366 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1375 EVT ResVecTy = Op->getValueType(0);
1383 SDValue LaneA = Op->getOperand(OpNr);
1420 auto *CImm = cast<ConstantSDNode>(Op->getOperand(ImmOp));
1422 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),
1424 SDLoc(Op), Op->getValueType(0));
1466 EVT VecTy = Op->getValueType(0);
1504 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1509 EVT ResTy = Op->getValueType(0);
1510 SDValue Vec = Op->getOperand(2);
1521 EVT ResTy = Op->getValueType(0);
1526 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1532 EVT ResTy = Op->getValueType(0);
1534 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1537 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1543 unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1583 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1583 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1584 Op->getOperand(2));
1589 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1589 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1592 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1592 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1593 Op->getOperand(2));
1595 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1595 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1612 EVT VecTy = Op->getValueType(0);
1614 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1617 Op->getConstantOperandVal(3) + 1);
1620 Op->getOperand(2), Op->getOperand(1));
1620 Op->getOperand(2), Op->getOperand(1));
1627 EVT VecTy = Op->getValueType(0);
1629 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1632 Op->getConstantOperandVal(3) + 1);
1635 Op->getOperand(2), Op->getOperand(1));
1635 Op->getOperand(2), Op->getOperand(1));
1638 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1638 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1639 Op->getOperand(2), Op->getOperand(1));
1639 Op->getOperand(2), Op->getOperand(1));
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1642 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1643 Op->getOperand(1));
1645 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1645 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1646 Op->getOperand(1), Op->getOperand(2));
1646 Op->getOperand(1), Op->getOperand(2));
1648 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1649 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1650 Op->getOperand(2));
1655 EVT VecTy = Op->getValueType(0);
1658 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1666 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1672 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1673 Op->getOperand(1));
1675 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1676 Op->getOperand(1));
1679 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1680 Op->getOperand(1), Op->getOperand(3),
1680 Op->getOperand(1), Op->getOperand(3),
1681 Op->getOperand(2));
1684 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1685 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1686 Op->getOperand(2));
1691 EVT VecTy = Op->getValueType(0);
1694 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1702 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1708 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1709 Op->getOperand(1));
1711 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1712 Op->getOperand(1));
1717 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1717 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1718 Op->getOperand(2), ISD::SETEQ);
1723 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1723 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1729 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1729 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1730 Op->getOperand(2), ISD::SETLE);
1735 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1735 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1741 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1741 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1742 Op->getOperand(2), ISD::SETULE);
1747 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1747 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1753 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1753 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1754 Op->getOperand(2), ISD::SETLT);
1759 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1759 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1765 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1765 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1766 Op->getOperand(2), ISD::SETULT);
1771 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1771 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1785 Op->getValueType(0), Op->getOperand(1),
1785 Op->getValueType(0), Op->getOperand(1),
1786 Op->getOperand(2));
1803 Op->getValueType(0), Op->getOperand(1),
1803 Op->getValueType(0), Op->getOperand(1),
1804 Op->getOperand(2));
1810 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1810 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1811 Op->getOperand(2));
1816 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1816 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1817 Op->getOperand(2));
1821 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1821 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1822 Op->getOperand(2));
1826 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1826 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1827 Op->getOperand(2), ISD::SETOEQ);
1830 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1830 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1831 Op->getOperand(2), ISD::SETOLE);
1834 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1834 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1835 Op->getOperand(2), ISD::SETOLT);
1838 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1838 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1839 Op->getOperand(2), ISD::SETONE);
1842 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1842 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1843 Op->getOperand(2), ISD::SETO);
1846 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1846 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1847 Op->getOperand(2), ISD::SETUEQ);
1850 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1850 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1851 Op->getOperand(2), ISD::SETULE);
1854 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1854 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1855 Op->getOperand(2), ISD::SETULT);
1858 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1858 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1859 Op->getOperand(2), ISD::SETUO);
1862 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1862 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1863 Op->getOperand(2), ISD::SETUNE);
1867 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1867 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1868 Op->getOperand(2));
1871 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1872 Op->getOperand(1));
1875 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1876 Op->getOperand(1));
1881 EVT ResTy = Op->getValueType(0);
1883 Op->getOperand(1));
1892 EVT ResTy = Op->getValueType(0);
1894 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1895 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1899 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1899 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1902 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1903 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1903 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1903 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1907 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1907 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1908 Op->getOperand(2));
1912 return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
1913 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1913 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1913 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1917 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1917 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1920 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1920 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1924 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1924 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1925 Op->getOperand(2));
1928 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1929 Op->getOperand(1));
1932 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1933 Op->getOperand(1));
1938 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1939 Op->getOperand(1), Op->getOperand(2));
1939 Op->getOperand(1), Op->getOperand(2));
1944 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1945 Op->getOperand(1), Op->getOperand(2));
1945 Op->getOperand(1), Op->getOperand(2));
1950 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1951 Op->getOperand(1), Op->getOperand(2));
1951 Op->getOperand(1), Op->getOperand(2));
1956 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1957 Op->getOperand(1), Op->getOperand(2));
1957 Op->getOperand(1), Op->getOperand(2));
1962 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1963 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1963 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1963 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1977 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1980 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1981 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1981 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1981 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1991 EVT ResTy = Op->getValueType(0);
1992 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1994 Op->getOperand(2), Op->getOperand(3)));
1994 Op->getOperand(2), Op->getOperand(3)));
2000 EVT ResTy = Op->getValueType(0);
2001 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2003 Op->getOperand(2), Op->getOperand(3)));
2003 Op->getOperand(2), Op->getOperand(3)));
2009 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2010 Op->getOperand(1), Op->getOperand(2));
2010 Op->getOperand(1), Op->getOperand(2));
2015 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2016 Op->getOperand(1), Op->getOperand(2));
2016 Op->getOperand(1), Op->getOperand(2));
2021 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2022 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2027 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2028 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2033 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2034 Op->getOperand(1), Op->getOperand(2));
2034 Op->getOperand(1), Op->getOperand(2));
2039 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2040 Op->getOperand(1), Op->getOperand(2));
2040 Op->getOperand(1), Op->getOperand(2));
2045 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2046 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2051 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2052 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2057 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2057 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2058 Op->getOperand(2));
2063 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2063 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2064 Op->getOperand(2));
2069 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2069 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2070 Op->getOperand(2));
2075 EVT ResTy = Op->getValueType(0);
2076 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2078 Op->getOperand(2), Op->getOperand(3)));
2078 Op->getOperand(2), Op->getOperand(3)));
2084 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2084 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2086 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2087 Op->getOperand(1), Op->getOperand(2));
2087 Op->getOperand(1), Op->getOperand(2));
2088 return DAG.getNOT(DL, Res, Res->getValueType(0));
2091 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2092 Op->getOperand(1),
2094 return DAG.getNOT(DL, Res, Res->getValueType(0));
2097 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2097 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2098 Op->getOperand(2));
2100 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2101 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2106 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2107 Op->getOperand(1), Op->getOperand(2));
2107 Op->getOperand(1), Op->getOperand(2));
2112 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2113 Op->getOperand(1), Op->getOperand(2));
2113 Op->getOperand(1), Op->getOperand(2));
2118 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2118 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2140 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2148 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2151 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2152 Op->getOperand(2), Op->getOperand(1));
2152 Op->getOperand(2), Op->getOperand(1));
2167 int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2176 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2176 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2182 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2183 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2192 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2193 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2194 Op->getOperand(1));
2199 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2200 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2201 Op->getOperand(1));
2206 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2206 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2212 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2213 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2227 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2236 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2236 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2242 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2243 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2257 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2266 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2266 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2267 Op->getOperand(2));
2272 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2273 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2278 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2279 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2279 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2279 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2281 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2281 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2282 Op->getOperand(2));
2284 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2285 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2296 SDValue ChainIn = Op->getOperand(0);
2297 SDValue Address = Op->getOperand(2);
2298 SDValue Offset = Op->getOperand(3);
2299 EVT ResTy = Op->getValueType(0);
2300 EVT PtrTy = Address->getValueType(0);
2315 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2370 SDValue ChainIn = Op->getOperand(0);
2371 SDValue Value = Op->getOperand(2);
2372 SDValue Address = Op->getOperand(3);
2373 SDValue Offset = Op->getOperand(4);
2374 EVT PtrTy = Address->getValueType(0);
2390 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2412 EVT ResTy = Op->getValueType(0);
2413 SDValue Op0 = Op->getOperand(0);
2414 EVT VecTy = Op0->getValueType(0);
2420 SDValue Op1 = Op->getOperand(1);
2430 if (Op->isUndef())
2462 EVT ResTy = Op->getValueType(0);
2600 Op->getOperand(0));
2679 Wt = Op->getOperand(0);
2681 Wt = Op->getOperand(1);
2688 Ws = Op->getOperand(0);
2690 Ws = Op->getOperand(1);
2725 Wt = Op->getOperand(0);
2727 Wt = Op->getOperand(1);
2734 Ws = Op->getOperand(0);
2736 Ws = Op->getOperand(1);
2772 Wt = Op->getOperand(0);
2774 Wt = Op->getOperand(1);
2781 Ws = Op->getOperand(0);
2783 Ws = Op->getOperand(1);
2820 Wt = Op->getOperand(0);
2822 Wt = Op->getOperand(1);
2829 Ws = Op->getOperand(0);
2832 Ws = Op->getOperand(1);
2866 Wt = Op->getOperand(0);
2868 Wt = Op->getOperand(1);
2873 Ws = Op->getOperand(0);
2875 Ws = Op->getOperand(1);
2909 Wt = Op->getOperand(0);
2911 Wt = Op->getOperand(1);
2916 Ws = Op->getOperand(0);
2918 Ws = Op->getOperand(1);
2963 Op0 = Op->getOperand(0);
2964 Op1 = Op->getOperand(1);
2966 Op0 = Op1 = Op->getOperand(0);
2968 Op0 = Op1 = Op->getOperand(1);
2987 EVT ResTy = Op->getValueType(0);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 639 if (Vector->getOpcode() == ISD::BITCAST) {
641 Source = Vector->getOperand(0);
3442 if (LHS->getOpcode() == ISD::AND) {
3451 SDValue AndLHS = LHS->getOperand(0);
3452 SDValue AndRHS = LHS->getOperand(1);
3494 } else if (LHS->getOpcode() == ISD::SHL) {
3502 Val = LHS->getOperand(0);
3504 SDValue ShlRHS = LHS->getOperand(1);
lib/Target/NVPTX/NVPTXISelLowering.cpp 1920 if (!(Op->getValueType(0) == MVT::v2f16 &&
1921 isa<ConstantFPSDNode>(Op->getOperand(0)) &&
1922 isa<ConstantFPSDNode>(Op->getOperand(1))))
1926 cast<ConstantFPSDNode>(Op->getOperand(0))->getValueAPF().bitcastToAPInt();
1928 cast<ConstantFPSDNode>(Op->getOperand(1))->getValueAPF().bitcastToAPInt();
1936 SDValue Index = Op->getOperand(1);
1942 SDValue Vector = Op->getOperand(0);
2209 SDValue Op0 = Op->getOperand(0);
2210 SDValue Op1 = Op->getOperand(1);
2211 SDValue Op2 = Op->getOperand(2);
4482 Val = Val->getOperand(0);
4485 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4485 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4486 Val = Val->getOperand(0);
4489 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4490 Val->getOpcode() == NVPTXISD::LoadV4) {
4516 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4516 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4557 for (const SDNode *U : Num->uses()) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 4689 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4747 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
6252 SDValue Op32 = ISR->getOperand(1);
6541 LLVM_DEBUG(Base->dump(CurDAG));
lib/Target/PowerPC/PPCISelLowering.cpp 2262 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
2262 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
5056 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
5058 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
7444 if (EnableQuadPrecision && (Op->getOperand(0).getValueType() == MVT::f128))
8231 SDValue Op0 = Op->getOperand(0);
9543 for (auto UI : Op.getOperand(1)->uses()) {
10053 isa<ConstantSDNode>(Op0->getOperand(1)) &&
13774 N->getOperand(1)->getOpcode() == ISD::ADD) {
13780 if (DAG.MaskedValueIsZero(Add->getOperand(1),
13783 SDNode *BasePtr = Add->getOperand(0).getNode();
13798 if (isa<ConstantSDNode>(Add->getOperand(1))) {
13799 SDNode *BasePtr = Add->getOperand(0).getNode();
13804 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
15124 N1->getOpcode() == ISD::AND)
15125 if (ConstantSDNode *Mask = isConstOrConstSplat(N1->getOperand(1)))
15127 return DAG.getNode(TargetOpcode, SDLoc(N), VT, N0, N1->getOperand(0));
15158 return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0),
15484 unsigned SubOpcd0 = N->getOperand(0)->getOperand(0).getOpcode();
15485 unsigned SubOpcd1 = N->getOperand(0)->getOperand(1).getOpcode();
15491 N->getOperand(0)->getOperand(0),
15492 N->getOperand(0)->getOperand(1),
15500 N->getOperand(0)->getOperand(0),
15501 N->getOperand(0)->getOperand(1),
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 269 LLVM_DEBUG(Base->dump(CurDAG));
lib/Target/RISCV/RISCVISelLowering.cpp 934 if (Op0->getOpcode() == RISCVISD::BuildPairF64)
991 if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) {
1033 auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
lib/Target/Sparc/SparcISelDAGToDAG.cpp 317 New->setNodeId(-1);
lib/Target/Sparc/SparcISelLowering.cpp 1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
2176 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2549 EVT VT = Size->getValueType(0);
2974 assert(MulResult->use_empty() && "Illegally typed node still in use!");
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 463 unsigned Op0Code = Op0->getOpcode();
464 unsigned Op1Code = Op1->getOpcode();
610 if (N->getNodeId() == -1 ||
618 N->setNodeId(Pos->getNodeId());
1256 SDValue Load = StoredVal->getOperand(0);
1300 for (SDValue Op : StoredVal->ops())
1332 unsigned Opc = StoredVal->getOpcode();
1500 if (auto *Op0Op1 = dyn_cast<ConstantSDNode>(Op0->getOperand(1)))
1730 return !N->isPredecessorOf(CCUser->getOperand(0).getNode());
lib/Target/SystemZ/SystemZISelLowering.cpp 1905 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1924 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), Op->getVTList(), Ops);
2146 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
2146 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
2166 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
2166 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
2193 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
2193 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
2487 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2491 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
3923 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3939 if (Op->getNumValues() == 1)
3941 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3942 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
5756 for (auto *U : Vec->uses()) {
5807 for (auto *U : Vec->uses()) {
6102 if (Select->getOpcode() != SystemZISD::SELECT_CCMASK)
6105 auto *SelectCCValid = dyn_cast<ConstantSDNode>(Select->getOperand(2));
6106 auto *SelectCCMask = dyn_cast<ConstantSDNode>(Select->getOperand(3));
6112 auto *TrueVal = dyn_cast<ConstantSDNode>(Select->getOperand(0));
6113 auto *FalseVal = dyn_cast<ConstantSDNode>(Select->getOperand(1));
6128 return Select->getOperand(4);
6149 if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)
6150 return N->getOperand(0);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 555 MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0);
789 if (Callee->getOpcode() == ISD::GlobalAddress) {
1319 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1321 const SDValue &SwizzleSrc = Lane->getOperand(0);
1322 const SDValue &IndexExt = Lane->getOperand(1);
1323 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG)
1325 const SDValue &Index = IndexExt->getOperand(0);
1326 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1328 const SDValue &SwizzleIndices = Index->getOperand(0);
1331 Index->getOperand(1)->getOpcode() != ISD::Constant ||
1331 Index->getOperand(1)->getOpcode() != ISD::Constant ||
1332 Index->getConstantOperandVal(1) != I)
1365 const SDValue &Lane = Op->getOperand(I);
1407 for (const SDValue &Lane : Op->op_values()) {
1439 const SDValue &Lane = Op->getOperand(I);
lib/Target/X86/X86ISelDAGToDAG.cpp 391 if (OtherOp->getOpcode() == ISD::CopyFromReg &&
393 OtherOp->getOperand(1).getNode())))
736 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
736 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
743 Ops.append(Call->op_begin() + 1, Call->op_end());
743 Ops.append(Call->op_begin() + 1, Call->op_end());
1549 if (N->getNodeId() == -1 ||
1552 DAG.RepositionNode(Pos->getIterator(), N.getNode());
1557 N->setNodeId(Pos->getNodeId());
1557 N->setNodeId(Pos->getNodeId());
1617 int64_t Mask = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
2372 if (N->getOpcode() != X86ISD::Wrapper)
2379 if (N->getOpcode() == ISD::TargetGlobalTLSAddress)
2383 if (N->getOpcode() != ISD::TargetGlobalAddress)
2565 unsigned Opc = N.getOperand(0)->getOpcode();
2604 if (N->getOpcode() != X86ISD::VBROADCAST_LOAD ||
2661 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
2661 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
2697 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
2697 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
2753 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
2753 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
2822 SDValue Load = StoredVal->getOperand(LoadOpNo);
2905 for (SDValue Op : StoredVal->ops())
2942 unsigned Opc = StoredVal->getOpcode();
3118 SDValue Operand = StoredVal->getOperand(1-LoadOpNo);
3215 if (V->getOpcode() == ISD::TRUNCATE && checkOneUse(V)) {
3228 if (Mask->getOpcode() != ISD::ADD || !checkOneUse(Mask))
3231 if (!isAllOnesConstant(Mask->getOperand(1)))
3234 SDValue M0 = peekThroughOneUseTruncation(Mask->getOperand(0));
3235 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0))
3237 if (!isOneConstant(M0->getOperand(0)))
3239 NBits = M0->getOperand(1);
3257 if (!isAllOnes(Mask->getOperand(1)))
3260 SDValue M0 = peekThroughOneUseTruncation(Mask->getOperand(0));
3261 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0))
3264 if (!isAllOnes(M0->getOperand(0)))
3266 NBits = M0->getOperand(1);
3317 if (N0->getOpcode() != ISD::SHL || !checkOneUse(N0))
3321 SDValue N01 = N0->getOperand(1);
3328 X = N0->getOperand(0);
3470 if (N0->getOpcode() != ISD::SRL && N0->getOpcode() != ISD::SRA)
3470 if (N0->getOpcode() != ISD::SRL && N0->getOpcode() != ISD::SRA)
3474 if (!N0->hasOneUse())
3483 ConstantSDNode *ShiftCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
3544 SDValue Input = N0->getOperand(0);
3650 if (ShiftAmt->getOpcode() == ISD::TRUNCATE)
3651 ShiftAmt = ShiftAmt->getOperand(0);
3657 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
3657 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
3658 SDValue Add0 = ShiftAmt->getOperand(0);
3659 SDValue Add1 = ShiftAmt->getOperand(1);
3667 } else if (ShiftAmt->getOpcode() == ISD::SUB &&
lib/Target/X86/X86ISelLowering.cpp 3999 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
4000 Callee->getOpcode() == ISD::ExternalSymbol) {
4007 Callee->getValueType(0) == MVT::i32) {
5477 Vec->ops().slice(IdxVal, ElemsPerChunk));
5931 if (Ptr->getOpcode() == X86ISD::Wrapper ||
5932 Ptr->getOpcode() == X86ISD::WrapperRIP)
5933 Ptr = Ptr->getOperand(0);
6146 if (Ptr->getOpcode() == X86ISD::Wrapper ||
6147 Ptr->getOpcode() == X86ISD::WrapperRIP)
6148 Ptr = Ptr->getOperand(0);
6981 !N->isOnlyUserOf(Sub.getNode()))
7598 Elt = Op->getOperand(EltIdx);
7629 SDValue Current = Op->getOperand(i);
7630 SDValue SrcVector = Current->getOperand(0);
8616 if (Op->isUndef()) {
8624 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
8624 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
8728 if (!isUndefLO && !V0->isUndef())
8730 if (!isUndefHI && !V1->isUndef())
8734 if (!isUndefLO && (!V0_LO->isUndef() || !V1_LO->isUndef()))
8734 if (!isUndefLO && (!V0_LO->isUndef() || !V1_LO->isUndef()))
8737 if (!isUndefHI && (!V0_HI->isUndef() || !V1_HI->isUndef()))
8737 if (!isUndefHI && (!V0_HI->isUndef() || !V1_HI->isUndef()))
8882 !Opnd0->hasNUsesOfValue(ExpectedUses, 0) || !Subtarget.hasAnyFMA())
9098 if (BV->getOperand(i)->isUndef())
9102 if (BV->getOperand(i)->isUndef())
9556 SDValue ExtractedIndex = Op->getOperand(1);
9781 SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElems);
9781 SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElems);
9820 DAG.getBuildVector(HVT, dl, Op->ops().slice(0, NumElems / 2));
9822 HVT, dl, Op->ops().slice(NumElems / 2, NumElems /2));
9979 ArrayRef<SDUse> Ops = Op->ops();
10068 ArrayRef<SDUse> Ops = Op->ops();
10467 int Scale = Size / V->getNumOperands();
10490 int Scale = V->getNumOperands() / Size;
17461 if (VT.getSizeInBits() == 8 && Op->isOnlyUserOf(Vec.getNode())) {
18703 SDValue V = Op->getOperand(0);
18709 if (VecFloatVT != Op->getSimpleValueType(0))
19112 MVT VT = Op->getSimpleValueType(0);
19113 SDValue In = Op->getOperand(0);
19749 for (SDNode *User : Op->uses())
19964 if (!Subtarget.hasSSE41() || !Op->hasOneUse())
19999 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
19999 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
20036 switch (Op->getOpcode()) {
20111 return DAG.getNode(X86ISD::SUB, dl, VTs, Op->getOperand(0),
20112 Op->getOperand(1)).getValue(1);
20125 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
20125 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
21172 assert(Op->getValueType(1) == MVT::i8 && "Unexpected VT!");
21173 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC);
21216 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
21521 MVT VT = Op->getSimpleValueType(0);
21522 SDValue In = Op->getOperand(0);
21577 SDValue In = Op->getOperand(0);
21594 SDValue In = Op->getOperand(0);
21595 MVT VT = Op->getSimpleValueType(0);
21705 MVT VT = Op->getSimpleValueType(0);
21706 SDValue In = Op->getOperand(0);
21930 assert(NewLd->getNumValues() == 2 && "Loads must carry a chain!");
22464 unsigned NumElts = SrcOp->getNumOperands();
22470 SDValue CurrentOp = SrcOp->getOperand(i);
22471 if (CurrentOp->isUndef()) {
22482 SDValue CurrentOp = SrcOp->getOperand(i);
22483 if (CurrentOp->isUndef()) {
22494 SDValue CurrentOp = SrcOp->getOperand(i);
22495 if (CurrentOp->isUndef()) {
23285 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
23505 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
23505 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
23520 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
23520 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
23533 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
23533 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
23605 Op->getOperand(1), Op->getOperand(2));
23605 Op->getOperand(1), Op->getOperand(2));
23987 SDValue Chain = Op->getOperand(0);
24006 DAG.getNode(Opcode, dl, VTs, Chain, Op->getOperand(2),
24007 Op->getOperand(3), Op->getOperand(4));
24007 Op->getOperand(3), Op->getOperand(4));
24009 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
24030 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
24043 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32, MVT::Other);
24048 SDValue Ops[] = {DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
24049 DAG.getConstant(1, dl, Op->getValueType(1)),
24052 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, Op->getValueType(1), Ops);
24055 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
24125 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
24129 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
24130 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
25167 bool IsSigned = Op->getOpcode() == ISD::MULHS;
25391 switch (Op->getOpcode()) {
25406 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
25407 EVT ArgVT = Op->getOperand(i).getValueType();
25412 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr,
25715 SDValue Op = Amt->getOperand(i);
25716 if (Op->isUndef()) {
25840 SDValue A = Amt->getOperand(i);
26723 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(),
27106 switch (N->getOpcode()) {
27130 {N->getOperand(0), N->getOperand(1), N->getOperand(2)},
27130 {N->getOperand(0), N->getOperand(1), N->getOperand(2)},
27130 {N->getOperand(0), N->getOperand(1), N->getOperand(2)},
27131 /*MemVT=*/N->getSimpleValueType(0), MMO);
27138 SDValue Chain = N->getOperand(0);
27139 SDValue LHS = N->getOperand(1);
27140 SDValue RHS = N->getOperand(2);
27141 unsigned Opc = N->getOpcode();
27142 MVT VT = N->getSimpleValueType(0);
27148 if (N->hasAnyUseOfValue(0)) {
27178 assert(!N->hasAnyUseOfValue(0));
27180 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
27185 assert(!N->hasAnyUseOfValue(0));
27187 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
27193 assert(!N->hasAnyUseOfValue(0));
27195 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
27621 if (Op->getGluedNode())
27622 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
27622 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
27642 if (Op->getGluedNode())
27643 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
27643 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
27654 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
27654 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
27807 assert((N->getNumValues() == Res->getNumValues()) &&
31806 if (N->getOpcode() == X86ISD::Wrapper || N->getOpcode() == X86ISD::WrapperRIP)
31806 if (N->getOpcode() == X86ISD::Wrapper || N->getOpcode() == X86ISD::WrapperRIP)
31807 return N->getOperand(0);
33356 !V->isOnlyUserOf(V.getOperand(0).getNode()))
33505 for (SDNode *User : Src->uses())
33861 if (!V1->hasOneUse() || !V2->hasOneUse())
33861 if (!V1->hasOneUse() || !V2->hasOneUse())
33868 LHS = V1->getOperand(0); RHS = V1->getOperand(1);
33868 LHS = V1->getOperand(0); RHS = V1->getOperand(1);
33869 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
33869 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
33870 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
33870 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
33874 LHS = V2->getOperand(0); RHS = V2->getOperand(1);
33874 LHS = V2->getOperand(0); RHS = V2->getOperand(1);
33875 if ((V1->getOperand(0) != LHS || V1->getOperand(1) != RHS) &&
33875 if ((V1->getOperand(0) != LHS || V1->getOperand(1) != RHS) &&
33876 (V1->getOperand(0) != RHS || V1->getOperand(1) != LHS))
33876 (V1->getOperand(0) != RHS || V1->getOperand(1) != LHS))
33886 IsSubAdd = Op0Even ? V1->getOpcode() == ISD::FADD
33887 : V2->getOpcode() == ISD::FADD;
34289 bool AssumeSingleUse = llvm::all_of(Amt->uses(), [&Amt](SDNode *Use) {
35520 SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end());
35520 SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end());
35696 SDValue AbsOp1 = Abs->getOperand(0);
36253 for (SDValue Op : Vec->ops())
36490 if (all_of(InputVector->uses(), IsBoolExtract) &&
36772 for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end();
36772 for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end();
36791 for (SDNode *U : Cond->uses()) {
37108 if (Other.getNode() && Other->getNumOperands() == 2 &&
37109 Other->getOperand(0) == Cond.getOperand(0)) {
37110 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
37110 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
37111 SDValue CondRHS = Cond->getOperand(1);
37117 Other->getOpcode() == ISD::SUB && OpRHS == CondRHS)
37130 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
37167 SDValue CondLHS = Cond->getOperand(0);
37168 SDValue CondRHS = Cond->getOperand(1);
37252 (Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
37357 (Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
37475 if (Cond->getOpcode() == X86ISD::CMP) {
37476 if (!isNullConstant(Cond->getOperand(1)))
37479 Cond = Cond->getOperand(0);
37485 switch (Cond->getOpcode()) {
37493 SetCC0 = Cond->getOperand(0);
37494 SetCC1 = Cond->getOperand(1);
37501 SetCC0->getOperand(1) != SetCC1->getOperand(1))
37501 SetCC0->getOperand(1) != SetCC1->getOperand(1))
37504 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
37505 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
37506 Flags = SetCC0->getOperand(1);
37543 DAG.getNode(X86ISD::SUB, SDLoc(CarryOp1), CarryOp1->getVTList(),
38667 SDValue CMP00 = CMP0->getOperand(0);
38668 SDValue CMP01 = CMP0->getOperand(1);
38795 if (Narrow->getOpcode() != ISD::XOR &&
38796 Narrow->getOpcode() != ISD::AND &&
38797 Narrow->getOpcode() != ISD::OR)
38800 SDValue N0 = Narrow->getOperand(0);
38801 SDValue N1 = Narrow->getOperand(1);
38821 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), VT))
38832 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, VT, N0, N1);
39258 N->getOperand(0)->isOnlyUserOf(SrcVec.getNode()) &&
39495 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Cmp->getOperand(0));
39518 return (N->getOpcode() == ISD::OR && N->hasOneUse());
39518 return (N->getOpcode() == ISD::OR && N->hasOneUse());
39530 return N->getOpcode() == X86ISD::SETCC && N->hasOneUse() &&
39530 return N->getOpcode() == X86ISD::SETCC && N->hasOneUse() &&
39531 X86::CondCode(N->getConstantOperandVal(0)) == X86::COND_E &&
39532 N->getOperand(1).getOpcode() == X86ISD::CMP &&
39533 isNullConstant(N->getOperand(1).getOperand(1)) &&
39534 N->getOperand(1).getValueType().bitsGE(MVT::i32);
39546 OR = (LHS->getOpcode() == ISD::OR) ? LHS.getNode() : RHS.getNode();
39576 if (RHS->getOpcode() == ISD::OR)
40107 for (SDValue Op : V->ops()) {
40540 StoredVal->ops().slice(0, 32));
40543 StoredVal->ops().slice(32, 32));
41428 EVT VT = Op->getValueType(0);
41560 Arg->getFlags().hasNoSignedZeros() && Subtarget.hasAnyFMA()) {
41583 return DAG.getBitcast(OrigVT, DAG.getNode(NewOpcode, DL, VT, Arg->ops()));
41721 if (!RHSC || RHSC->getZExtValue() != 1 || LHS->getOpcode() != X86ISD::SETCC)
41725 X86::CondCode(LHS->getConstantOperandVal(0)));
41727 return getSETCC(NewCC, LHS->getOperand(1), DL, DAG);
42217 bool NSW = Add->getFlags().hasNoSignedWrap();
42218 bool NUW = Add->getFlags().hasNoUnsignedWrap();
43115 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
43116 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
43116 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
43138 N->getOperand(0)->getOperand(0), MaskConst);
43294 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
43294 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
43332 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
43332 for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
43583 SDValue EFLAGS = Y->getOperand(1);
43610 SDValue EFLAGS = Y->getOperand(1);
43711 (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
43712 Op->isOnlyUserOf(Op.getOperand(1).getNode())));
43732 SDValue N0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, MulOp->getOperand(0));
43733 SDValue N1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, MulOp->getOperand(1));
43868 SDValue Op0L = Op0->getOperand(i), Op1L = Op1->getOperand(i),
43868 SDValue Op0L = Op0->getOperand(i), Op1L = Op1->getOperand(i),
43869 Op0H = Op0->getOperand(i + 1), Op1H = Op1->getOperand(i + 1);
43869 Op0H = Op0->getOperand(i + 1), Op1H = Op1->getOperand(i + 1);
43876 auto *Const0L = dyn_cast<ConstantSDNode>(Op0L->getOperand(1));
43877 auto *Const1L = dyn_cast<ConstantSDNode>(Op1L->getOperand(1));
43878 auto *Const0H = dyn_cast<ConstantSDNode>(Op0H->getOperand(1));
43879 auto *Const1H = dyn_cast<ConstantSDNode>(Op1H->getOperand(1));
43901 Mul = Op0L->getOperand(0);
43902 if (Mul->getOpcode() != ISD::MUL ||
43907 if (Mul != Op0L->getOperand(0) || Mul != Op1L->getOperand(0) ||
43907 if (Mul != Op0L->getOperand(0) || Mul != Op1L->getOperand(0) ||
43908 Mul != Op0H->getOperand(0) || Mul != Op1H->getOperand(0))
43908 Mul != Op0H->getOperand(0) || Mul != Op1H->getOperand(0))
44217 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
44608 SDValue NotOp = V->getOperand(0);
45116 SDNode *User = *Op->use_begin();
45129 SDNode *User = *Op->use_begin();
lib/Target/XCore/XCoreISelDAGToDAG.cpp 220 if (Chain->getOpcode() != ISD::TokenFactor)
224 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
225 if (Chain->getOperand(i) == Old) {
229 Ops.push_back(Chain->getOperand(i));
242 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
244 unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
247 SDValue nextAddr = Addr->getOperand(2);
254 SDValue CheckEventChainIn = Addr->getOperand(0);
272 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
273 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
273 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
275 nextAddr->getOperand(0), Glue);
lib/Target/XCore/XCoreISelLowering.cpp 429 isWordAligned(BasePtr->getOperand(0), DAG)) {
430 SDValue NewBasePtr = BasePtr->getOperand(0);
431 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
438 BasePtr->getValueType(0));
1315 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
1366 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));