|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc79507 if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg)
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4869 return N->getOpcode() != ISD::TRUNCATE &&
4870 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4871 N->getOpcode() != ISD::CopyFromReg;
gen/lib/Target/X86/X86GenDAGISel.inc253996 return N->getOpcode() != ISD::TRUNCATE &&
253997 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
253998 N->getOpcode() != ISD::CopyFromReg &&
253999 N->getOpcode() != ISD::AssertSext &&
254000 N->getOpcode() != ISD::AssertZext;
include/llvm/CodeGen/SelectionDAG.h 1776 TargetMemSDNode(dl.getIROrder(), DebugLoc(), VTs, MemVT, MMO).getOpcode();
include/llvm/CodeGen/SelectionDAGNodes.h 908 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
1159 return Node->getOpcode();
1290 return N->getOpcode() == ISD::ADDRSPACECAST;
1397 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1404 return N->getOpcode() == ISD::LOAD ||
1405 N->getOpcode() == ISD::STORE ||
1406 N->getOpcode() == ISD::PREFETCH ||
1407 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1408 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1409 N->getOpcode() == ISD::ATOMIC_SWAP ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1411 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1412 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1413 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1414 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1415 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1416 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1417 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1418 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1419 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1420 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1421 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1422 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1423 N->getOpcode() == ISD::ATOMIC_LOAD ||
1424 N->getOpcode() == ISD::ATOMIC_STORE ||
1425 N->getOpcode() == ISD::MLOAD ||
1426 N->getOpcode() == ISD::MSTORE ||
1427 N->getOpcode() == ISD::MGATHER ||
1428 N->getOpcode() == ISD::MSCATTER ||
1450 unsigned Op = getOpcode();
1464 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1465 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1466 N->getOpcode() == ISD::ATOMIC_SWAP ||
1467 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1470 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1471 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1472 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1473 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1474 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1475 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1476 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1477 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1478 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1479 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1480 N->getOpcode() == ISD::ATOMIC_LOAD ||
1481 N->getOpcode() == ISD::ATOMIC_STORE;
1502 N->getOpcode() == ISD::PREFETCH ||
1569 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1601 return N->getOpcode() == ISD::Constant ||
1602 N->getOpcode() == ISD::TargetConstant;
1656 return N->getOpcode() == ISD::ConstantFP ||
1657 N->getOpcode() == ISD::TargetConstantFP;
1741 return N->getOpcode() == ISD::GlobalAddress ||
1742 N->getOpcode() == ISD::TargetGlobalAddress ||
1743 N->getOpcode() == ISD::GlobalTLSAddress ||
1744 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1762 return N->getOpcode() == ISD::FrameIndex ||
1763 N->getOpcode() == ISD::TargetFrameIndex;
1794 return N->getOpcode() == ISD::LIFETIME_START ||
1795 N->getOpcode() == ISD::LIFETIME_END;
1815 return N->getOpcode() == ISD::JumpTable ||
1816 N->getOpcode() == ISD::TargetJumpTable;
1877 return N->getOpcode() == ISD::ConstantPool ||
1878 N->getOpcode() == ISD::TargetConstantPool;
1900 return N->getOpcode() == ISD::TargetIndex;
1920 return N->getOpcode() == ISD::BasicBlock;
2006 return N->getOpcode() == ISD::BUILD_VECTOR;
2028 return N->getOpcode() == ISD::SRCVALUE;
2045 return N->getOpcode() == ISD::MDNODE_SDNODE;
2061 return N->getOpcode() == ISD::Register;
2079 return N->getOpcode() == ISD::RegisterMask;
2101 return N->getOpcode() == ISD::BlockAddress ||
2102 N->getOpcode() == ISD::TargetBlockAddress;
2120 return N->getOpcode() == ISD::EH_LABEL ||
2121 N->getOpcode() == ISD::ANNOTATION_LABEL;
2141 return N->getOpcode() == ISD::ExternalSymbol ||
2142 N->getOpcode() == ISD::TargetExternalSymbol;
2158 return N->getOpcode() == ISD::MCSymbol;
2175 return N->getOpcode() == ISD::CONDCODE;
2194 return N->getOpcode() == ISD::VALUETYPE;
2210 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2226 return N->getOpcode() == ISD::LOAD ||
2227 N->getOpcode() == ISD::STORE;
2255 return N->getOpcode() == ISD::LOAD;
2286 return N->getOpcode() == ISD::STORE;
2304 return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
2307 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2311 return N->getOpcode() == ISD::MLOAD ||
2312 N->getOpcode() == ISD::MSTORE;
2338 return N->getOpcode() == ISD::MLOAD;
2373 return N->getOpcode() == ISD::MSTORE;
2415 return N->getOpcode() == ISD::MGATHER ||
2416 N->getOpcode() == ISD::MSCATTER;
2435 return N->getOpcode() == ISD::MGATHER;
2454 return N->getOpcode() == ISD::MSCATTER;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 238 assert(N->getOpcode() != ISD::DELETED_NODE &&
243 if (N->getOpcode() == ISD::HANDLENODE)
1458 assert(N->getOpcode() != ISD::DELETED_NODE &&
1489 switch (N->getOpcode()) {
1627 assert(N->getOpcode() != ISD::DELETED_NODE &&
1630 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1631 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1643 switch (N->getOpcode()) {
1672 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1680 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1722 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1837 switch (CurNode->getOpcode()) {
1917 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&
1948 auto BinOpcode = BO->getOpcode();
1995 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
1995 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2001 bool IsAdd = N->getOpcode() == ISD::ADD;
2036 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2036 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2042 bool IsAdd = N->getOpcode() == ISD::ADD;
2316 unsigned Opcode = N->getOpcode();
2591 bool IsSigned = (ISD::SADDO == N->getOpcode());
2604 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2897 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2897 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2900 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3114 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
3188 return DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, N0.getNode(),
3231 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3308 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
3511 unsigned Opcode = Node->getOpcode();
3547 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
3553 unsigned UserOpc = User->getOpcode();
3583 unsigned Opc = N->getOpcode();
3869 unsigned Opcode = N->getOpcode();
4180 bool IsSigned = (ISD::SMULO == N->getOpcode());
4188 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
4218 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
4223 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
4227 unsigned Opcode = N->getOpcode();
4252 unsigned LogicOpcode = N->getOpcode();
4783 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
4783 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
4933 assert(N->getOpcode() == ISD::AND);
4949 OuterShift = M->getOpcode();
4985 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op");
5233 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
6649 assert(N->getOpcode() == ISD::OR &&
6788 assert(N->getOpcode() == ISD::XOR);
7073 unsigned ShiftOpcode = Shift->getOpcode();
7161 if (N->getOpcode() != ISD::SHL)
7191 SDValue NewRHS = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(1),
7195 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0),
7201 assert(N->getOpcode() == ISD::TRUNCATE);
7246 return DAG.getNode(N->getOpcode(), dl, VT, N0,
7255 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1);
7265 bool SameSide = (N->getOpcode() == NextOp);
7273 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
7923 if (Use->getOpcode() == ISD::BRCOND)
7925 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
7928 if (Use->getOpcode() == ISD::BRCOND)
7941 bool IsFSHL = N->getOpcode() == ISD::FSHL;
7962 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1,
8377 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
8390 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
8404 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
8423 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
8842 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND;
8888 unsigned Opcode = N->getOpcode();
8907 if (N0->getOpcode() == ISD::SELECT) {
8988 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
9011 if (User->getOpcode() == ISD::CopyToReg)
9020 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
9060 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
9061 N->getOpcode() == ISD::ZERO_EXTEND) &&
9081 if (N0->getOpcode() != ISD::LOAD)
9093 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI))
9097 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
9149 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode());
9157 assert(N->getOpcode() == ISD::ZERO_EXTEND);
9237 unsigned CastOpcode = Cast->getOpcode();
9381 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
9382 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext");
9404 auto ShiftOpcode = N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
9649 if (N->getOpcode() == ISD::TRUNCATE) {
9680 assert((Extend->getOpcode() == ISD::ZERO_EXTEND ||
9681 Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op");
10105 unsigned Opcode = N->getOpcode();
10166 unsigned Opc = N->getOpcode();
10258 if (Mask->getOpcode() == ISD::AND &&
10574 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND))
10860 assert(N->getOpcode() == ISD::BUILD_PAIR);
11157 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
11433 N1->getOpcode() == PreferredFusedOpcode &&
11834 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation");
12480 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
12812 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
12816 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
12941 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
13064 N->use_begin()->getOpcode() == ISD::FP_ROUND)
13232 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
13471 if (N->getOpcode() == ISD::ADD) {
13480 } else if (N->getOpcode() == ISD::SUB) {
13603 if (Use.getUser()->getOpcode() != ISD::ADD &&
13604 Use.getUser()->getOpcode() != ISD::SUB) {
13695 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
13696 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
13765 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
13765 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
13794 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
13794 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
14421 if (Use->getOpcode() != ISD::BITCAST)
14632 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
14640 if (User->getOpcode() != ISD::TRUNCATE)
14688 assert(SliceInst->getOpcode() == ISD::LOAD &&
14708 if (V->getOpcode() != ISD::AND ||
14757 else if (Chain->getOpcode() == ISD::TokenFactor &&
15038 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use.
15074 if (OtherOp->getOpcode() == ISD::ADD &&
15441 if (N->getOpcode() == ISD::TokenFactor) {
16213 if (N->getOpcode() != ISD::DELETED_NODE)
16311 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N))
16937 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
16950 if (N->getOpcode() != ISD::DELETED_NODE)
17283 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector");
17884 if (Scalar->getOpcode() == ISD::TRUNCATE &&
18922 if (V->getOpcode() == ISD::BITCAST) {
18929 if (V->getOpcode() == ISD::BUILD_VECTOR) {
19390 if (N0->getOpcode() == ISD::FP16_TO_FP)
19400 if (N0->getOpcode() == ISD::AND) {
19414 unsigned Opcode = N->getOpcode();
19446 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!");
19537 unsigned Opcode = N->getOpcode();
19588 unsigned Opcode = N->getOpcode();
19728 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
19794 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
19821 if (TheSelect->getOpcode() == ISD::SELECT) {
20068 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 113 if (User->getOpcode() == ISD::CopyToReg &&
228 if (User->getOpcode() == ISD::CopyToReg &&
341 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
484 if (User->getOpcode() == ISD::CopyToReg &&
946 if (F->getOpcode() == ISD::CopyFromReg) {
949 } else if (F->getOpcode() == ISD::CopyToReg) {
982 switch (Node->getOpcode()) {
1024 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1035 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1051 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 677 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
698 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
967 if (Node->getOpcode() == ISD::TargetConstant ||
968 Node->getOpcode() == ISD::Register)
988 switch (Node->getOpcode()) {
993 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
996 Action = TLI.getOperationAction(Node->getOpcode(),
1000 Action = TLI.getOperationAction(Node->getOpcode(),
1003 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1013 Action = TLI.getOperationAction(Node->getOpcode(),
1018 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1022 Action = TLI.getOperationAction(Node->getOpcode(),
1028 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1029 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1030 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1036 if (Node->getOpcode() == ISD::SELECT_CC)
1037 Action = TLI.getOperationAction(Node->getOpcode(),
1040 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1068 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1080 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1087 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1097 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1115 Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
1122 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1130 Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1135 Action = TLI.getOperationAction(Node->getOpcode(),
1139 Action = TLI.getOperationAction(Node->getOpcode(),
1156 Node->getOpcode(), Node->getOperand(0).getValueType());
1159 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1162 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1169 switch (Node->getOpcode()) {
1259 switch (Node->getOpcode()) {
2184 unsigned Opcode = Node->getOpcode();
2262 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2272 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2272 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2659 switch (Node->getOpcode()) {
2817 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2837 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2892 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3094 switch (Node->getOpcode()) {
3123 if (Node->getOpcode() == ISD::FCOS)
3199 bool isSigned = Node->getOpcode() == ISD::SREM;
3219 bool isSigned = Node->getOpcode() == ISD::SDIV;
3233 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3248 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3259 if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3349 bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3675 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3717 switch (Node->getOpcode()) {
3719 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3730 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3755 unsigned Opc = Node->getOpcode();
4125 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4126 Node->getOpcode() == ISD::SINT_TO_FP ||
4127 Node->getOpcode() == ISD::SETCC ||
4128 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4129 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4132 if (Node->getOpcode() == ISD::BR_CC)
4134 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4137 switch (Node->getOpcode()) {
4145 if (Node->getOpcode() == ISD::CTTZ) {
4156 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4157 if (Node->getOpcode() == ISD::CTLZ ||
4158 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4170 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4182 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4188 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4237 switch (Node->getOpcode()) {
4256 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4263 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4356 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4367 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4374 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4381 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4403 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 53 switch (N->getOpcode()) {
790 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
831 switch (N->getOpcode()) {
898 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16);
898 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16);
902 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
939 bool Signed = N->getOpcode() == ISD::FP_TO_SINT;
1120 switch (N->getOpcode()) {
1549 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
1634 switch (N->getOpcode()) {
1909 switch (N->getOpcode()) {
1954 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1961 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
2035 switch (N->getOpcode()) {
2164 SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);
2175 Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
2177 Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,
2211 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2222 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
2233 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, N->getFlags());
2243 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
2253 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2320 SDValue NV = DAG.getNode(N->getOpcode(), DL, NVT, N->getOperand(0));
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 48 switch (N->getOpcode()) {
225 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
237 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
250 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
274 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
435 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
454 if (N->getOpcode() == ISD::CTTZ) {
462 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
492 unsigned NewOpc = N->getOpcode();
499 if (N->getOpcode() == ISD::FP_TO_UINT &&
504 if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
526 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
527 N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
536 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
543 return DAG.getNode(N->getOpcode(), dl, NVT);
559 if (N->getOpcode() == ISD::SIGN_EXTEND)
562 if (N->getOpcode() == ISD::ZERO_EXTEND)
565 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
571 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
635 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
659 unsigned Opcode = N->getOpcode();
732 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
732 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
734 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
734 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
755 SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
761 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
778 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
842 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
869 return DAG.getNode(N->getOpcode(), SDLoc(N),
877 return DAG.getNode(N->getOpcode(), SDLoc(N),
885 return DAG.getNode(N->getOpcode(), SDLoc(N),
979 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1017 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1044 if (N->getOpcode() == ISD::SMULO) {
1052 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1058 if (N->getOpcode() == ISD::UMULO) {
1147 switch (N->getOpcode()) {
1298 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1414 if (N->getOpcode() == ISD::VSELECT)
1419 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1618 switch (N->getOpcode()) {
1640 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
1644 SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
1666 switch (N->getOpcode()) {
1814 unsigned Opc = Node->getOpcode();
1844 if (N->getOpcode() == ISD::SHL) {
1865 if (N->getOpcode() == ISD::SRL) {
1886 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1942 switch (N->getOpcode()) {
1970 switch (N->getOpcode()) {
1978 if (N->getOpcode() != ISD::SHL)
1987 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1990 if (N->getOpcode() != ISD::SHL)
2024 switch (N->getOpcode()) {
2097 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2109 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2138 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2142 if (N->getOpcode() == ISD::ADD) {
2160 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2166 if (N->getOpcode() == ISD::ADD) {
2179 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2188 if (N->getOpcode() == ISD::ADD) {
2205 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2214 if (N->getOpcode() == ISD::ADD) {
2263 if (N->getOpcode() == ISD::ADDC) {
2289 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2291 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2308 switch(N->getOpcode()) {
2335 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2367 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2369 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2500 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
2532 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
2763 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2764 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2853 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2878 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
2879 N->getOpcode() == ISD::UMULFIXSAT);
2880 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
2881 N->getOpcode() == ISD::SMULFIXSAT);
3091 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3113 Node->getOpcode() == ISD::SADDO ?
3170 if (N->getOpcode() == ISD::SHL) {
3172 } else if (N->getOpcode() == ISD::SRL) {
3175 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3214 if (N->getOpcode() == ISD::SHL) {
3224 } else if (N->getOpcode() == ISD::SRL) {
3235 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3361 if (N->getOpcode() == ISD::UMULO) {
3594 switch (N->getOpcode()) {
4231 switch(N->getOpcode()) {
4244 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
4248 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4272 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 879 if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
917 if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
lib/CodeGen/SelectionDAG/LegalizeTypes.h 82 return N->getOpcode() == ISD::TargetConstant ||
83 N->getOpcode() == ISD::Register;
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 539 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
540 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 341 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
348 TLI.getStrictFPOperationAction(Node->getOpcode(),
352 if (TLI.getOperationAction(Node->getOpcode(), EltVT)
354 TLI.getStrictFPOperationAction(Node->getOpcode(), EltVT)
452 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
459 Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
478 Action = TLI.getOperationAction(Node->getOpcode(),
602 unsigned NewOpc = Op->getOpcode();
615 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
748 if (Scalarized->getOpcode() == ISD::MERGE_VALUES) {
771 switch (Op->getOpcode()) {
1400 SDValue ScalarOp = DAG.getNode(Op->getOpcode(), dl, ValueVTs, Opers);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 39 switch (N->getOpcode()) {
202 return DAG.getNode(N->getOpcode(), SDLoc(N),
210 return DAG.getNode(N->getOpcode(), SDLoc(N),
218 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
244 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers);
273 N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode();
396 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
403 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
423 switch (N->getOpcode()) {
474 if (Cond->getOpcode() == ISD::SETCC) {
587 switch (N->getOpcode()) {
681 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
694 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
834 switch (N->getOpcode()) {
1023 unsigned Opcode = N->getOpcode();
1038 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
1040 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
1052 unsigned Opcode = N->getOpcode();
1255 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
1257 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
1263 unsigned Opcode = N->getOpcode();
1336 Lo = DAG.getNode(N->getOpcode(), dl, LoValueVTs, OpsLo);
1337 Hi = DAG.getNode(N->getOpcode(), dl, HiValueVTs, OpsHi);
1385 SDValue Scalar = DAG.getNode(N->getOpcode(), dl, ChainVTs, Operands);
1424 unsigned Opcode = N->getOpcode();
1727 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1728 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1747 if (N->getOpcode() == ISD::FP_ROUND) {
1748 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1749 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1750 } else if (N->getOpcode() == ISD::STRICT_FP_ROUND) {
1751 Lo = DAG.getNode(N->getOpcode(), dl, { LoVT, MVT::Other },
1753 Hi = DAG.getNode(N->getOpcode(), dl, { HiVT, MVT::Other },
1759 Lo = DAG.getNode(N->getOpcode(), dl, { LoVT, MVT::Other },
1761 Hi = DAG.getNode(N->getOpcode(), dl, { HiVT, MVT::Other },
1769 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1770 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1810 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1814 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1815 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1970 switch (N->getOpcode()) {
2121 switch (N->getOpcode()) {
2146 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
2161 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other },
2163 Hi = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other },
2175 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
2176 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
2609 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2610 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
2662 Lo = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other },
2664 Hi = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other },
2699 switch (N->getOpcode()) {
2874 if (!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&
2875 TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
2914 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2923 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2933 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3,
3020 unsigned Opcode = N->getOpcode();
3032 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
3036 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
3096 unsigned Opcode = N->getOpcode();
3239 N->getOpcode(), DL, WideVTs, WideLHS, WideRHS).getNode();
3268 unsigned Opcode = N->getOpcode();
3352 unsigned Opcode = N->getOpcode();
3378 unsigned Opcode = N->getOpcode();
3445 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3464 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3471 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
3481 return DAG.getNode(N->getOpcode(), SDLoc(N),
3852 SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3902 if (N->getOpcode() != ISD::VSELECT)
3905 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3905 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3960 if (Cond->getOpcode() == ISD::SETCC) {
3963 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3994 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
4038 return DAG.getNode(N->getOpcode(), SDLoc(N),
4135 switch (N->getOpcode()) {
4260 switch (N->getOpcode()) {
4291 unsigned Opcode = N->getOpcode();
4591 switch (N->getOpcode()) {
4636 return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Op, N->getFlags());
4651 SDValue Select = DAG.getNode(N->getOpcode(), DL, LeftIn.getValueType(), Cond,
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 81 switch (ScegN->getOpcode()) {
118 switch (ScegN->getOpcode()) {
441 switch (N->getOpcode()) {
547 switch(N->getOpcode()) {
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 428 if (N->getOpcode() == ISD::CopyFromReg) {
482 if (Node->getOpcode() == ISD::INLINEASM ||
483 Node->getOpcode() == ISD::INLINEASM_BR) {
665 (N->getOpcode() == ISD::EntryToken || isPassiveNode(N)))
737 (N->getOpcode() != ISD::EntryToken && !isPassiveNode(N)))
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 323 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
450 if (N->getOpcode() == ISD::TokenFactor) {
474 if (N->getOpcode() == ISD::EntryToken)
495 if (N->getOpcode() == ISD::TokenFactor) {
532 if (N->getOpcode() == ISD::EntryToken)
701 switch (SU->getNode()->getOpcode()) {
1279 if (N->getOpcode() == ISD::CopyFromReg) {
1362 if (Node->getOpcode() == ISD::INLINEASM ||
1363 Node->getOpcode() == ISD::INLINEASM_BR) {
2032 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2249 if (N->getOpcode() != ISD::CopyToReg)
2271 if (PN->getOpcode() == ISD::CopyFromReg) {
2335 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2362 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2383 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
2433 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2450 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2711 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2954 if (N->getOpcode() == ISD::CopyToReg &&
3001 if (N->getOpcode() == ISD::CopyFromReg &&
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
122 if (Def->getOpcode() == ISD::CopyFromReg &&
154 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
404 if (NI->getOpcode() == ISD::TokenFactor)
426 if (SUNode->getOpcode() != ISD::CopyToReg)
500 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
547 if (Node->getOpcode() == ISD::CopyFromReg)
614 if (N && N->getOpcode() == ISD::TokenFactor) {
656 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h 79 if (Node->getOpcode() == ISD::EntryToken ||
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 154 while (N->getOpcode() == ISD::BITCAST)
157 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
198 while (N->getOpcode() == ISD::BITCAST)
201 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
234 if (N->getOpcode() != ISD::BUILD_VECTOR)
247 if (N->getOpcode() != ISD::BUILD_VECTOR)
473 switch (N->getOpcode()) {
641 AddNodeIDOpcode(ID, N->getOpcode());
660 switch (N->getOpcode()) {
706 if (N->getOpcode() == ISD::DELETED_NODE)
792 switch (N->getOpcode()) {
849 switch (N->getOpcode()) {
883 assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!");
884 assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!");
942 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
962 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
980 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
1040 switch (N->getOpcode()) {
1055 switch (N->getOpcode()) {
4458 unsigned OpOpcode = Operand.getNode()->getOpcode();
4752 if (GA->getOpcode() != ISD::GlobalAddress)
7749 unsigned OrigOpc = Node->getOpcode();
8089 switch (N.getOpcode()) {
8593 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
9019 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9145 switch (N->getOpcode()) {
9147 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands,
9159 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0],
9165 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
9181 unsigned Opcode = N->getOpcode();
9546 if (GA->getOpcode() == ISD::GlobalAddress &&
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 192 switch (Base->getOpcode()) {
212 unsigned int IndexResNo = (Base->getOpcode() == ISD::LOAD) ? 1 : 0;
231 if (Base->getOpcode() == ISD::ADD) {
240 if (Base->getOperand(1)->getOpcode() == ISD::MUL)
248 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
254 if (Index->getOpcode() != ISD::ADD ||
260 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 8794 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
8799 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 60 switch (getOpcode()) {
62 if (getOpcode() < ISD::BUILTIN_OP_END)
69 return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>";
73 const char *Name = TLI.getTargetNodeName(getOpcode());
75 return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
77 return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
144 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
797 if (Node.getOpcode() == ISD::EntryToken)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 758 if (N->getOpcode() != ISD::CopyToReg)
1135 if (N->getOpcode() == ISD::TokenFactor || N->getNodeId() < 0)
1138 if (Op->getOpcode() == ISD::TokenFactor)
1163 (TLI->getOperationAction(Node->getOpcode(), Node->getValueType(0))
2301 assert(ChainNode->getOpcode() != ISD::DELETED_NODE &&
2318 if (ChainNode->getOpcode() != ISD::TokenFactor)
2358 if (V->getOpcode() == ISD::EntryToken)
2362 if (V->getOpcode() == ISD::TokenFactor) {
2502 return N->getOpcode() == Opc;
2577 if (N->getOpcode() != ISD::AND) return false;
2590 if (N->getOpcode() != ISD::OR) return false;
2752 switch (NodeToMatch->getOpcode()) {
2788 NodeToMatch->getOpcode() == ISD::INLINEASM_BR);
3237 if (Imm->getOpcode() == ISD::Constant) {
3241 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3453 assert(NodeToMatch->getOpcode() != ISD::DELETED_NODE &&
3623 assert(N->getOpcode() == ISD::OR && "Unexpected opcode");
3646 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3647 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3648 N->getOpcode() != ISD::INTRINSIC_VOID) {
lib/CodeGen/SelectionDAG/StatepointLowering.cpp 339 if (CallEnd->getOpcode() == ISD::LOAD)
342 while (CallEnd->getOpcode() == ISD::CopyFromReg)
346 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END && "expected!");
lib/CodeGen/SelectionDAG/TargetLowering.cpp 90 if (Value->getOpcode() != ISD::CopyFromReg)
2856 if (N0->getOpcode() != ISD::ADD)
3152 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
3156 } else if (N0->getOpcode() == ISD::AND) {
3163 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
3210 unsigned N0Opc = N0->getOpcode();
3945 if (N->getOpcode() == ISD::ADD) {
5774 bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), N,
5802 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
5838 bool IsLeft = Node->getOpcode() == ISD::ROTL;
6122 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
6149 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
6228 if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
6280 if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
6478 if (Scalarized->getOpcode() == ISD::MERGE_VALUES)
6859 assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
6883 unsigned Opcode = Node->getOpcode();
6964 assert((Node->getOpcode() == ISD::SMULFIX ||
6965 Node->getOpcode() == ISD::UMULFIX ||
6966 Node->getOpcode() == ISD::SMULFIXSAT ||
6967 Node->getOpcode() == ISD::UMULFIXSAT) &&
6975 bool Saturating = (Node->getOpcode() == ISD::SMULFIXSAT ||
6976 Node->getOpcode() == ISD::UMULFIXSAT);
6977 bool Signed = (Node->getOpcode() == ISD::SMULFIX ||
6978 Node->getOpcode() == ISD::SMULFIXSAT);
7107 bool IsAdd = Node->getOpcode() == ISD::UADDO;
7136 bool IsAdd = Node->getOpcode() == ISD::SADDO;
7178 bool isSigned = Node->getOpcode() == ISD::SMULO;
7319 switch (Node->getOpcode()) {
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 144 switch(N->getOpcode()) {
265 return N->getOpcode() == Opc &&
504 if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
505 DL->getOpcode() != AArch64ISD::DUPLANE32)
699 if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
699 if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
700 Use->getOpcode() != ISD::ATOMIC_LOAD &&
701 Use->getOpcode() != ISD::ATOMIC_STORE)
1539 assert(N->getOpcode() == ISD::AND &&
1575 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1582 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1629 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
1637 if (Op->getOpcode() == ISD::TRUNCATE) {
1676 if (N->getOpcode() != ISD::SRL)
1708 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1708 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1728 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1729 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1766 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1768 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1773 assert(N->getOpcode() == ISD::SIGN_EXTEND);
1803 switch (N->getOpcode()) {
2194 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2283 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2442 if (N->getOpcode() != ISD::OR)
2464 if (N->getOpcode() != ISD::AND)
2496 switch (N->getOpcode()) {
2529 if (ShiftAmt->getOpcode() == ISD::ZERO_EXTEND ||
2530 ShiftAmt->getOpcode() == ISD::ANY_EXTEND)
2533 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
2533 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
2544 else if (ShiftAmt->getOpcode() == ISD::SUB &&
2826 if (IRG_SP->getOpcode() != ISD::INTRINSIC_W_CHAIN ||
2880 switch (Node->getOpcode()) {
lib/Target/AArch64/AArch64ISelLowering.cpp 1753 unsigned Opcode = Val->getOpcode();
1814 unsigned Opcode = Val->getOpcode();
2652 if (N->getOpcode() != ISD::BUILD_VECTOR)
2675 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2675 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2679 N->getOpcode());
2681 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
2699 return N->getOpcode() == ISD::SIGN_EXTEND ||
2704 return N->getOpcode() == ISD::ZERO_EXTEND ||
2709 unsigned Opcode = N->getOpcode();
2720 unsigned Opcode = N->getOpcode();
2812 return DAG.getNode(N0->getOpcode(), DL, VT,
7346 unsigned Opcode = N->getOpcode();
9223 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
9302 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
9410 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ADD ||
9411 N->use_begin()->getOpcode() == ISD::SUB))
9489 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
9490 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
9509 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
9553 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
9621 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
9644 unsigned Opc = Op->getOpcode();
9734 assert(N->getOpcode() == ISD::OR && "Unexpected root");
9926 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
9931 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
9941 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
9988 N0->getOpcode() == ISD::TRUNCATE &&
9989 N1->getOpcode() == ISD::TRUNCATE) {
10032 if (N1->getOpcode() != ISD::BITCAST)
10144 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
10247 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
10304 if (N->getOpcode() == ISD::ADD)
10335 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
10533 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
10599 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
10616 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
10617 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
10644 if (BasePtr->getOpcode() == ISD::ADD &&
10879 if (LD->getOpcode() != ISD::LOAD)
10913 if (User->getOpcode() != ISD::ADD
11016 if (User->getOpcode() != ISD::ADD ||
11144 switch(V.getNode()->getOpcode()) {
11327 unsigned CondOpcode = SubsNode->getOpcode();
11338 if (AndNode->getOpcode() != ISD::AND)
11473 if (Op->getOpcode() == ISD::TRUNCATE &&
11479 if (Op->getOpcode() == ISD::ANY_EXTEND &&
11491 switch (Op->getOpcode()) {
11545 unsigned NewOpc = N->getOpcode();
11675 if (N->getOpcode() != ISD::ADD)
11718 switch (N->getOpcode()) {
11824 if (Copy->getOpcode() == ISD::CopyToReg) {
11831 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
11836 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
11861 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
11861 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
11869 if (Op->getOpcode() == ISD::SUB)
11873 IsInc = (Op->getOpcode() == ISD::ADD);
12056 switch (N->getOpcode()) {
lib/Target/AArch64/AArch64ISelLowering.h 241 unsigned Opc = N.getOpcode();
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 105 assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2);
490 switch (N->getOpcode()) {
548 if (N->getOpcode() == ISD::CopyToReg) {
597 return CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
698 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
715 unsigned int Opc = N->getOpcode();
901 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT),
984 unsigned Opcode = N->getOpcode();
1048 unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64
1059 unsigned Opc = N->getOpcode() == ISD::UADDO ?
1143 bool Signed = N->getOpcode() == AMDGPUISD::MAD_I64_I32;
1924 bool Signed = N->getOpcode() == ISD::SRA;
1936 switch (N->getOpcode()) {
2012 assert(N->getOpcode() == ISD::BRCOND);
2086 bool IsFMA = N->getOpcode() == ISD::FMA;
2768 unsigned int Opc = N->getOpcode();
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 559 switch (N->getOpcode()) {
710 switch (N->getOpcode()) {
1169 switch (N->getOpcode()) {
2766 bool IsIntrin = Node24->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
2770 unsigned NewOpcode = Node24->getOpcode();
2968 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3029 switch (LHS->getOpcode()) {
3380 bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3875 switch(N->getOpcode()) {
4001 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
lib/Target/AMDGPU/R600ISelLowering.cpp 653 switch (N->getOpcode()) {
1312 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) {
1856 switch (N->getOpcode()) {
lib/Target/AMDGPU/SIISelLowering.cpp 4252 switch (N->getOpcode()) {
4383 if (I->getOpcode() == Opcode)
4390 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4443 if (Intr->getOpcode() == ISD::SETCC) {
4467 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
4468 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
8105 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
8253 if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &&
9120 unsigned Opc = N->getOpcode();
9438 unsigned Opc = N->getOpcode();
9596 unsigned Opc = N->getOpcode();
9869 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
9937 switch (N->getOpcode()) {
10249 if (Node->getOpcode() == ISD::CopyToReg) {
10814 assert(N->getOpcode() == ISD::CopyFromReg);
10818 if (N->getOpcode() == ISD::INLINEASM ||
10819 N->getOpcode() == ISD::INLINEASM_BR)
10821 } while (N->getOpcode() == ISD::CopyFromReg);
10828 switch (N->getOpcode()) {
lib/Target/ARC/ARCISelDAGToDAG.cpp 170 switch (N->getOpcode()) {
lib/Target/ARM/ARMISelDAGToDAG.cpp 303 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
320 return N->getOpcode() == Opc &&
355 if (N->getOpcode() != ISD::ADD)
443 if (Use->getOpcode() == ISD::CopyToReg)
594 assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
763 unsigned Opcode = Op->getOpcode();
799 unsigned Opcode = Op->getOpcode();
819 unsigned Opcode = Op->getOpcode();
898 unsigned Opcode = Op->getOpcode();
996 ((MemN->getOpcode() == ARMISD::VST1_UPD ||
997 MemN->getOpcode() == ARMISD::VLD1_UPD) &&
1300 unsigned Opcode = Op->getOpcode();
1352 unsigned Opcode = Op->getOpcode();
2644 if (N->getOpcode() == ISD::AND) {
2746 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2846 assert(N->getOpcode() == ARMISD::CMPZ);
2861 And->getOpcode() != ISD::AND)
2925 switch (N->getOpcode()) {
3291 unsigned Opc = N->getOpcode() == ARMISD::WLS ?
4787 SDValue New = CurDAG->getNode(N->getOpcode(), SDLoc(N),
lib/Target/ARM/ARMISelLowering.cpp 2876 if (Copy->getOpcode() == ISD::CopyToReg) {
2882 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2888 if (UI->getOpcode() != ISD::CopyToReg)
2911 } else if (Copy->getOpcode() == ISD::BITCAST) {
2916 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2930 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2931 UI->getOpcode() != ARMISD::INTRET_FLAG)
4167 } else if (Op->getOpcode() == ISD::BITCAST &&
4172 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4249 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4272 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4521 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4772 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
5680 if (Move->getOpcode() != ARMISD::VMOVhr)
5722 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5727 if (Copy->getOpcode() == ISD::CopyToReg &&
5728 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5911 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
6046 if (N->getOpcode() == ISD::SHL) {
6054 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6054 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6059 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
6070 (N->getOpcode() == ISD::SRA ? ARMISD::VSHLs : ARMISD::VSHLu);
6083 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6083 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6084 N->getOpcode() == ISD::SHL) &&
6087 unsigned ShOpc = N->getOpcode();
6131 if (!isOneConstant(N->getOperand(1)) || N->getOpcode() == ISD::SHL)
6146 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
7207 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7907 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
8218 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
8221 BVN->getOpcode() != ISD::BUILD_VECTOR)
8242 if (N->getOpcode() != ISD::BUILD_VECTOR)
8268 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
8278 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
8352 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
8352 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
8356 N->getOpcode());
8374 if (N->getOpcode() == ISD::BITCAST) {
8376 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
8384 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
8402 unsigned Opcode = N->getOpcode();
8413 unsigned Opcode = N->getOpcode();
8491 return DAG.getNode(N0->getOpcode(), DL, VT,
8846 if (N->getOpcode() != ISD::SDIV)
8996 (PassThru->getOpcode() == ARMISD::VMOVIMM &&
9279 switch (N->getOpcode()) {
9314 return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
10838 switch (N->getOpcode()) {
10872 else if (N->getOpcode() == ISD::ZERO_EXTEND)
10922 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
10949 if (N->getOpcode() == ARMISD::VUZP)
10953 if (N->getOpcode() == ARMISD::VTRN && N->getValueType(0) == MVT::v2i32)
11062 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11072 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
11073 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
11138 if (V->getOpcode() == ISD::UMUL_LOHI ||
11139 V->getOpcode() == ISD::SMUL_LOHI)
11244 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE ||
11245 AddeSubeNode->getOpcode() == ARMISD::SUBE) &&
11254 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE &&
11255 AddcSubcNode->getOpcode() != ARMISD::ADDC) ||
11256 (AddeSubeNode->getOpcode() == ARMISD::SUBE &&
11257 AddcSubcNode->getOpcode() != ARMISD::SUBC))
11273 if (AddeSubeNode->getOpcode() == ARMISD::ADDE &&
11274 AddcSubcOp0->getOpcode() != ISD::UMUL_LOHI &&
11275 AddcSubcOp0->getOpcode() != ISD::SMUL_LOHI &&
11276 AddcSubcOp1->getOpcode() != ISD::UMUL_LOHI &&
11277 AddcSubcOp1->getOpcode() != ISD::SMUL_LOHI)
11299 unsigned Opc = MULOp->getOpcode();
11351 LowAddSub->getNode()->getOpcode() == ISD::Constant &&
11355 if (AddcSubcNode->getOpcode() == ARMISD::SUBC) {
11364 } else if (AddcSubcNode->getOpcode() == ARMISD::SUBC)
11401 if (AddcNode->getOpcode() != ARMISD::ADDC)
11451 if ((AddcNode->getOpcode() == ARMISD::ADDC) &&
11452 (AddeNode->getOpcode() == ARMISD::ADDE) &&
11469 if (N->getOpcode() == ARMISD::SUBC) {
11473 if (LHS->getOpcode() == ARMISD::ADDE &&
11487 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
11513 unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE
11519 } else if (N->getOperand(1)->getOpcode() == ISD::SMUL_LOHI) {
11532 if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0)))
11588 if (N->getOpcode() != ISD::SHL)
11595 if (N->getOpcode() != ISD::SHL)
11598 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND &&
11598 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND &&
11599 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR)
11599 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR)
11604 if (N1->getOpcode() == ISD::ADD && Const->getAPIntValue().slt(0) &&
11666 switch(U->getOpcode()) {
11691 if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR &&
11691 if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR &&
11692 N->getOpcode() != ISD::XOR && N->getOpcode() != ISD::AND)
11692 N->getOpcode() != ISD::XOR && N->getOpcode() != ISD::AND)
11729 SDValue BinOp = DAG.getNode(N->getOpcode(), dl, MVT::i32, X,
11928 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
11928 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
11931 bool LeftShift = N0->getOpcode() == ISD::SHL;
12272 if (N0->getOpcode() == ARMISD::VCMP)
12275 else if (N0->getOpcode() == ARMISD::VCMPZ)
12278 if (N1->getOpcode() == ARMISD::VCMP)
12281 else if (N1->getOpcode() == ARMISD::VCMPZ)
12299 if (N0->getOpcode() == ARMISD::VCMP)
12304 if (N1->getOpcode() == ARMISD::VCMP)
12308 SDValue NewN0 = DCI.DAG.getNode(N0->getOpcode(), SDLoc(N0), VT, Ops0);
12309 SDValue NewN1 = DCI.DAG.getNode(N1->getOpcode(), SDLoc(N1), VT, Ops1);
12441 assert(N->getOpcode() == ARMISD::BFI);
12449 if (From->getOpcode() == ISD::SRL &&
12706 if (Use->getOpcode() != ISD::BITCAST ||
12720 if (Elt->getOpcode() == ISD::BITCAST) {
12778 if (Op->getOpcode() == ARMISD::PREDICATE_CAST) {
12875 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
12876 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
12877 const bool isStore = N->getOpcode() == ISD::STORE;
12887 if (User->getOpcode() != ISD::ADD ||
12949 switch (N->getOpcode()) {
13058 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
13074 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
13109 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
13137 if (User->getOpcode() != ARMISD::VDUPLANE ||
13343 if (Trunc->getOpcode() != ISD::TRUNCATE)
13413 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
13434 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
13508 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
13537 unsigned OpOpcode = Op.getNode()->getOpcode();
13746 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
13759 if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 &&
13760 N->getOperand(0)->getOpcode() == ISD::AND &&
13802 switch (N->getOpcode()) {
13817 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
13865 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
13914 switch (N->getOpcode()) {
13967 assert(CmpZ->getOpcode() == ARMISD::CMPZ);
13969 if (And->getOpcode() != ISD::AND)
13984 if (Op1->getOpcode() != ISD::OR)
14041 switch (N->getOpcode()) {
14098 if (N->getOpcode() == ISD::BRCOND) {
14103 assert(N->getOpcode() == ISD::BR_CC && "Expected BRCOND or BR_CC!");
14145 assert((N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BR)
14219 LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
14418 switch (N->getOpcode()) {
14829 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
14829 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
14830 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM))
14830 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM))
15127 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15127 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15136 assert(Ptr->getOpcode() == ISD::ADD);
15142 isInc = (Ptr->getOpcode() == ISD::ADD);
15150 assert(Ptr->getOpcode() == ISD::ADD);
15158 if (Ptr->getOpcode() == ISD::ADD) {
15172 isInc = (Ptr->getOpcode() == ISD::ADD);
15186 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15186 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15193 assert(Ptr->getOpcode() == ISD::ADD);
15198 isInc = Ptr->getOpcode() == ISD::ADD;
15211 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15211 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15221 assert(Ptr->getOpcode() == ISD::ADD);
15226 isInc = Ptr->getOpcode() == ISD::ADD;
15332 if (Op->getOpcode() != ISD::ADD || !isNonExt)
15365 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
15396 if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) &&
15918 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15918 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15919 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15919 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15921 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
15922 N->getOpcode() == ISD::SREM;
15936 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15936 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15937 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15937 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15939 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
15940 N->getOpcode() == ISD::SREM;
15962 unsigned Opcode = Op->getOpcode();
16040 bool isSigned = N->getOpcode() == ISD::SREM;
lib/Target/AVR/AVRISelDAGToDAG.cpp 224 if (Op->getOpcode() == ISD::FrameIndex) {
239 if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
239 if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
250 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) {
477 bool isSigned = N->getOpcode() == ISD::SMUL_LOHI;
533 unsigned Opcode = N->getOpcode();
lib/Target/AVR/AVRISelLowering.cpp 340 unsigned Opcode = Op->getOpcode();
720 switch (N->getOpcode()) {
802 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
802 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
808 if (Op->getOpcode() == ISD::SUB)
853 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
853 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
859 if (Op->getOpcode() == ISD::SUB)
lib/Target/BPF/BPFISelDAGToDAG.cpp 180 unsigned Opcode = Node->getOpcode();
261 unsigned opcode = LDAddrNode->getOpcode();
268 if (OP1N->getOpcode() <= ISD::BUILTIN_OP_END || OP1N->getNumOperands() == 0)
279 } else if (LDAddrNode->getOpcode() > ISD::BUILTIN_OP_END &&
331 unsigned Opcode = Node->getOpcode();
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 186 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
274 if (C->getOpcode() != ISD::INTRINSIC_W_CHAIN)
319 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
360 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
686 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
762 unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c
827 SDNode *T = CurDAG->MorphNodeTo(N, N->getOpcode(),
879 switch (N->getOpcode()) {
901 switch (N->getOpcode()) {
941 unsigned Opc = U->getOpcode();
965 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
965 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
981 if (I->getOpcode() != ISD::OR)
1029 if (I->getOpcode() != ISD::STORE)
1093 unsigned Opc = N->getOpcode();
1158 unsigned Opc = N->getOpcode();
1194 unsigned UseOpc = U->getOpcode();
1389 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1586 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1601 switch (N->getOpcode()) {
1880 assert(!TopLevel || N->getOpcode() == ISD::ADD);
1923 unsigned NOpcode = N->getOpcode();
2235 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
2235 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
2257 unsigned Opcode = N->getOpcode();
2266 if (N->hasOneUse() && Opcode == N->use_begin()->getOpcode())
2280 if (N->getOpcode() == ISD::LOAD)
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 943 switch (N->getOpcode()) {
958 N->use_begin()->getOpcode() == HexagonISD::VSPLATW;
lib/Target/Hexagon/HexagonISelLowering.cpp 562 if (Op->getOpcode() != ISD::ADD)
2895 if (N->getOpcode() != ISD::STORE)
2904 switch (N->getOpcode()) {
2949 if (Cond->getOpcode() == ISD::XOR) {
2951 if (C1->getOpcode() == HexagonISD::PTRUE) {
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 1496 unsigned MemOpc = BN->getOpcode();
1595 if (Cond->getOpcode() == ISD::XOR) {
1597 if (C1->getOpcode() == HexagonISD::QTRUE) {
lib/Target/Lanai/LanaiISelDAGToDAG.cpp 273 unsigned Opcode = Node->getOpcode();
lib/Target/Lanai/LanaiISelLowering.cpp 1350 switch (N->getOpcode()) {
1433 DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1472 switch (N->getOpcode()) {
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 391 switch (Node->getOpcode()) {
lib/Target/MSP430/MSP430ISelLowering.cpp 1337 if (Op->getOpcode() != ISD::ADD)
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 180 unsigned Opcode = Node->getOpcode();
lib/Target/Mips/MipsISelDAGToDAG.cpp 224 assert(Node->getOpcode() == ISD::ADD && "Should only get 'add' here.");
268 unsigned Opcode = Node->getOpcode();
lib/Target/Mips/MipsISelLowering.cpp 576 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
774 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
1017 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1018 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1019 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1020 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1039 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1156 unsigned Opc = N->getOpcode();
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 554 if (N->getOpcode() == ISD::BITCAST)
630 if (N->getOpcode() == ISD::BITCAST)
661 if (N->getOpcode() == ISD::BITCAST)
695 if (N->getOpcode() == ISD::BITCAST)
717 if (N->getOpcode() == ISD::BITCAST)
734 unsigned Opcode = Node->getOpcode();
899 if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
900 Node->getOperand(2)->getOpcode() != ISD::Constant)
lib/Target/Mips/MipsSEISelLowering.cpp 489 unsigned Op0Opcode = Op0->getOpcode();
556 if (N->getOpcode() == ISD::BITCAST)
578 if (N->getOpcode() != ISD::XOR)
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
610 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
905 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
912 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
913 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
920 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
1016 if (NotOp->getOpcode() == ISD::OR)
1029 switch (N->getOpcode()) {
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 83 switch (N->getOpcode()) {
615 if (U->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
639 if (Vector->getOpcode() == ISD::BITCAST) {
1048 switch (N->getOpcode()) {
1065 assert(N->getOpcode() == NVPTXISD::LoadV4 && "Unexpected load opcode.");
1072 switch (N->getOpcode()) {
1099 switch (N->getOpcode()) {
1127 switch (N->getOpcode()) {
1147 switch (N->getOpcode()) {
1175 switch (N->getOpcode()) {
1195 switch (N->getOpcode()) {
1239 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1292 switch (N->getOpcode()) {
1368 switch (N->getOpcode()) {
1438 switch (N->getOpcode()) {
1514 switch (N->getOpcode()) {
1584 switch (N->getOpcode()) {
1914 switch (N->getOpcode()) {
1937 assert(N->getOpcode() == NVPTXISD::StoreV4 && "Unexpected load opcode.");
1950 switch (N->getOpcode()) {
1971 switch (N->getOpcode()) {
1994 switch (N->getOpcode()) {
2014 switch (N->getOpcode()) {
2037 switch (N->getOpcode()) {
2057 switch (N->getOpcode()) {
2102 switch (Node->getOpcode()) {
2180 switch (N->getOpcode()) {
2253 switch (N->getOpcode()) {
2282 switch (N->getOpcode()) {
2348 switch (N->getOpcode()) {
2866 switch (N->getOpcode()) {
3385 if (N->getOpcode() == ISD::AND) {
3441 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
3441 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
3442 if (LHS->getOpcode() == ISD::AND) {
3494 } else if (LHS->getOpcode() == ISD::SHL) {
3537 if (N->getOpcode() == ISD::SRA) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 4390 if (User->getOpcode() != ISD::FADD)
4489 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4490 Val->getOpcode() == NVPTXISD::LoadV4) {
4542 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4542 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4551 bool IsSigned = N->getOpcode() == ISD::SREM;
4558 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4655 if (N->getOpcode() == ISD::MUL) {
4662 if (N->getOpcode() == ISD::SHL) {
4758 switch (N->getOpcode()) {
5049 switch (N->getOpcode()) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 486 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
496 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
569 return N->getOpcode() == Opc
596 unsigned Opcode = N->getOpcode();
1040 Use->isMachineOpcode() ? Use->getMachineOpcode() : Use->getOpcode();
2504 switch (N->getOpcode()) {
2531 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2532 N->getOpcode() == ISD::SIGN_EXTEND) &&
2539 N->getOpcode() == ISD::ZERO_EXTEND)
2546 N->getOpcode() == ISD::SIGN_EXTEND ?
2556 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2557 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2573 assert(isLogicOp(N->getOpcode()) &&
3563 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3564 CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
3565 CompareUse->getOpcode() != ISD::SELECT &&
3566 !isLogicOp(CompareUse->getOpcode())) {
3632 switch (N->getOpcode()) {
3657 switch (N->getOpcode()) {
4210 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
4359 if (N->getOpcode() == ISD::ADD &&
4371 switch (N->getOpcode()) {
4689 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4747 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4800 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
4990 CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ
5248 assert(N->getOpcode() == ISD::OR &&
5466 if (N->getOpcode() != ISD::ZERO_EXTEND &&
5467 N->getOpcode() != ISD::SIGN_EXTEND &&
5468 N->getOpcode() != ISD::ANY_EXTEND)
5481 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
5494 return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl,
5534 switch (N->getOpcode()) {
lib/Target/PowerPC/PPCISelLowering.cpp 2534 UI->getOpcode() != ISD::SCALAR_TO_VECTOR)
7573 if (Origin->getOpcode() != ISD::LOAD)
7590 if (UI->getOpcode() != ISD::SINT_TO_FP &&
7591 UI->getOpcode() != ISD::UINT_TO_FP)
9544 if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
9545 (Op.getOpcode() == ISD::UREM && UI->getOpcode() == ISD::UDIV))
10190 switch (N->getOpcode()) {
10212 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
10244 isOperationCustom(N->getOpcode(), TrgVT) &&
11770 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
11816 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
11896 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
11929 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
11943 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
11975 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
11989 if (UI->getOpcode() != ISD::ZERO_EXTEND)
12030 if (N->getOpcode() == ISD::TRUNCATE &&
12038 if (N->getOpcode() == ISD::SETCC ||
12039 N->getOpcode() == ISD::SELECT_CC) {
12044 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
12056 return (N->getOpcode() == ISD::SETCC ? ConvertSETCCToSubtract(N, DCI)
12088 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
12088 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
12114 if (N->getOpcode() == ISD::TRUNCATE)
12179 if (User->getOpcode() == ISD::SELECT) {
12182 } else if (User->getOpcode() == ISD::SELECT_CC) {
12203 if (User->getOpcode() == ISD::SELECT) {
12206 } else if (User->getOpcode() == ISD::SELECT_CC) {
12288 if (N->getOpcode() == ISD::TRUNCATE)
12389 if (User->getOpcode() == ISD::SELECT) {
12393 } else if (User->getOpcode() == ISD::SELECT_CC) {
12414 if (User->getOpcode() == ISD::SELECT) {
12418 } else if (User->getOpcode() == ISD::SELECT_CC) {
12431 if (N->getOpcode() != ISD::ANY_EXTEND) {
12442 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
12446 (N->getOpcode() == ISD::SIGN_EXTEND &&
12467 else if (N->getOpcode() == ISD::SIGN_EXTEND)
12470 else if (N->getOpcode() == ISD::ZERO_EXTEND)
12532 if (N->getOpcode() == ISD::SIGN_EXTEND)
12534 else if (N->getOpcode() == ISD::ZERO_EXTEND)
12562 if (N->getOpcode() == ISD::ZERO_EXTEND)
12568 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
12581 assert(N->getOpcode() == ISD::SETCC &&
12628 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
12713 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
12932 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
13015 assert((N->getOpcode() == ISD::SINT_TO_FP ||
13016 N->getOpcode() == ISD::UINT_TO_FP) &&
13039 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
13127 switch (N->getOpcode()) {
13196 switch (N->getOpcode()) {
13344 if (LSBase->getOpcode() == ISD::LOAD) {
13352 if (LSBase->getOpcode() == ISD::STORE) {
13368 switch (N->getOpcode()) {
13546 if (Trunc->getOpcode() != ISD::TRUNCATE)
13549 if (Trunc->getOpcode() != ISD::TRUNCATE ||
13553 if (RightShift->getOpcode() != ISD::SRL ||
13560 if (Trunc2->getOpcode() != ISD::TRUNCATE ||
13568 if (Bitcast->getOpcode() != ISD::BITCAST ||
13571 if (Bitcast2->getOpcode() != ISD::BITCAST ||
13774 N->getOperand(1)->getOpcode() == ISD::ADD) {
13787 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
13802 if (UI->getOpcode() == ISD::ADD &&
13810 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
13934 if (UI->getOpcode() == PPCISD::VCMPo &&
13965 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
15106 unsigned Opcode = N->getOpcode();
15124 N1->getOpcode() == ISD::AND)
15472 assert((N->getOpcode() == ISD::ABS) && "Need ABS node here");
15516 assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here");
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 90 if (Node->getOpcode() == ISD::AND &&
108 unsigned Opcode = Node->getOpcode();
lib/Target/RISCV/RISCVISelLowering.cpp 840 RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode());
854 SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1);
864 switch (N->getOpcode()) {
927 switch (N->getOpcode()) {
934 if (Op0->getOpcode() == RISCVISD::BuildPairF64)
991 if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) {
lib/Target/Sparc/SparcISelDAGToDAG.cpp 315 SDValue New = CurDAG->getNode(N->getOpcode(), SDLoc(N),
329 switch (N->getOpcode()) {
352 if (N->getOpcode() == ISD::SDIV) {
364 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
lib/Target/Sparc/SparcISelLowering.cpp 1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
3089 switch (N->getOpcode()) {
3342 switch (N->getOpcode()) {
3352 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3378 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 463 unsigned Op0Code = Op0->getOpcode();
464 unsigned Op1Code = Op1->getOpcode();
522 if (Base->getOpcode() == ISD::FrameIndex)
551 unsigned IndexOpcode = Index->getOpcode();
970 if (Count == 1 && N->getOpcode() != ISD::AND)
1332 unsigned Opc = StoredVal->getOpcode();
1467 unsigned Opcode = Node->getOpcode();
1704 if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) {
1714 if (CCUser->getOpcode() == ISD::CopyToReg ||
1898 switch (N->getOpcode()) {
lib/Target/SystemZ/SystemZISelLowering.cpp 2148 if (N->getOpcode() == ISD::SUB &&
2168 if (N->getOpcode() == ISD::FNEG) {
2195 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
5070 switch (N->getOpcode()) {
5488 unsigned Opcode = N->getOpcode();
5535 if (UI->getOpcode() == SystemZISD::REPLICATE) {
5759 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5810 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5958 if (ICmp->getOpcode() != SystemZISD::ICMP)
5966 if (CompareLHS->getOpcode() == SystemZISD::SELECT_CCMASK) {
6002 if (CompareLHS->getOpcode() == ISD::SRA) {
6007 if (SHL->getOpcode() != ISD::SHL)
6013 if (IPM->getOpcode() != SystemZISD::IPM)
6102 if (Select->getOpcode() != SystemZISD::SELECT_CCMASK)
6149 if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)
6156 switch(N->getOpcode()) {
lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp 90 switch (Node->getOpcode()) {
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 789 if (Callee->getOpcode() == ISD::GlobalAddress) {
955 switch (N->getOpcode()) {
1319 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1323 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG)
1326 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1331 Index->getOperand(1)->getOpcode() != ISD::Constant ||
lib/Target/X86/X86ISelDAGToDAG.cpp 355 if (User->getOpcode() == ISD::STORE &&
371 if (User->getOpcode() == ISD::ADD &&
379 if (User->getOpcode() == X86ISD::ADD ||
380 User->getOpcode() == ISD::ADD ||
381 User->getOpcode() == X86ISD::SUB ||
382 User->getOpcode() == ISD::SUB) {
391 if (OtherOp->getOpcode() == ISD::CopyFromReg &&
441 assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
538 unsigned Opcode = N->getOpcode();
564 if (N->getOpcode() == ISD::AND)
587 switch (U->getOpcode()) {
622 if (U->getOpcode() == ISD::AND &&
630 if (U->getOpcode() == ISD::AND &&
638 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) &&
638 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) &&
663 if (U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR) {
663 if (U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR) {
672 if (U->getOpcode() == ISD::AND) {
706 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR &&
796 if (N->getOpcode() == X86ISD::AND && !N->hasAnyUseOfValue(1)) {
806 switch (N->getOpcode()) {
815 switch (N->getOpcode()) {
837 switch (N->getOpcode()) {
859 unsigned NewOpc = N->getOpcode() == ISD::ANY_EXTEND
879 switch (N->getOpcode()) {
920 switch (N->getOpcode()) {
930 Res = CurDAG->getNode(N->getOpcode(), dl, VecVT, Op0, Op1);
946 ((N->getOpcode() == X86ISD::CALL && !Subtarget->slowTwoMemOps()) ||
947 (N->getOpcode() == X86ISD::TC_RETURN &&
969 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
987 switch (N->getOpcode()) {
1010 if (N->getOpcode() == ISD::FP_EXTEND)
1021 if (N->getOpcode() == ISD::FP_ROUND)
1068 if (N->getOpcode() == ISD::STRICT_FP_EXTEND)
1079 if (N->getOpcode() == ISD::STRICT_FP_ROUND)
1992 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
2042 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
2043 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
2044 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
2045 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
2261 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
2262 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
2263 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
2264 Parent->getOpcode() != X86ISD::ENQCMD && // Fixme
2265 Parent->getOpcode() != X86ISD::ENQCMDS && // Fixme
2266 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
2267 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
2372 if (N->getOpcode() != X86ISD::Wrapper)
2379 if (N->getOpcode() == ISD::TargetGlobalTLSAddress)
2383 if (N->getOpcode() != ISD::TargetGlobalAddress)
2565 unsigned Opc = N.getOperand(0)->getOpcode();
2604 if (N->getOpcode() != X86ISD::VBROADCAST_LOAD ||
2623 if (N->getOpcode() == ISD::TRUNCATE)
2625 if (N->getOpcode() != X86ISD::Wrapper)
2667 if (UI->getOpcode() != ISD::CopyToReg ||
2703 if (UI->getOpcode() != ISD::CopyToReg ||
2759 unsigned UIOpc = UI->getOpcode();
2942 unsigned Opc = StoredVal->getOpcode();
3189 (Node->getOpcode() == ISD::AND || Node->getOpcode() == ISD::SRL) &&
3189 (Node->getOpcode() == ISD::AND || Node->getOpcode() == ISD::SRL) &&
3215 if (V->getOpcode() == ISD::TRUNCATE && checkOneUse(V)) {
3228 if (Mask->getOpcode() != ISD::ADD || !checkOneUse(Mask))
3235 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0))
3261 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0))
3314 if (Node->getOpcode() != ISD::SRL)
3317 if (N0->getOpcode() != ISD::SHL || !checkOneUse(N0))
3337 if (Node->getOpcode() == ISD::AND) {
3470 if (N0->getOpcode() != ISD::SRL && N0->getOpcode() != ISD::SRA)
3470 if (N0->getOpcode() != ISD::SRL && N0->getOpcode() != ISD::SRA)
3650 if (ShiftAmt->getOpcode() == ISD::TRUNCATE)
3657 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
3657 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
3667 } else if (ShiftAmt->getOpcode() == ISD::SUB &&
3724 unsigned Opcode = N->getOpcode();
3842 assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB) &&
3842 assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB) &&
3873 unsigned NewOpcode = Node->getOpcode() == ISD::ADD ? ISD::SUB : ISD::ADD;
4303 assert(N->getOpcode() == ISD::OR && "Unexpected opcode!");
4351 unsigned Opcode = Node->getOpcode();
5205 switch (Node->getOpcode()) {
lib/Target/X86/X86ISelLowering.cpp 2675 if (Copy->getOpcode() == ISD::CopyToReg) {
2681 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2687 if (UI->getOpcode() != X86ISD::RET_FLAG)
3999 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
4000 Callee->getOpcode() == ISD::ExternalSymbol) {
4514 unsigned Opcode = Op.getNode()->use_begin()->getOpcode();
4882 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() ||
4883 UI->use_begin()->getOpcode() != ISD::STORE)
5115 assert(((N->getOpcode() == ISD::SHL &&
5117 (N->getOpcode() == ISD::SRL &&
5573 if (N->getOpcode() == ISD::CONCAT_VECTORS) {
5578 if (N->getOpcode() == ISD::INSERT_SUBVECTOR &&
5931 if (Ptr->getOpcode() == X86ISD::Wrapper ||
5932 Ptr->getOpcode() == X86ISD::WrapperRIP)
6146 if (Ptr->getOpcode() == X86ISD::Wrapper ||
6147 Ptr->getOpcode() == X86ISD::WrapperRIP)
6428 switch (N->getOpcode()) {
8095 unsigned Opc = U->getOpcode();
8624 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
17303 if ((User->getOpcode() != ISD::STORE ||
17305 (User->getOpcode() != ISD::BITCAST ||
19750 if (User->getOpcode() == ISD::FNEG)
20003 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
20009 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
20009 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
20010 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
20036 switch (Op->getOpcode()) {
20084 if (UI->getOpcode() != ISD::CopyToReg &&
20085 UI->getOpcode() != ISD::SETCC &&
20086 UI->getOpcode() != ISD::STORE)
22080 if (User->getOpcode() == ISD::BR) {
22121 if (User->getOpcode() == ISD::BR) {
25167 bool IsSigned = Op->getOpcode() == ISD::MULHS;
25391 switch (Op->getOpcode()) {
27106 switch (N->getOpcode()) {
27141 unsigned Opc = N->getOpcode();
27821 switch (N->getOpcode()) {
27893 SDValue Res = DAG.getNode(N->getOpcode(), dl, WideVT, InVec0, InVec1);
27934 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
27956 SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1);
28053 assert(N->getOpcode() == ISD::SIGN_EXTEND && "Unexpected opcode");
28090 In = DAG.getNode(N->getOpcode(), dl, InVT, In);
28099 SDValue Lo = getExtendInVec(N->getOpcode(), dl, LoVT, In, DAG);
28109 Hi = getExtendInVec(N->getOpcode(), dl, HiVT, Hi, DAG);
28118 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
28136 Res = DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
28197 Res = DAG.getNode(N->getOpcode(), SDLoc(N), VecVT, Res);
31806 if (N->getOpcode() == X86ISD::Wrapper || N->getOpcode() == X86ISD::WrapperRIP)
31806 if (N->getOpcode() == X86ISD::Wrapper || N->getOpcode() == X86ISD::WrapperRIP)
33506 if (User != N.getNode() && User->getOpcode() == X86ISD::VBROADCAST &&
33848 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
33886 IsSubAdd = Op0Even ? V1->getOpcode() == ISD::FADD
33887 : V2->getOpcode() == ISD::FADD;
33901 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
34018 unsigned Opcode = N->getOpcode();
34169 if (isTargetShuffle(N->getOpcode())) {
34193 if (N->getOpcode() == X86ISD::VZEXT_MOVL &&
34220 if (N->getOpcode() == X86ISD::VZEXT_MOVL && !DCI.isBeforeLegalizeOps() &&
34234 if (N->getOpcode() == X86ISD::VZEXT_MOVL && N->getOperand(0).hasOneUse() &&
34290 unsigned UseOpc = Use->getOpcode();
35334 assert(N->getOpcode() == ISD::BITCAST && "Expected a bitcast");
36087 return DAG.getNode(N->getOpcode(), dl, VT, Src, Idx);
36168 assert(ExtElt->getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Expected extract");
36267 assert(ExtElt->getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unexpected caller");
36391 bool IsPextr = N->getOpcode() != ISD::EXTRACT_VECTOR_ELT;
36482 if (Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
36528 if (N->getOpcode() != ISD::VSELECT)
36632 unsigned Opcode = N->getOpcode();
36731 if ((N->getOpcode() != ISD::VSELECT &&
36732 N->getOpcode() != X86ISD::BLENDV) ||
36774 if ((UI->getOpcode() != ISD::VSELECT &&
36775 UI->getOpcode() != X86ISD::BLENDV) ||
36792 if (U->getOpcode() == X86ISD::BLENDV)
36989 if (Subtarget.hasAVX512() && N->getOpcode() == ISD::SELECT &&
37015 return DAG.getNode(N->getOpcode(), DL, VT, Cond, LHS, RHS);
37072 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
37090 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
37117 Other->getOpcode() == ISD::SUB && OpRHS == CondRHS)
37130 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
37159 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
37227 return DAG.getNode(N->getOpcode(), DL, VT,
37475 if (Cond->getOpcode() == X86ISD::CMP) {
37485 switch (Cond->getOpcode()) {
38178 N->use_begin()->getOpcode() == ISD::ADD))
38416 unsigned Opcode = N->getOpcode();
38516 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() ||
38516 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() ||
38517 X86ISD::VSRL == N->getOpcode()) &&
38531 unsigned X86Opc = getTargetVShiftUniformOpcode(N->getOpcode(), false);
38549 unsigned Opcode = N->getOpcode();
38628 assert(((N->getOpcode() == X86ISD::PINSRB && VT == MVT::v16i8) ||
38629 (N->getOpcode() == X86ISD::PINSRW && VT == MVT::v8i16)) &&
38676 switch (UI->getOpcode()) {
38753 assert(N->getOpcode() == ISD::AND);
38788 assert((N->getOpcode() == ISD::ANY_EXTEND ||
38789 N->getOpcode() == ISD::ZERO_EXTEND ||
38790 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
38795 if (Narrow->getOpcode() != ISD::XOR &&
38796 Narrow->getOpcode() != ISD::AND &&
38797 Narrow->getOpcode() != ISD::OR)
38821 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), VT))
38832 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, VT, N0, N1);
38833 unsigned Opcode = N->getOpcode();
38871 switch (N->getOpcode()) {
39112 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!");
39291 assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
39338 if (N->getOpcode() != ISD::OR)
39398 return N->getOpcode() == ISD::SUB && N->getOperand(1) == V &&
39440 assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
39518 return (N->getOpcode() == ISD::OR && N->hasOneUse());
39530 return N->getOpcode() == X86ISD::SETCC && N->hasOneUse() &&
39546 OR = (LHS->getOpcode() == ISD::OR) ? LHS.getNode() : RHS.getNode();
39576 if (RHS->getOpcode() == ISD::OR)
40918 bool IsFadd = N->getOpcode() == ISD::FADD;
40920 assert((IsFadd || N->getOpcode() == ISD::FSUB) && "Wrong opcode");
40939 assert(N->getOpcode() == ISD::TRUNCATE && "Wrong opcode");
41418 if (N->getOpcode() == ISD::FNEG)
41702 switch (N->getOpcode()) {
41716 if (N->getOpcode() != ISD::XOR)
41721 if (!RHSC || RHSC->getZExtValue() != 1 || LHS->getOpcode() != X86ISD::SETCC)
41875 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
41875 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
41893 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
41893 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
41902 switch (N->getOpcode()) {
41928 auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN;
42008 SDValue Convert = DAG.getNode(N->getOpcode(), dl, VT,
42043 SDValue Convert = DAG.getNode(N->getOpcode(), dl, VT,
42099 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
42161 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
42203 if (Ext->getOpcode() != ISD::SIGN_EXTEND &&
42204 Ext->getOpcode() != ISD::ZERO_EXTEND)
42216 bool Sext = Ext->getOpcode() == ISD::SIGN_EXTEND;
42239 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
42239 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
42250 SDValue NewExt = DAG.getNode(Ext->getOpcode(), SDLoc(Ext), VT, AddOp0);
42279 unsigned ExtendOpcode = Extend->getOpcode();
42324 unsigned Opcode = N->getOpcode();
42444 if (N->getOpcode() == ISD::ZERO_EXTEND)
42543 negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC, false);
42565 unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), false, true, false);
43115 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
43116 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
43134 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
43178 return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), NewExtElt);
43299 switch (User->getOpcode()) {
43337 switch (User->getOpcode()) {
43445 assert((X86ISD::ADD == N->getOpcode() || X86ISD::SUB == N->getOpcode()) &&
43445 assert((X86ISD::ADD == N->getOpcode() || X86ISD::SUB == N->getOpcode()) &&
43452 unsigned GenericOpc = X86ISD::ADD == N->getOpcode() ? ISD::ADD : ISD::SUB;
43472 MatchGeneric(RHS, LHS, X86ISD::SUB == N->getOpcode());
43536 bool IsSub = N->getOpcode() == ISD::SUB;
43902 if (Mul->getOpcode() != ISD::MUL ||
44256 if (N->getOpcode() == X86ISD::PCMPEQ)
44258 if (N->getOpcode() == X86ISD::PCMPGT)
44795 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), RHS, LHS);
44822 return DAG.getNode(N->getOpcode(), dl, MVT::v2i64, LHS, RHS);
44832 return DAG.getNode(N->getOpcode(), dl, MVT::v2i64, LHS, RHS);
44851 ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
44867 if (Subtarget.hasAVX() && N->getOpcode() != ISD::SIGN_EXTEND_VECTOR_INREG) {
44894 switch (N->getOpcode()) {
45130 if (User->getOpcode() != ISD::ATOMIC_STORE)
lib/Target/X86/X86ISelLowering.h 1530 return N->getOpcode() == X86ISD::VTRUNCSTORES ||
1531 N->getOpcode() == X86ISD::VTRUNCSTOREUS;
1550 return N->getOpcode() == X86ISD::VMTRUNCSTORES ||
1551 N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
1563 return N->getOpcode() == X86ISD::VTRUNCSTORES;
1575 return N->getOpcode() == X86ISD::VTRUNCSTOREUS;
1588 return N->getOpcode() == X86ISD::VMTRUNCSTORES;
1601 return N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
1621 return N->getOpcode() == X86ISD::MGATHER ||
1622 N->getOpcode() == X86ISD::MSCATTER;
1636 return N->getOpcode() == X86ISD::MGATHER;
1650 return N->getOpcode() == X86ISD::MSCATTER;
lib/Target/XCore/XCoreISelDAGToDAG.cpp 133 switch (N->getOpcode()) {
220 if (Chain->getOpcode() != ISD::TokenFactor)
242 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
272 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
273 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
lib/Target/XCore/XCoreISelLowering.cpp 233 switch (N->getOpcode()) {
695 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
695 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
698 if (N->getOpcode() == ISD::ADD)
719 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
939 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
970 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP");
1593 switch (N->getOpcode()) {