|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc20521 MF.getSubtarget().getFrameLowering());
gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc 30 if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
35 if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc48810 MF.getSubtarget().getFrameLowering());
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc12385 MF.getSubtarget().getFrameLowering());
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 866 MF.getSubtarget().getFrameLowering());
gen/lib/Target/ARM/ARMGenRegisterInfo.inc16088 MF.getSubtarget().getFrameLowering());
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 1770 MF.getSubtarget().getFrameLowering());
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 752 MF.getSubtarget().getFrameLowering());
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72225 case 1: return (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72227 case 3: return (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72230 case 6: return (HST->useHVXOps()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72231 case 7: return (HST->useHVXOps()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72233 case 9: return (HST->useHVXOps()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72234 case 10: return (HST->useHVXOps()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72240 case 16: return (HST->hasV60Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72242 case 18: return (HST->hasV60Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72243 case 19: return (HST->hasV62Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72245 case 21: return (HST->hasV62Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72246 case 22: return (HST->hasV65Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72248 case 24: return (HST->hasV65Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72249 case 25: return (HST->hasV62Ops()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72250 case 26: return (HST->hasV66Ops()) && (HST->useHVX64BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72252 case 28: return (HST->hasV66Ops()) && (HST->useHVX128BOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
72253 case 29: return (HST->hasV65Ops()) && (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length64b"));
72255 case 31: return (HST->hasV65Ops()) && (HST->useHVXOps()) && (MF->getSubtarget().checkFeatures("+hvx-length128b"));
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 3729 MF.getSubtarget().getFrameLowering());
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 978 MF.getSubtarget().getFrameLowering());
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 636 MF.getSubtarget().getFrameLowering());
gen/lib/Target/Mips/MipsGenCallingConv.inc 117 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
144 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
273 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
373 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
378 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
392 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
404 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
405 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) {
418 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
419 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) {
445 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
482 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) {
494 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) {
506 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) {
518 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) {
536 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
565 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
578 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
599 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
615 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
622 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
682 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N32()) {
687 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N64()) {
710 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
727 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
817 if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
829 if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 7461 MF.getSubtarget().getFrameLowering());
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 1337 MF.getSubtarget().getFrameLowering());
gen/lib/Target/PowerPC/PPCGenCallingConv.inc 48 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasQPX()) {
66 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
78 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasP9Vector()) {
128 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
139 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
147 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
154 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
188 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
200 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
207 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
234 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
242 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
250 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
276 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasP9Vector()) {
394 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
406 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
447 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
459 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
471 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
483 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) {
491 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasP9Vector()) {
505 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasQPX()) {
523 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
639 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasP9Vector()) {
653 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasQPX()) {
671 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
692 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
704 if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) {
751 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasP9Vector()) {
762 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasQPX()) {
777 if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) {
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 5887 MF.getSubtarget().getFrameLowering());
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13749 case 0: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13751 case 2: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13752 case 3: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13754 case 5: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13755 case 6: return (MF->getSubtarget().checkFeatures("-64bit"));
13756 case 7: return (MF->getSubtarget().checkFeatures("+64bit"));
13757 case 8: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13759 case 10: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13760 case 11: return (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"));
13762 case 13: return (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"));
13764 case 15: return (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"));
13765 case 16: return (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"));
13766 case 17: return (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"));
13768 case 19: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13770 case 21: return (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"));
13771 case 22: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13772 case 23: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13773 case 24: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13774 case 25: return (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"));
13776 case 27: return (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"));
13777 case 28: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13779 case 30: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13781 case 32: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13783 case 34: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
13784 case 35: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
13786 case 37: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1905 MF.getSubtarget().getFrameLowering());
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 2850 MF.getSubtarget().getFrameLowering());
gen/lib/Target/SystemZ/SystemZGenCallingConv.inc 101 if (static_cast<const SystemZSubtarget&>(State.getMachineFunction().getSubtarget()).hasVector()) {
120 if (static_cast<const SystemZSubtarget&>(State.getMachineFunction().getSubtarget()).hasVector()) {
134 if (static_cast<const SystemZSubtarget&>(State.getMachineFunction().getSubtarget()).hasVector()) {
225 if (static_cast<const SystemZSubtarget&>(State.getMachineFunction().getSubtarget()).hasVector()) {
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 3024 MF.getSubtarget().getFrameLowering());
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 590 MF.getSubtarget().getFrameLowering());
gen/lib/Target/X86/X86GenCallingConv.inc 172 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
184 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
196 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
208 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
274 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
279 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
300 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
321 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
436 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
547 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
601 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
795 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
859 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
868 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
878 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
902 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
919 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
936 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
947 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
972 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1036 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1189 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1253 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1339 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1355 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1401 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1466 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1467 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1548 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1566 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1585 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1686 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1703 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1720 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1861 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1928 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1940 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
1950 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1974 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1991 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2008 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2019 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2044 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2324 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2391 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2403 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2413 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2437 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2454 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2471 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2482 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2507 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2642 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2830 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
2887 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2924 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2936 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
3096 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3105 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3125 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3142 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3159 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3176 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3259 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3270 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3669 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3681 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3701 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3718 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3735 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3752 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3869 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3881 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3901 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3918 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3935 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3952 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
gen/lib/Target/X86/X86GenRegisterInfo.inc10167 MF.getSubtarget().getFrameLowering());
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 616 MF.getSubtarget().getFrameLowering());
include/llvm/CodeGen/LiveRangeEdit.h 143 VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate),
include/llvm/CodeGen/MachinePipeliner.h 203 P.MF->getSubtarget().getSMSMutations(Mutations);
509 : ST(mf->getSubtarget()), MRI(mf->getRegInfo()), ProcItinResources(&ST) {}
include/llvm/CodeGen/MachineRegisterInfo.h 154 return MF->getSubtarget().getRegisterInfo();
include/llvm/CodeGen/ModuloSchedule.h 257 : Schedule(S), MF(MF), ST(MF.getSubtarget()), MRI(MF.getRegInfo()),
306 : Schedule(S), MF(MF), ST(MF.getSubtarget()), MRI(MF.getRegInfo()),
include/llvm/CodeGen/SelectionDAG.h 419 const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
lib/CodeGen/AggressiveAntiDepBreaker.cpp 129 TII(MF.getSubtarget().getInstrInfo()),
130 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
lib/CodeGen/Analysis.cpp 738 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 766 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
798 << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
812 << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo());
883 const TargetFrameLowering *TFI = AP.MF->getSubtarget().getFrameLowering();
897 OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo());
1155 MF->getSubtarget().getInstrInfo()->getNoop(Noop);
1826 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
1871 Value = MF->getSubtarget().getTargetLowering()->LowerCustomJumpTableEntry(
1911 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
3128 if (MF->getSubtarget().getTargetTriple().isOSBinFormatELF()) {
3145 } else if (MF->getSubtarget().getTargetTriple().isOSBinFormatMachO()) {
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 532 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/AsmPrinter/CodeViewDebug.cpp 1145 const TargetSubtargetInfo &TSI = MF.getSubtarget();
1211 const TargetRegisterInfo *TRI = Asm->MF->getSubtarget().getRegisterInfo();
1329 const TargetSubtargetInfo &TSI = MF->getSubtarget();
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 235 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp 207 calculateDbgEntityHistory(MF, Asm->MF->getSubtarget().getRegisterInfo(),
lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp 399 const TargetRegisterInfo *RI = Asm->MF->getSubtarget().getRegisterInfo();
642 const TargetFrameLowering *TFI = Asm->MF->getSubtarget().getFrameLowering();
670 *Asm->MF->getSubtarget().getRegisterInfo(), Cursor, FrameReg);
1181 const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo();
1211 const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 551 const auto &TRI = MF->getSubtarget().getRegisterInfo();
552 const auto &TII = MF->getSubtarget().getInstrInfo();
553 const auto &TLI = MF->getSubtarget().getTargetLowering();
703 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
763 : StringRef(MF.getSubtarget()
2207 const TargetRegisterInfo &TRI = *AP.MF->getSubtarget().getRegisterInfo();
lib/CodeGen/AsmPrinter/WinException.cpp 338 const TargetFrameLowering &TFI = *Asm->MF->getSubtarget().getFrameLowering();
345 Asm->MF->getSubtarget()
816 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
952 const TargetFrameLowering *TFI = Asm->MF->getSubtarget().getFrameLowering();
1015 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1025 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
lib/CodeGen/BranchFolding.cpp 134 MF, MF.getSubtarget().getInstrInfo(), MF.getSubtarget().getRegisterInfo(),
134 MF, MF.getSubtarget().getInstrInfo(), MF.getSubtarget().getRegisterInfo(),
lib/CodeGen/BranchRelaxation.cpp 546 const TargetSubtargetInfo &ST = MF->getSubtarget();
lib/CodeGen/BreakFalseDeps.cpp 267 TII = MF->getSubtarget().getInstrInfo();
268 TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/CFIInstrInserter.cpp 130 MF.getSubtarget().getFrameLowering()->getInitialCFAOffset(MF);
134 MF.getSubtarget().getFrameLowering()->getInitialCFARegister(MF);
247 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/CalcSpillWeights.cpp 154 const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo();
298 if (isRematerializable(li, LIS, VRM, *MF.getSubtarget().getInstrInfo()))
lib/CodeGen/CallingConvLower.cpp 32 TRI(*MF.getSubtarget().getRegisterInfo()), Locs(locs), Context(C) {
54 MF.getSubtarget().getTargetLowering()->HandleByVal(this, Size,
250 const TargetLowering *TL = MF.getSubtarget().getTargetLowering();
lib/CodeGen/CriticalAntiDepBreaker.cpp 47 TII(MF.getSubtarget().getInstrInfo()),
48 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
lib/CodeGen/DFAPacketizer.cpp 196 : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
197 ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
lib/CodeGen/DeadMachineInstructionElim.cpp 103 TRI = MF.getSubtarget().getRegisterInfo();
104 TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/EarlyIfConversion.cpp 168 TII = MF.getSubtarget().getInstrInfo();
169 TRI = MF.getSubtarget().getRegisterInfo();
905 const TargetSubtargetInfo &STI = MF.getSubtarget();
1039 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/CodeGen/ExecutionDomainFix.cpp 417 TII = MF->getSubtarget().getInstrInfo();
418 TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/ExpandPostRAPseudos.cpp 185 TRI = MF.getSubtarget().getRegisterInfo();
186 TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/FEntryInserter.cpp 43 auto *TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/FinalizeISel.cpp 49 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
lib/CodeGen/GCRootLowering.cpp 290 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
314 TII = MF.getSubtarget().getInstrInfo();
319 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/CombinerHelper.cpp 558 const auto &TLI = *MF.getSubtarget().getTargetLowering();
625 const auto &TLI = *MF.getSubtarget().getTargetLowering();
923 const auto &TLI = *MF.getSubtarget().getTargetLowering();
1037 const auto &TLI = *MF.getSubtarget().getTargetLowering();
1080 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1145 const auto &TLI = *MF.getSubtarget().getTargetLowering();
1187 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 33 : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),
lib/CodeGen/GlobalISel/IRTranslator.cpp 1167 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1172 auto &TLI = *MF->getSubtarget().getTargetLowering();
1360 auto &TLI = *MF->getSubtarget().getTargetLowering();
1409 const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1469 Register StackPtr = MF->getSubtarget()
1483 Register StackPtr = MF->getSubtarget()
1577 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1652 const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1736 auto &TLI = *MF->getSubtarget().getTargetLowering();
1823 MF->getSubtarget().getFrameLowering()->getStackAlignment();
1897 const auto &TLI = *MF->getSubtarget().getTargetLowering();
2237 CLI = MF->getSubtarget().getCallLowering();
2245 const auto &TLI = *MF->getSubtarget().getTargetLowering();
lib/CodeGen/GlobalISel/InstructionSelect.cpp 76 InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
185 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
225 auto &TLI = *MF.getSubtarget().getTargetLowering();
251 MF.getSubtarget()
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 70 LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
351 auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
363 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
412 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
1887 auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3677 auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
4168 const auto &TLI = *MF.getSubtarget().getTargetLowering();
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 738 if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) {
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 30 State.TII = MF.getSubtarget().getInstrInfo();
433 const auto *TLI = getMF().getSubtarget().getTargetLowering();
lib/CodeGen/GlobalISel/RegBankSelect.cpp 82 RBI = MF.getSubtarget().getRegBankInfo();
85 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 166 const TargetSubtargetInfo &STI = MF.getSubtarget();
600 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
620 Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
781 ? getMI().getMF()->getSubtarget().getRegisterInfo()
lib/CodeGen/IfConversion.cpp 441 const TargetSubtargetInfo &ST = MF.getSubtarget();
602 MF, TII, MF.getSubtarget().getRegisterInfo(),
1475 const TargetRegisterInfo *TRI = MI.getMF()->getSubtarget().getRegisterInfo();
lib/CodeGen/ImplicitNullChecks.cpp 297 TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/InlineSpiller.cpp 146 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
147 TRI(*mf.getSubtarget().getRegisterInfo()),
202 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
203 TRI(*mf.getSubtarget().getRegisterInfo()),
lib/CodeGen/LiveDebugValues.cpp 808 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
1297 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
1432 TRI = MF.getSubtarget().getRegisterInfo();
1433 TII = MF.getSubtarget().getInstrInfo();
1434 TFI = MF.getSubtarget().getFrameLowering();
lib/CodeGen/LiveDebugVariables.cpp 960 TRI = mf.getSubtarget().getRegisterInfo();
1393 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/LiveIntervals.cpp 128 TRI = MF->getSubtarget().getRegisterInfo();
129 TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/LiveRangeEdit.cpp 470 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/LiveRegMatrix.cpp 55 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/LiveStacks.cpp 50 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/LiveVariables.cpp 623 TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/LocalStackSlotAllocation.cpp 114 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
193 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
290 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
291 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
lib/CodeGen/MIRParser/MIParser.cpp 970 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1114 const auto *TRI = MF.getSubtarget().getRegisterInfo();
1244 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
2023 const auto *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MIRParser/MIRParser.cpp 390 Target->setTarget(MF.getSubtarget());
392 Target.reset(new PerTargetMIParsingState(MF.getSubtarget()));
487 MF.getSubtarget().mirFileLoaded(MF);
630 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/CodeGen/MIRPrinter.cpp 213 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
361 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
470 const auto *TRI = MF.getSubtarget().getRegisterInfo();
543 const auto *TRI = MF.getSubtarget().getRegisterInfo();
708 const auto &SubTarget = MF->getSubtarget();
lib/CodeGen/MachineBasicBlock.cpp 171 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
186 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
338 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
340 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
503 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
533 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
840 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
969 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
991 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1121 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/MachineBlockPlacement.cpp 2988 TII = MF.getSubtarget().getInstrInfo();
2989 TLI = MF.getSubtarget().getTargetLowering();
3043 if (BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(),
lib/CodeGen/MachineCSE.cpp 885 TII = MF.getSubtarget().getInstrInfo();
886 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MachineCombiner.cpp 633 STI = &MF.getSubtarget();
lib/CodeGen/MachineCopyPropagation.cpp 646 TRI = MF.getSubtarget().getRegisterInfo();
647 TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/MachineFrameInfo.cpp 115 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
137 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
138 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
190 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
217 const TargetFrameLowering *FI = MF.getSubtarget().getFrameLowering();
lib/CodeGen/MachineFunction.cpp 204 std::make_unique<PseudoSourceValueManager>(*(getSubtarget().
465 unsigned NumRegs = getSubtarget().getRegisterInfo()->getNumRegs();
497 const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo();
lib/CodeGen/MachineInstr.cpp 95 TRI = MF->getSubtarget().getRegisterInfo();
98 TII = MF->getSubtarget().getInstrInfo();
1194 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1463 TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/MachineInstrBundle.cpp 131 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
132 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MachineLICM.cpp 309 const TargetSubtargetInfo &ST = MF.getSubtarget();
lib/CodeGen/MachineOperand.cpp 316 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
398 TRI = MF->getSubtarget().getRegisterInfo();
404 const auto *TII = MF.getSubtarget().getInstrInfo();
542 const auto *TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/MachineOutliner.cpp 1070 CandidatesForRepeatedSeq[0].getMF()->getSubtarget().getInstrInfo();
1132 const TargetSubtargetInfo &STI = MF.getSubtarget();
1225 const TargetSubtargetInfo &STI = MF->getSubtarget();
1317 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/MachinePipeliner.cpp 207 if (!mf.getSubtarget().enableMachinePipeliner())
212 if (mf.getSubtarget().useDFAforSMS() &&
213 (!mf.getSubtarget().getInstrItineraryData() ||
214 mf.getSubtarget().getInstrItineraryData()->isEmpty()))
220 TII = MF->getSubtarget().getInstrInfo();
1019 Resources.push_back(new ResourceManager(&MF.getSubtarget()));
1023 FuncUnitSorter FUS = FuncUnitSorter(MF.getSubtarget());
1068 ResourceManager *NewResource = new ResourceManager(&MF.getSubtarget());
1546 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2057 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2238 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MachineRegisterInfo.cpp 45 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
123 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/MachineSSAUpdater.cpp 45 : InsertedPHIs(NewPHI), TII(MF.getSubtarget().getInstrInfo()),
lib/CodeGen/MachineScheduler.cpp 367 } else if (!mf.getSubtarget().enableMachineScheduler())
405 } else if (!mf.getSubtarget().enablePostRAScheduler()) {
471 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1488 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2732 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2737 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2749 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
2769 MF.getSubtarget().overrideSchedPolicy(RegionPolicy, NumRegionInstrs);
3338 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
lib/CodeGen/MachineSink.cpp 306 TII = MF.getSubtarget().getInstrInfo();
307 TRI = MF.getSubtarget().getRegisterInfo();
766 const TargetInstrInfo &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1167 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1341 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1342 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/MachineTraceMetrics.cpp 67 const TargetSubtargetInfo &ST = MF->getSubtarget();
lib/CodeGen/MachineVerifier.cpp 365 TII = MF.getSubtarget().getInstrInfo();
366 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MacroFusion.cpp 148 const TargetSubtargetInfo &ST = DAG.MF.getSubtarget();
lib/CodeGen/ModuloSchedule.cpp 787 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
912 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1283 TII(BB->getParent()->getSubtarget().getInstrInfo()), LIS(LIS) {
lib/CodeGen/OptimizePHIs.cpp 78 TII = Fn.getSubtarget().getInstrInfo();
lib/CodeGen/PHIElimination.cpp 263 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/PatchableFunction.cpp 71 auto *TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/PeepholeOptimizer.cpp 1603 TII = MF.getSubtarget().getInstrInfo();
1604 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/PostRAHazardRecognizer.cpp 69 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
lib/CodeGen/PostRASchedulerList.cpp 213 MF.getSubtarget().getInstrItineraryData();
215 MF.getSubtarget().getInstrInfo()->CreateTargetPostRAHazardRecognizer(
217 MF.getSubtarget().getPostRAMutations(Mutations);
285 TII = Fn.getSubtarget().getInstrInfo();
298 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(),
lib/CodeGen/ProcessImplicitDefs.cpp 139 TII = MF.getSubtarget().getInstrInfo();
140 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/PrologEpilogInserter.cpp 217 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
218 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
298 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
299 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
387 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
397 const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering();
536 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
537 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
538 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
563 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
564 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
565 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
599 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
784 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
883 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1093 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
1132 const auto &ST = MF.getSubtarget();
1176 assert(MF.getSubtarget().getRegisterInfo() &&
1178 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1179 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
1180 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/CodeGen/ReachingDefAnalysis.cpp 138 TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/RegAllocFast.cpp 1296 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/CodeGen/RegAllocGreedy.cpp 3163 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
3215 TRI = MF->getSubtarget().getRegisterInfo();
3216 TII = MF->getSubtarget().getInstrInfo();
3220 MF->getSubtarget().enableRALocalReassignment(
3224 MF->getSubtarget().enableAdvancedRASplitCost();
lib/CodeGen/RegAllocPBQP.cpp 401 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
441 CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
584 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
685 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
709 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
825 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
lib/CodeGen/RegUsageInfoCollector.cpp 103 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
175 MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) {
197 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
198 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/RegisterClassInfo.cpp 48 if (MF->getSubtarget().getRegisterInfo() != TRI) {
49 TRI = MF->getSubtarget().getRegisterInfo();
93 auto &STI = MF->getSubtarget();
lib/CodeGen/RegisterCoalescer.cpp 3679 const TargetSubtargetInfo &STI = fn.getSubtarget();
lib/CodeGen/RegisterPressure.cpp 272 TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/RegisterScavenging.cpp 58 TII = MF.getSubtarget().getInstrInfo();
59 TRI = MF.getSubtarget().getRegisterInfo();
794 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/CodeGen/RenameIndependentSubregs.cpp 386 TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/ScheduleDAG.cpp 54 : TM(mf.getTarget()), TII(mf.getSubtarget().getInstrInfo()),
55 TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
lib/CodeGen/ScheduleDAGInstrs.cpp 119 const TargetSubtargetInfo &ST = mf.getSubtarget();
234 const TargetSubtargetInfo &ST = MF.getSubtarget();
426 const TargetSubtargetInfo &ST = MF.getSubtarget();
726 const TargetSubtargetInfo &ST = MF.getSubtarget();
lib/CodeGen/SelectionDAG/FastISel.cpp 1927 TII(*MF->getSubtarget().getInstrInfo()),
1928 TLI(*MF->getSubtarget().getTargetLowering()),
1929 TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 85 TLI = MF->getSubtarget().getTargetLowering();
87 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
184 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
285 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
352 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
363 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 1162 TII(MF->getSubtarget().getInstrInfo()),
1163 TRI(MF->getSubtarget().getRegisterInfo()),
1164 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 44 : Picker(this), InstrItins(IS->MF->getSubtarget().getInstrItineraryData()) {
45 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 195 const TargetSubtargetInfo &STI = mf.getSubtarget();
3134 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3148 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3162 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3178 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
437 const TargetSubtargetInfo &ST = MF.getSubtarget();
lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp 73 const TargetSubtargetInfo &STI = mf.getSubtarget();
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 5817 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 7889 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 253 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
435 TII = MF->getSubtarget().getInstrInfo();
436 TLI = MF->getSubtarget().getTargetLowering();
543 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
lib/CodeGen/ShrinkWrap.cpp 168 MachineFunc->getSubtarget().getFrameLowering();
197 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
483 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
541 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
592 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/CodeGen/SplitKit.cpp 154 TII(*MF.getSubtarget().getInstrInfo()), IPA(lis, MF.getNumBlockIDs()) {}
371 TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
372 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
lib/CodeGen/StackMapLivenessAnalysis.cpp 110 TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/StackMaps.cpp 105 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
176 AP.MF ? AP.MF->getSubtarget().getRegisterInfo() : nullptr;
258 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
351 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
lib/CodeGen/StackSlotColoring.cpp 492 TII = MF.getSubtarget().getInstrInfo();
lib/CodeGen/SwiftErrorValueTracking.cpp 82 TLI = MF->getSubtarget().getTargetLowering();
83 TII = MF->getSubtarget().getInstrInfo();
224 const auto *TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/TailDuplicator.cpp 82 TII = MF->getSubtarget().getInstrInfo();
83 TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/TargetFrameLoweringImpl.cpp 47 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
65 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
79 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/TargetInstrInfo.cpp 382 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
549 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
779 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
780 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
964 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
998 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
999 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/TargetOptionsImpl.cpp 26 if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
lib/CodeGen/TargetRegisterInfo.cpp 449 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/CodeGen/TargetSchedule.cpp 305 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/TwoAddressInstructionPass.cpp 1670 TII = MF->getSubtarget().getInstrInfo();
1671 TRI = MF->getSubtarget().getRegisterInfo();
1672 InstrItins = MF->getSubtarget().getInstrItineraryData();
lib/CodeGen/UnreachableBlockElim.cpp 194 const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo();
lib/CodeGen/VirtRegMap.cpp 64 TII = mf.getSubtarget().getInstrInfo();
65 TRI = mf.getSubtarget().getRegisterInfo();
237 TRI = MF->getSubtarget().getRegisterInfo();
238 TII = MF->getSubtarget().getInstrInfo();
lib/CodeGen/XRayInstrumentation.cpp 193 auto *TII = MF.getSubtarget().getInstrInfo();
197 if (!MF.getSubtarget().isXRaySupported()) {
lib/Target/AArch64/AArch64A53Fix835769.cpp 120 TII = F.getSubtarget().getInstrInfo();
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 399 TII = mf.getSubtarget().getInstrInfo();
lib/Target/AArch64/AArch64AsmPrinter.cpp 123 STI = static_cast<const AArch64Subtarget*>(&MF.getSubtarget());
731 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
lib/Target/AArch64/AArch64BranchTargets.cpp 110 MBB.getParent()->getSubtarget().getInstrInfo());
lib/Target/AArch64/AArch64CallLowering.cpp 912 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
913 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
998 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
999 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
lib/Target/AArch64/AArch64CallingConvention.cpp 85 State.getMachineFunction().getSubtarget());
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 100 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
118 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/Target/AArch64/AArch64CondBrTuning.cpp 299 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
300 TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 334 TII = MF.getSubtarget().getInstrInfo();
lib/Target/AArch64/AArch64ConditionalCompares.cpp 194 TII = MF.getSubtarget().getInstrInfo();
195 TRI = MF.getSubtarget().getRegisterInfo();
934 TII = MF.getSubtarget().getInstrInfo();
935 TRI = MF.getSubtarget().getRegisterInfo();
936 SchedModel = MF.getSubtarget().getSchedModel();
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 191 TRI = MF.getSubtarget().getRegisterInfo();
192 TII = MF.getSubtarget().getInstrInfo();
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 505 auto TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
726 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 815 auto &ST = static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
lib/Target/AArch64/AArch64FastISel.cpp 296 &static_cast<const AArch64Subtarget &>(FuncInfo.MF->getSubtarget());
lib/Target/AArch64/AArch64FrameLowering.cpp 235 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
277 static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
348 const TargetSubtargetInfo &STI = MF.getSubtarget();
1604 MF.getSubtarget().getRegisterInfo());
1627 MF.getSubtarget().getRegisterInfo());
1950 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
2077 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
2183 MF.getSubtarget().getRegisterInfo());
2229 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2290 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2359 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
lib/Target/AArch64/AArch64InstrInfo.cpp 1052 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1053 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1481 MBB.getParent()->getSubtarget().getInstrInfo();
3236 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4106 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
5023 MF->getSubtarget().getRegisterInfo());
5350 MF->getSubtarget().getRegisterInfo());
5581 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 1818 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 330 TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 474 TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 271 const TargetSubtargetInfo &STI = MF.getSubtarget();
524 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 695 TII = MF.getSubtarget().getInstrInfo();
697 const TargetSubtargetInfo &ST = MF.getSubtarget();
lib/Target/AArch64/AArch64SpeculationHardening.cpp 658 TII = MF.getSubtarget().getInstrInfo();
659 TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 178 TII = static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo());
180 MF->getSubtarget().getRegisterInfo());
lib/Target/AArch64/AArch64StorePairSuppress.cpp 125 const TargetSubtargetInfo &ST = MF.getSubtarget();
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 234 const MCSubtargetInfo &STI = MF->getSubtarget();
1298 *MF->getSubtarget().getRegisterInfo());
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp 1011 *MF.getSubtarget().getRegisterInfo());
lib/Target/AMDGPU/SIInstrInfo.cpp 6040 &MF->getSubtarget());
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 91 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
92 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
93 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
123 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
124 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
125 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/ARC/ARCFrameLowering.cpp 437 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
494 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/Target/ARC/ARCRegisterInfo.cpp 65 MBB.getParent()->getSubtarget().getRegisterInfo();
lib/Target/ARM/ARMAsmPrinter.cpp 211 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
279 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
311 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
372 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
380 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
406 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
421 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1072 MF.getSubtarget().getRegisterInfo();
lib/Target/ARM/ARMBaseRegisterInfo.cpp 463 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
644 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
660 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
756 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/ARM/ARMBasicBlockInfo.h 120 static_cast<const ARMBaseInstrInfo*>(MF.getSubtarget().getInstrInfo());
lib/Target/ARM/ARMConstantIslandPass.cpp 355 STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
890 LivePhysRegs LRs(*MF->getSubtarget().getRegisterInfo());
lib/Target/ARM/ARMExpandPseudoInsts.cpp 1170 MBB.getParent()->getSubtarget().getInstrInfo());
1344 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1971 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
lib/Target/ARM/ARMFastISel.cpp 127 &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
lib/Target/ARM/ARMFrameLowering.cpp 105 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
287 static_cast<const ARMSubtarget &>(MF.getSubtarget());
774 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
776 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
893 MF.getSubtarget().getRegisterInfo());
979 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1056 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1170 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1343 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1510 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1511 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1600 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1604 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1609 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1649 MF.getSubtarget().getRegisterInfo());
1651 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1655 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2149 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2264 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/ARM/ARMHazardRecognizer.cpp 48 MF->getSubtarget().getInstrInfo());
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 2001 STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
2088 STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
lib/Target/ARM/ARMLowOverheadLoops.cpp 90 const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(mf.getSubtarget());
195 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/Target/ARM/MLxExpansionPass.cpp 374 TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
375 TRI = Fn.getSubtarget().getRegisterInfo();
lib/Target/ARM/MVEVPTBlockPass.cpp 257 static_cast<const ARMSubtarget &>(Fn.getSubtarget());
lib/Target/ARM/Thumb1FrameLowering.cpp 819 MF.getSubtarget().getRegisterInfo());
942 MF.getSubtarget().getRegisterInfo());
lib/Target/ARM/Thumb2ITBlockPass.cpp 287 static_cast<const ARMSubtarget &>(Fn.getSubtarget());
lib/Target/ARM/Thumb2SizeReduction.cpp 1123 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
lib/Target/ARM/ThumbRegisterInfo.cpp 88 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
lib/Target/AVR/AVRISelLowering.cpp 1625 ->getSubtarget()
lib/Target/AVR/AVRRegisterInfo.cpp 85 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
249 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/Target/BPF/BPFISelLowering.cpp 566 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
619 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
lib/Target/BPF/BPFRegisterInfo.cpp 82 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
lib/Target/Hexagon/HexagonAsmPrinter.cpp 130 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/Hexagon/HexagonCFGOptimizer.cpp 83 MI.getParent()->getParent()->getSubtarget().getInstrInfo();
lib/Target/Hexagon/HexagonConstPropagation.cpp 284 : TRI(*Fn.getSubtarget().getRegisterInfo()),
lib/Target/Hexagon/HexagonExpandCondsets.cpp 1254 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
1255 TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 113 static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
170 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1264 auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
lib/Target/Hexagon/HexagonMachineScheduler.cpp 263 const TargetSubtargetInfo &STI = DAG->MF.getSubtarget();
lib/Target/Hexagon/HexagonNewValueJump.cpp 459 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
461 MF.getSubtarget().getRegisterInfo());
lib/Target/Hexagon/HexagonPeephole.cpp 113 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/Hexagon/HexagonSubtarget.cpp 200 auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 438 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
lib/Target/Hexagon/RDFGraph.cpp 753 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
lib/Target/Lanai/LanaiRegisterInfo.cpp 143 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
144 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/Target/MSP430/MSP430BranchSelector.cpp 226 TII = static_cast<const MSP430InstrInfo *>(MF->getSubtarget().getInstrInfo());
lib/Target/MSP430/MSP430FrameLowering.cpp 46 *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
111 *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
191 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
217 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
229 *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/MSP430/MSP430ISelLowering.cpp 1415 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1550 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
lib/Target/MSP430/MSP430InstrInfo.cpp 313 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
lib/Target/MSP430/MSP430RegisterInfo.cpp 133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
lib/Target/Mips/MicroMipsSizeReduction.cpp 777 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 38 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
lib/Target/Mips/Mips16RegisterInfo.cpp 63 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
104 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
138 *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/Mips/MipsAsmPrinter.cpp 331 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
378 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsBranchExpansion.cpp 838 STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
lib/Target/Mips/MipsCallLowering.cpp 62 MIRBuilder.getMF().getSubtarget().getTargetLowering());
140 static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
144 static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
191 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
255 static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
290 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
582 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
626 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
640 static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
lib/Target/Mips/MipsConstantIslandPass.cpp 439 STI = &static_cast<const MipsSubtarget &>(mf.getSubtarget());
lib/Target/Mips/MipsDelaySlotFiller.cpp 336 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
747 RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo());
770 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
795 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
lib/Target/Mips/MipsExpandPseudo.cpp 683 STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
lib/Target/Mips/MipsISelDAGToDAG.cpp 57 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
lib/Target/Mips/MipsISelLowering.cpp 2741 State.getMachineFunction().getSubtarget());
lib/Target/Mips/MipsInstrInfo.cpp 610 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsLegalizerInfo.cpp 250 static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
341 static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
lib/Target/Mips/MipsMachineFunction.cpp 32 auto &STI = static_cast<const MipsSubtarget &>(MF.getSubtarget());
69 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
151 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
169 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
193 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsOptimizePICCall.cpp 138 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
153 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
197 if (static_cast<const MipsSubtarget &>(F.getSubtarget()).inMips16Mode())
lib/Target/Mips/MipsRegisterBankInfo.cpp 341 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
343 *CopyInst->getMF()->getSubtarget().getRegBankInfo();
372 assert(static_cast<const MipsSubtarget &>(MF.getSubtarget()).hasMSA() &&
667 const LegalizerInfo &LegInfo = *MF->getSubtarget().getLegalizerInfo();
lib/Target/Mips/MipsRegisterInfo.cpp 75 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
lib/Target/Mips/MipsSEFrameLowering.cpp 100 Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())),
856 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
865 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
lib/Target/Mips/MipsSERegisterInfo.cpp 157 static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
228 MBB.getParent()->getSubtarget().getInstrInfo());
244 MBB.getParent()->getSubtarget().getInstrInfo());
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 1630 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/NVPTX/NVPTXFrameLowering.cpp 56 MF.getSubtarget().getInstrInfo()->get(CvtaLocalOpcode),
60 BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 44 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
lib/Target/NVPTX/NVPTXPeephole.cpp 108 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp 51 const TargetSubtargetInfo &STI = MF.getSubtarget();
131 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
132 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
lib/Target/PowerPC/PPCBranchCoalescing.cpp 219 TII = MF.getSubtarget().getInstrInfo();
lib/Target/PowerPC/PPCBranchSelector.cpp 117 static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
265 static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
lib/Target/PowerPC/PPCEarlyReturn.cpp 174 TII = MF.getSubtarget().getInstrInfo();
lib/Target/PowerPC/PPCExpandISEL.cpp 149 TII = MF->getSubtarget().getInstrInfo();
lib/Target/PowerPC/PPCFrameLowering.cpp 341 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/Target/PowerPC/PPCISelLowering.cpp 6724 State.getMachineFunction().getSubtarget());
lib/Target/PowerPC/PPCInstrInfo.cpp 4170 TII(MF->getSubtarget().getInstrInfo()) {
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 170 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 62 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 78 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/RISCV/RISCVFrameLowering.cpp 27 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
327 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
415 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/Target/RISCV/RISCVISelLowering.cpp 1127 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
1157 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1158 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
1189 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1190 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
1287 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
lib/Target/Sparc/SparcFrameLowering.cpp 49 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
225 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
252 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/Target/Sparc/SparcRegisterInfo.cpp 123 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
lib/Target/SystemZ/SystemZAsmPrinter.cpp 571 static_cast<const SystemZInstrInfo *>(MF->getSubtarget().getInstrInfo());
lib/Target/SystemZ/SystemZElimCompare.cpp 627 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
lib/Target/SystemZ/SystemZFrameLowering.cpp 70 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
120 MBB.getParent()->getSubtarget().getRegisterInfo();
139 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
233 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
346 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
477 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/SystemZ/SystemZISelLowering.cpp 6572 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/Target/SystemZ/SystemZInstrInfo.cpp 827 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1001 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/SystemZ/SystemZLDCleanup.cpp 69 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
lib/Target/SystemZ/SystemZLongBranch.cpp 458 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
lib/Target/SystemZ/SystemZMachineScheduler.cpp 132 (C->MF->getSubtarget().getInstrInfo())),
134 const TargetSubtargetInfo *ST = &C->MF->getSubtarget();
lib/Target/SystemZ/SystemZPostRewrite.cpp 264 TII = static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/SystemZ/SystemZRegisterInfo.cpp 201 if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
215 if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
260 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 366 MF.getSubtarget().getFrameLowering());
lib/Target/X86/X86CallLowering.cpp 452 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
453 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
lib/Target/X86/X86CallingConv.cpp 98 State.getMachineFunction().getSubtarget())
166 State.getMachineFunction().getSubtarget().getRegisterInfo();
302 bool Is64Bit = static_cast<const X86Subtarget &>(MF.getSubtarget()).is64Bit();
lib/Target/X86/X86CmovConversion.cpp 168 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/Target/X86/X86ExpandPseudo.cpp 398 STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
lib/Target/X86/X86FloatingPoint.cpp 341 TII = MF.getSubtarget().getInstrInfo();
1684 *MBB.getParent()->getSubtarget().getRegisterInfo();
lib/Target/X86/X86ISelLowering.cpp29666 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
lib/Target/X86/X86InsertPrefetch.cpp 188 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
lib/Target/X86/X86InstrInfo.cpp 140 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
4743 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4767 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4786 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4899 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5075 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5472 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5612 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/X86/X86MachineFunctionInfo.cpp 21 MF->getSubtarget().getRegisterInfo());
lib/Target/X86/X86PadShortFunction.cpp 106 TSM.init(&MF.getSubtarget());
lib/Target/X86/X86RegisterBankInfo.cpp 280 const TargetSubtargetInfo &STI = MF.getSubtarget();
lib/Target/XCore/XCoreFrameLowering.cpp 266 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
331 MF.getSubtarget().getTargetLowering());
366 MF.getSubtarget().getTargetLowering());
424 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
457 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
578 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp 49 *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
lib/Target/XCore/XCoreMachineFunctionInfo.cpp 39 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
57 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/XCore/XCoreRegisterInfo.cpp 269 *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
tools/llvm-exegesis/lib/Assembler.cpp 125 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
131 MF.getSubtarget().getCallLowering()->lowerReturn(MIB, nullptr, {});
167 return MF.getSubtarget().getRegisterInfo()->getReservedRegs(MF);
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 40 AInfo Info(MF->getSubtarget());
72 AInfo Info(MF->getSubtarget());
106 AInfo Info(MF->getSubtarget());
140 AInfo Info(MF->getSubtarget());
173 AInfo Info(MF->getSubtarget());
202 AInfo Info(MF->getSubtarget());
229 AInfo Info(MF->getSubtarget());
260 AInfo Info(MF->getSubtarget());
293 AInfo Info(MF->getSubtarget());
335 AInfo Info(MF->getSubtarget());
371 AInfo Info(MF->getSubtarget());
406 AInfo Info(MF->getSubtarget());
440 AInfo Info(MF->getSubtarget());
473 AInfo Info(MF->getSubtarget());
509 AInfo Info(MF->getSubtarget());
548 AInfo Info(MF->getSubtarget());
586 AInfo Info(MF->getSubtarget());
776 AInfo Info(MF->getSubtarget());
822 AInfo Info(MF->getSubtarget());
889 AInfo Info(MF->getSubtarget());
938 AInfo Info(MF->getSubtarget());
1028 AInfo Info(MF->getSubtarget());
1072 AInfo Info(MF->getSubtarget());
1103 AInfo Info(MF->getSubtarget());
1133 AInfo Info(MF->getSubtarget());
1165 AInfo Info(MF->getSubtarget());