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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 5899 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs();
5917 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs();
5935 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
5955 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5973 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
5991 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
6011 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6029 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
6049 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6065 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6081 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6097 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6113 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6129 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6145 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6161 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6176 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6192 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6208 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
6223 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs();
6241 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
6259 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
6277 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
6295 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
6313 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
6331 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc 138 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX64BOps()) {
152 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX64BOps()) {
166 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX64BOps()) {
176 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX64BOps()) {
186 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX128BOps()) {
200 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX128BOps()) {
214 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX128BOps()) {
224 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX128BOps()) {
307 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX64BOps()) {
318 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX64BOps()) {
329 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX128BOps()) {
340 if (State.getMachineFunction().getSubtarget<HexagonSubtarget>().useHVX128BOps()) {
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 4761 const auto & S = MF.getSubtarget<MipsSubtarget>();
4778 const auto & S = MF.getSubtarget<MipsSubtarget>();
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 4273 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
4289 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
4305 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
4321 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
4337 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
4353 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
gen/lib/Target/X86/X86GenRegisterInfo.inc 6251 return MF.getSubtarget<X86Subtarget>().is64Bit();
6267 return MF.getSubtarget<X86Subtarget>().is64Bit();
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 227 return MF->getSubtarget<MCSubtargetInfo>();
lib/CodeGen/MachinePipeliner.cpp 757 const TargetSubtargetInfo &ST = MF.getSubtarget<TargetSubtargetInfo>();
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 313 if (!F.getSubtarget<AArch64Subtarget>().balanceFPOps())
lib/Target/AArch64/AArch64CallLowering.cpp 451 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
485 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
550 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
553 if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv()) {
596 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
817 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
819 if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
974 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
976 if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
lib/Target/AArch64/AArch64CompressJumpTables.cpp 141 const auto &ST = MF->getSubtarget<AArch64Subtarget>();
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 504 if (MF.getSubtarget<AArch64Subtarget>().isTargetILP32()) {
601 else if (MF->getSubtarget<AArch64Subtarget>().useEL3ForTP())
603 else if (MF->getSubtarget<AArch64Subtarget>().useEL2ForTP())
605 else if (MF->getSubtarget<AArch64Subtarget>().useEL1ForTP())
669 MF.getSubtarget<AArch64Subtarget>().getFrameLowering();
lib/Target/AArch64/AArch64FrameLowering.cpp 389 const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
415 const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
428 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
447 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
493 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
834 return MF.getSubtarget<AArch64Subtarget>().isTargetDarwin();
842 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1285 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1325 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1587 const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1629 const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1768 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1890 if (!MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(18))
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 56 Subtarget = &MF.getSubtarget<AArch64Subtarget>();
lib/Target/AArch64/AArch64InstrInfo.cpp 1474 auto &Subtarget = MBB.getParent()->getSubtarget<AArch64Subtarget>();
lib/Target/AArch64/AArch64RegisterInfo.cpp 48 if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows())
62 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
69 if (MF->getSubtarget<AArch64Subtarget>().isTargetDarwin())
91 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
131 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
158 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
206 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))
415 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
440 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
456 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
555 - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved()
lib/Target/AArch64/AArch64SelectionDAGInfo.cpp 26 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
lib/Target/AArch64/AArch64TargetMachine.cpp 362 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
373 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 73 const GCNSubtarget& ST = F.getSubtarget<GCNSubtarget>();
197 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
259 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
393 if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
431 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
486 Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
571 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
618 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
920 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1195 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1222 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 312 auto const &ST = B.getMF().getSubtarget<GCNSubtarget>();
441 const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
568 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp 213 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
881 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 394 Subtarget = &MF.getSubtarget<GCNSubtarget>();
2733 Subtarget = &MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 4522 DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1141 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1233 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 222 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
261 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
355 TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
385 const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 2875 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDGPURegisterInfo.cpp 130 MF.getSubtarget<GCNSubtarget>().getFrameLowering();
lib/Target/AMDGPU/AMDGPUSubtarget.cpp 844 const GCNSubtarget &ST = DAGInstrs->MF.getSubtarget<GCNSubtarget>();
896 return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<GCNSubtarget>());
898 return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<R600Subtarget>());
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp 817 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 154 TII = MF.getSubtarget<R600Subtarget>().getInstrInfo();
lib/Target/AMDGPU/GCNDPPCombine.cpp 555 auto &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 44 ST(MF.getSubtarget<GCNSubtarget>()),
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 110 const auto &ST = MF.getSubtarget<GCNSubtarget>();
134 const auto &ST = MF.getSubtarget<GCNSubtarget>();
318 dbgs(), &MF.getSubtarget<GCNSubtarget>());
420 const auto &ST = MF.getSubtarget<GCNSubtarget>();
435 const auto &ST = MF.getSubtarget<GCNSubtarget>();
452 const auto &ST = MF.getSubtarget<GCNSubtarget>();
489 const auto &ST = MF.getSubtarget<GCNSubtarget>();
543 const auto &ST = MF.getSubtarget<GCNSubtarget>();
577 const auto &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/GCNNSAReassign.cpp 224 ST = &MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 728 ST = &MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/GCNSchedStrategy.cpp 37 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
315 ST(MF.getSubtarget<GCNSubtarget>()),
lib/Target/AMDGPU/R600AsmPrinter.cpp 47 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600ClauseMergePass.cpp 186 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 508 ST = &MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 317 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 83 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600FrameLowering.cpp 26 = MF.getSubtarget<R600Subtarget>().getRegisterInfo();
lib/Target/AMDGPU/R600InstrInfo.cpp 1092 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1224 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600MachineScheduler.cpp 30 const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 337 const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600Packetizer.cpp 326 const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/R600RegisterInfo.cpp 34 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
lib/Target/AMDGPU/SIAddIMGInit.cpp 64 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 589 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIFixVGPRCopies.cpp 49 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIFixupVectorISel.cpp 224 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIFoldOperands.cpp 1447 ST = &MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 308 ST = &MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIFrameLowering.cpp 404 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
592 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
692 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
834 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
945 const SIRegisterInfo *RI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
956 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
994 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1068 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1105 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1150 MF.getSubtarget<GCNSubtarget>().getRegisterInfo()->needsStackRealignment(MF) ||
lib/Target/AMDGPU/SIISelLowering.cpp 919 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
924 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
982 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
1027 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1871 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
3179 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3279 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3601 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3750 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3840 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5320 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
5858 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
6823 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
10677 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
10833 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIInsertSkips.cpp 247 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>();
275 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
346 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>();
430 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1445 ST = &MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIInstrInfo.cpp 820 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
1233 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2938 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3466 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3634 if (isFLAT(MI) && !MF->getSubtarget<GCNSubtarget>().hasFlatInstOffsets()) {
3955 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
4323 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
4406 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
4737 assert(MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration()
6245 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 1833 STM = &MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SILowerControlFlow.cpp 495 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SILowerI1Copies.cpp 428 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
436 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
459 ST = &MF->getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 187 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
231 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 51 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
183 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
255 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
269 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
329 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 860 const GCNSubtarget &STM = MBB.getParent()->getSubtarget<GCNSubtarget>();
1288 CC = SICacheControl::create(MF.getSubtarget<GCNSubtarget>());
lib/Target/AMDGPU/SIModeRegister.cpp 377 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 271 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 297 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1205 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 166 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIShrinkInstructions.cpp 227 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
554 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
lib/Target/AMDGPU/SIWholeQuadMode.cpp 883 ST = &MF.getSubtarget<GCNSubtarget>();
lib/Target/ARC/ARCBranchFinalize.cpp 148 TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo();
lib/Target/ARC/ARCExpandPseudos.cpp 77 const ARCSubtarget *STI = &MF.getSubtarget<ARCSubtarget>();
lib/Target/ARC/ARCFrameLowering.cpp 123 const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo();
244 const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo();
473 const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo();
lib/Target/ARC/ARCOptAddrMode.cpp 490 AST = &MF.getSubtarget<ARCSubtarget>();
lib/Target/ARC/ARCRegisterInfo.cpp 174 const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo();
lib/Target/ARM/A15SDOptimizer.cpp 659 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMAsmPrinter.cpp 109 Subtarget = &MF.getSubtarget<ARMSubtarget>();
1244 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMBaseRegisterInfo.cpp 66 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
124 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
147 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
154 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
164 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
188 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
242 if (MF.getSubtarget<ARMSubtarget>().hasNEON())
266 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
426 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
448 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMCallLowering.cpp 162 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
270 auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
388 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
507 const auto &STI = MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMFastISel.cpp 3077 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
lib/Target/ARM/ARMFrameLowering.cpp 86 return MF.getSubtarget<ARMSubtarget>().useFastISel();
2249 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMISelDAGToDAG.cpp 63 Subtarget = &MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMInstrInfo.cpp 94 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMMachineFunctionInfo.cpp 17 : isThumb(MF.getSubtarget<ARMSubtarget>().isThumb()),
18 hasThumb2(MF.getSubtarget<ARMSubtarget>().hasThumb2()) {}
lib/Target/ARM/ARMRegisterBankInfo.cpp 475 MF.getSubtarget<ARMSubtarget>().hasVFP2Base()) &&
lib/Target/ARM/ARMSelectionDAGInfo.cpp 27 DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
132 DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
lib/Target/ARM/ARMTargetMachine.cpp 342 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
352 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
521 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
533 return MF.getSubtarget<ARMSubtarget>().isThumb2();
lib/Target/ARM/MLxExpansionPass.cpp 377 const ARMSubtarget *STI = &Fn.getSubtarget<ARMSubtarget>();
lib/Target/ARM/Thumb1FrameLowering.cpp 82 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/Thumb1InstrInfo.cpp 44 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
lib/Target/ARM/ThumbRegisterInfo.cpp 45 if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
56 if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
68 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
108 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
130 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
365 assert(MBB.getParent()->getSubtarget<ARMSubtarget>().isThumb1Only() &&
433 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
456 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
568 if (MF.getSubtarget<ARMSubtarget>().isThumb1Only()) {
lib/Target/AVR/AVRAsmPrinter.cpp 108 const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
lib/Target/AVR/AVRExpandPseudoInsts.cpp 113 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
lib/Target/AVR/AVRFrameLowering.cpp 58 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
164 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
246 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
286 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
308 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
364 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
507 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
lib/Target/AVR/AVRISelDAGToDAG.cpp 60 Subtarget = &MF.getSubtarget<AVRSubtarget>();
210 const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
lib/Target/AVR/AVRInstrInfo.cpp 45 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
494 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
lib/Target/AVR/AVRRelaxMemOperations.cpp 63 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
lib/Target/BPF/BPFISelDAGToDAG.cpp 56 Subtarget = &MF.getSubtarget<BPFSubtarget>();
lib/Target/BPF/BPFMIChecking.cpp 61 TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo();
lib/Target/BPF/BPFMIPeephole.cpp 74 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
232 TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo();
343 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
lib/Target/BPF/BPFMISimplifyPatchable.cpp 70 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
lib/Target/Hexagon/HexagonAsmPrinter.cpp 270 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
761 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
lib/Target/Hexagon/HexagonAsmPrinter.h 38 Subtarget = &Fn.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonBitSimplify.cpp 953 : MF(mf), HII(*MF.getSubtarget<HexagonSubtarget>().getInstrInfo()),
2762 auto &HST = MF.getSubtarget<HexagonSubtarget>();
3313 auto &HST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonBitTracker.cpp 117 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonBlockRanges.cpp 220 : MF(mf), HST(mf.getSubtarget<HexagonSubtarget>()),
lib/Target/Hexagon/HexagonBranchRelaxation.cpp 94 auto &HST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonConstExtenders.cpp 495 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1954 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
1955 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
lib/Target/Hexagon/HexagonConstPropagation.cpp 1911 HII(*Fn.getSubtarget<HexagonSubtarget>().getInstrInfo()),
1912 HRI(*Fn.getSubtarget<HexagonSubtarget>().getRegisterInfo()) {
lib/Target/Hexagon/HexagonCopyToCombine.cpp 469 ST = &MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 1051 auto &ST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonFrameLowering.cpp 225 auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
404 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
505 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
563 return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();
574 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
587 auto &HST = MF.getSubtarget<HexagonSubtarget>();
648 auto &HST = MF.getSubtarget<HexagonSubtarget>();
736 auto &HST = MF.getSubtarget<HexagonSubtarget>();
884 auto &HST = MF.getSubtarget<HexagonSubtarget>();
997 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1113 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1219 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1285 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1680 auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1711 auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1730 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1790 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1835 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1864 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1884 auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
1932 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1981 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2010 auto &HST = MF.getSubtarget<HexagonSubtarget>();
2488 auto &HST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonGenInsert.cpp 1513 const auto &ST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonGenMux.cpp 380 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
381 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
lib/Target/Hexagon/HexagonGenPredicate.cpp 499 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
500 TRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
lib/Target/Hexagon/HexagonHardwareLoops.cpp 387 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonISelDAGToDAG.h 42 HST = &MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonISelLowering.cpp 183 if (MF.getSubtarget<HexagonSubtarget>().useHVXOps())
484 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
lib/Target/Hexagon/HexagonInstrInfo.cpp 689 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
lib/Target/Hexagon/HexagonMachineScheduler.cpp 120 auto &QST = MBB->getParent()->getSubtarget<HexagonSubtarget>();
689 auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonNewValueJump.cpp 465 !MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
lib/Target/Hexagon/HexagonOptAddrMode.cpp 782 auto &HST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonPeephole.cpp 114 QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
lib/Target/Hexagon/HexagonRDFOpt.cpp 293 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
294 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
lib/Target/Hexagon/HexagonRegisterInfo.cpp 170 if (MF.getSubtarget<HexagonSubtarget>().hasReservedR19())
190 auto &HST = MF.getSubtarget<HexagonSubtarget>();
244 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
334 return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp 47 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 62 auto &HST = Fn.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonSplitDouble.cpp 1195 auto &ST = MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonStoreWidening.cpp 591 auto &ST = MFn.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonSubtarget.cpp 201 auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
lib/Target/Hexagon/HexagonVExtract.cpp 101 HST = &MF.getSubtarget<HexagonSubtarget>();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 137 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
138 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
205 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1096 if (MF->getSubtarget<HexagonSubtarget>().hasV60OpsOnly() &&
1522 if (Slot1Store && MF.getSubtarget<HexagonSubtarget>().hasV65Ops() &&
lib/Target/Hexagon/HexagonVectorPrint.cpp 132 QST = &Fn.getSubtarget<HexagonSubtarget>();
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 49 const LanaiSubtarget &Subtarget = MF.getSubtarget<LanaiSubtarget>();
lib/Target/Lanai/LanaiMemAluCombiner.cpp 413 TII = MF.getSubtarget<LanaiSubtarget>().getInstrInfo();
lib/Target/Mips/MipsAsmPrinter.cpp 79 Subtarget = &MF.getSubtarget<MipsSubtarget>();
lib/Target/Mips/MipsDelaySlotFiller.cpp 558 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
599 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
702 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
852 MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
lib/Target/Mips/MipsFastISel.cpp 258 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
lib/Target/Mips/MipsRegisterInfo.cpp 49 MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
160 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
282 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
305 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
lib/Target/Mips/MipsSERegisterInfo.cpp 110 ->getSubtarget<MipsSubtarget>();
lib/Target/Mips/MipsTargetMachine.cpp 212 Subtarget = &MF->getSubtarget<MipsSubtarget>();
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 222 const NVPTXSubtarget &STI = MI->getMF()->getSubtarget<NVPTXSubtarget>();
515 const NVPTXSubtarget &STI = MI->getMF()->getSubtarget<NVPTXSubtarget>();
lib/Target/PowerPC/PPCAsmPrinter.cpp 119 Subtarget = &MF.getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCBranchSelector.cpp 108 if (Fn.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
lib/Target/PowerPC/PPCExpandISEL.cpp 154 return !GenerateISEL || !MF.getSubtarget<PPCSubtarget>().hasISEL();
393 LivePhysRegs LPR(*MF->getSubtarget<PPCSubtarget>().getRegisterInfo());
lib/Target/PowerPC/PPCFastISel.cpp 99 PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
2465 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCFrameLowering.cpp 2279 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
2467 return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
2468 MF.getSubtarget<PPCSubtarget>().isPPC64());
lib/Target/PowerPC/PPCHazardRecognizers.cpp 161 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
221 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 152 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCISelLowering.cpp 4799 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCInstrInfo.cpp 128 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
4011 if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
4192 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR,
lib/Target/PowerPC/PPCMCInstLower.cpp 114 const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
lib/Target/PowerPC/PPCMIPeephole.cpp 140 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
220 assert(MF->getSubtarget<PPCSubtarget>().isELFv2ABI() &&
319 !MF->getSubtarget<PPCSubtarget>().isELFv2ABI())
1400 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0())
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 169 const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 154 const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
417 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
570 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
lib/Target/PowerPC/PPCRegisterInfo.cpp 143 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
200 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
225 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
273 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
348 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
395 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
454 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
502 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
621 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
649 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
694 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
737 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
817 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
867 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
893 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
915 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
994 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1145 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1231 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1257 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 51 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
153 TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
lib/Target/PowerPC/PPCTOCRegDeps.cpp 114 MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
lib/Target/PowerPC/PPCTargetMachine.cpp 269 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
281 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCVSXCopy.cpp 144 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 350 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 196 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
222 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 680 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
695 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
lib/Target/RISCV/RISCVFrameLowering.cpp 399 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
400 MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 41 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
lib/Target/RISCV/RISCVISelLowering.cpp 1634 RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
1655 RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
2263 MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(RISCV::X1))
2369 RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
2384 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
2480 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
lib/Target/RISCV/RISCVInstrInfo.cpp 167 bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
lib/Target/RISCV/RISCVRegisterInfo.cpp 44 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
74 if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
91 return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
110 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
154 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
lib/Target/Sparc/DelaySlotFiller.cpp 50 Subtarget = &F.getSubtarget<SparcSubtarget>();
108 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>();
lib/Target/Sparc/LeonPasses.cpp 41 Subtarget = &MF.getSubtarget<SparcSubtarget>();
78 Subtarget = &MF.getSubtarget<SparcSubtarget>();
128 Subtarget = &MF.getSubtarget<SparcSubtarget>();
lib/Target/Sparc/SparcAsmPrinter.cpp 274 if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
lib/Target/Sparc/SparcFrameLowering.cpp 91 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
264 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
lib/Target/Sparc/SparcISelDAGToDAG.cpp 39 Subtarget = &MF.getSubtarget<SparcSubtarget>();
lib/Target/Sparc/SparcRegisterInfo.cpp 56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
lib/Target/SystemZ/SystemZAsmPrinter.cpp 461 if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 354 Subtarget = &MF.getSubtarget<SystemZSubtarget>();
lib/Target/SystemZ/SystemZRegisterInfo.cpp 84 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
197 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
211 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
283 MF.getSubtarget<SystemZSubtarget>().hasVector()) {
lib/Target/SystemZ/SystemZShortenInst.cpp 369 const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
lib/Target/WebAssembly/WebAssemblyAsmPrinter.h 50 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 213 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
376 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
443 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
641 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
726 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
1381 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
1382 if (!MF.getSubtarget<WebAssemblySubtarget>()
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 108 MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 198 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 198 Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 355 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 47 MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
128 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
143 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
163 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
230 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp 56 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
92 if (!MF.getSubtarget<WebAssemblySubtarget>().hasAtomics())
132 if (!MF.getSubtarget<WebAssemblySubtarget>().hasBulkMemory())
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 127 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
145 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
236 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 142 ->getSubtarget<WebAssemblySubtarget>()
186 *MF.getSubtarget<WebAssemblySubtarget>().getTargetLowering();
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 140 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
142 *MF.getSubtarget<WebAssemblySubtarget>().getTargetLowering();
lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp 81 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 776 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
777 const auto *TRI = MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 113 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
147 if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp 70 const auto &TRI = *MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp 26 .getSubtarget<WebAssemblySubtarget>()
50 .getSubtarget<WebAssemblySubtarget>()
lib/Target/X86/X86AsmPrinter.cpp 56 Subtarget = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 674 !MF.getSubtarget<X86Subtarget>().is64Bit())
679 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
680 TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
lib/Target/X86/X86AvoidTrailingCall.cpp 61 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86CallFrameOptimization.cpp 237 STI = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86CallLowering.cpp 103 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
384 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86CondBrFolding.cpp 572 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86DomainReassignment.cpp 730 STI = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86EvexToVex.cpp 95 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
97 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86FastISel.cpp 63 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>();
lib/Target/X86/X86FixupBWInsts.cpp 156 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
lib/Target/X86/X86FixupLEAs.cpp 197 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86FixupSetCC.cpp 98 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
136 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
lib/Target/X86/X86FlagsCopyLowering.cpp 341 Subtarget = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86FrameLowering.cpp 488 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
530 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
878 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
973 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
lib/Target/X86/X86ISelDAGToDAG.cpp 184 Subtarget = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86IndirectBranchTracking.cpp 100 const X86Subtarget &SubTarget = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86InstrInfo.cpp 4007 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
7740 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7901 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7921 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
lib/Target/X86/X86MCInstLower.cpp 98 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
1833 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1974 MF->getSubtarget<X86Subtarget>().getFrameLowering();
lib/Target/X86/X86OptimizeLEAs.cpp 682 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
683 TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
lib/Target/X86/X86PadShortFunction.cpp 103 if (!MF.getSubtarget<X86Subtarget>().padShortFunctions())
lib/Target/X86/X86RegisterInfo.cpp 125 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
181 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
283 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
411 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
596 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
696 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
800 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
809 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86RetpolineThunks.cpp 96 STI = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86SelectionDAGInfo.cpp 52 DAG.getMachineFunction().getSubtarget<X86Subtarget>();
308 DAG.getMachineFunction().getSubtarget<X86Subtarget>();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 408 Subtarget = &MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86VZeroUpper.cpp 281 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
lib/Target/X86/X86WinAllocaExpander.cpp 278 STI = &MF.getSubtarget<X86Subtarget>();
lib/Target/XCore/XCoreFrameLowering.cpp 230 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();
347 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();
489 const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();