|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 872 OutMIs[InsnID].addImm(Imm);
910 OutMIs[NewInsnID].addImm(
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 154 MIB.addImm(Imm);
include/llvm/CodeGen/MachineInstrBuilder.h 288 return addImm(Disp.getImm() + off);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 727 MIB.addImm(IsPre);
lib/CodeGen/GlobalISel/IRTranslator.cpp 1150 ICall.addImm(CI.isTailCall() ? 1 : 0);
1539 .addImm(ExtraInfo);
1639 MIB.addImm(CI->getSExtValue());
1852 .addImm(DL->getABITypeAlignment(U.getType()));
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 151 MIB.addImm(CI->getZExtValue());
178 MIB.addImm(Align);
257 MIB.addImm(NumBits);
531 Extract.addImm(Index);
668 .addImm(Index);
905 .addImm(Ordering)
906 .addImm(Scope);
lib/CodeGen/ImplicitNullChecks.cpp 638 .addImm(FK)
640 .addImm(MI->getOpcode());
lib/CodeGen/MachineInstr.cpp 2023 MIB.addImm(0U);
2042 MIB.addImm(0U);
2092 .addImm(0U)
lib/CodeGen/PatchableFunction.cpp 74 .addImm(2)
75 .addImm(FirstActualI->getOpcode());
lib/CodeGen/SelectionDAG/FastISel.cpp 842 Builder.addImm(0);
853 .addImm(0)
854 .addImm(0);
1311 .addImm(ExtraInfo);
1425 .addImm(CI->getZExtValue())
2130 .addImm(Imm);
2134 .addImm(Imm);
2153 .addImm(Imm1)
2154 .addImm(Imm2);
2158 .addImm(Imm1)
2159 .addImm(Imm2);
2199 .addImm(Imm);
2204 .addImm(Imm);
2218 .addImm(Imm);
2220 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 372 MIB.addImm(C->getSExtValue());
585 MIB.addImm(SD->getZExtValue());
592 MIB.addImm(SubIdx);
736 MIB.addImm(CI->getSExtValue());
741 MIB.addImm(0);
1067 MIB.addImm(ExtraInfo);
1082 MIB.addImm(Flags);
lib/CodeGen/TargetInstrInfo.cpp 520 MIB.addImm(StackMaps::IndirectMemRefOp);
521 MIB.addImm(SpillSize);
523 MIB.addImm(SpillOffset);
lib/CodeGen/TargetLoweringBase.cpp 1058 MIB.addImm(StackMaps::IndirectMemRefOp);
1059 MIB.addImm(MFI.getObjectSize(FI));
1061 MIB.addImm(0);
1065 MIB.addImm(StackMaps::DirectMemRefOp);
1067 MIB.addImm(0);
lib/CodeGen/XRayInstrumentation.cpp 109 .addImm(T.getOpcode());
lib/Target/AArch64/AArch64A53Fix835769.cpp 179 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
183 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
lib/Target/AArch64/AArch64BranchTargets.cpp 128 .addImm(HintNum);
lib/Target/AArch64/AArch64CallLowering.cpp 814 MIB.addImm(0);
897 CallSeqStart.addImm(NumBytes).addImm(0);
897 CallSeqStart.addImm(NumBytes).addImm(0);
902 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
902 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
1023 CallSeqStart.addImm(Handler.StackSize).addImm(0);
1023 CallSeqStart.addImm(Handler.StackSize).addImm(0);
1025 .addImm(Handler.StackSize)
1026 .addImm(CalleePopBytes);
lib/Target/AArch64/AArch64CondBrTuning.cpp 138 .addImm(CC)
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 282 .addImm(Imm)
292 .addImm(Cmp)
lib/Target/AArch64/AArch64ConditionalCompares.cpp 640 .addImm(0)
641 .addImm(0);
698 MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
701 MIB.addImm(NZCV).addImm(HeadCmpBBCC);
701 MIB.addImm(NZCV).addImm(HeadCmpBBCC);
709 .addImm(isNZ ? AArch64CC::NE : AArch64CC::EQ)
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 138 .addImm(I->Op2));
148 .addImm(I->Op1)
149 .addImm(I->Op2));
160 .addImm(I->Op1)
161 .addImm(I->Op2));
202 .addImm(0).addImm(0);
202 .addImm(0).addImm(0);
208 .addImm(ExtendImm);
210 .addImm(AArch64CC::NE)
289 .addImm(0);
293 .addImm(AArch64CC::EQ);
297 .addImm(0);
301 .addImm(AArch64CC::EQ);
367 .addImm(2)
373 .addImm(16 * 2)
374 .addImm(0);
470 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
570 .addImm(48);
578 .addImm(0);
590 .addImm(0);
608 .addImm(SysReg);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 773 .addImm(0);
788 .addImm(0);
lib/Target/AArch64/AArch64FastISel.cpp 372 .addImm(0)
373 .addImm(0);
425 .addImm(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
501 .addImm(0)
503 .addImm(AArch64::sub_32);
517 .addImm(0);
1060 .addImm(0)
1061 .addImm(0);
1135 MIB.addFrameIndex(FI).addImm(Offset);
1150 MIB.addImm(IsSigned);
1151 MIB.addImm(Addr.getShift() != 0);
1153 MIB.addReg(Addr.getReg()).addImm(Offset);
1392 .addImm(Imm)
1393 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1436 .addImm(getShifterImm(ShiftType, ShiftImm));
1481 .addImm(getArithExtendImm(ExtType, ShiftImm));
1914 .addImm(0)
1916 .addImm(AArch64::sub_32);
2413 MIB.addImm(TestBit);
2481 .addImm(ExtraCC)
2487 .addImm(CC)
2518 .addImm(CC)
2543 .addImm(0)
2627 .addImm(CondCodes[0]);
2632 .addImm(CondCodes[1]);
2646 .addImm(invertedCC);
2816 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
3076 .addImm(NumBytes).addImm(0);
3076 .addImm(NumBytes).addImm(0);
3159 .addImm(NumBytes).addImm(0);
3159 .addImm(NumBytes).addImm(0);
3509 .addImm(0)
3510 .addImm(0);
3647 .addImm(1);
3652 .addImm(0xF000);
4023 .addImm(0)
4025 .addImm(AArch64::sub_32);
4176 .addImm(0)
4178 .addImm(AArch64::sub_32);
4297 .addImm(0)
4299 .addImm(AArch64::sub_32);
4406 .addImm(0)
4408 .addImm(AArch64::sub_32);
4465 .addImm(0)
4467 .addImm(AArch64::sub_32);
4562 .addImm(0)
4564 .addImm(AArch64::sub_32);
4606 .addImm(0)
4608 .addImm(AArch64::sub_32);
5136 .addImm(0);
5142 .addImm(AArch64CC::NE);
lib/Target/AArch64/AArch64FrameLowering.cpp 506 .addImm(Reg0)
507 .addImm(Reg1)
508 .addImm(Imm * 8)
520 .addImm(Imm * 8)
524 .addImm(RegInfo->getSEHRegNum(Reg0))
525 .addImm(RegInfo->getSEHRegNum(Reg1))
526 .addImm(Imm * 8)
536 .addImm(Reg)
537 .addImm(Imm)
547 .addImm(Reg)
548 .addImm(Imm)
557 .addImm(Reg0)
558 .addImm(Reg1)
559 .addImm(Imm * 8)
569 .addImm(Imm * 8)
573 .addImm(RegInfo->getSEHRegNum(Reg0))
574 .addImm(RegInfo->getSEHRegNum(Reg1))
575 .addImm(Imm * 8)
583 .addImm(Reg)
584 .addImm(Imm * 8)
592 .addImm(Reg)
593 .addImm(Imm * 8)
708 MIB.addImm(CSStackSizeInc / Scale);
1031 .addImm(LowNumWords)
1032 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1039 .addImm((NumWords & 0xFFFF0000) >> 16) // High half
1040 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 16))
1047 .addImm(NumWords)
1099 .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 4))
1104 .addImm(NumBytes)
1151 .addImm(andMaskEncoded);
1156 .addImm(NumBytes & andMaskEncoded)
1966 .addImm(8)
2059 .addImm(RPI.Offset) // [sp, #offset*scale],
2144 .addImm(RPI.Offset) // [sp, #offset*scale]
2166 .addImm(-8)
2378 BuildMI(MBB, MBBI, DL, TII.get(AArch64::MOVi64imm), DstReg).addImm(-2);
2382 .addImm(0);
lib/Target/AArch64/AArch64ISelLowering.cpp 1358 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
lib/Target/AArch64/AArch64InstrInfo.cpp 376 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
383 MIB.addImm(Cond[3].getImm());
582 .addImm(0)
583 .addImm(0);
588 .addImm(0)
589 .addImm(0);
611 .addImm(
616 .addImm(
671 .addImm(CC);
1497 .addImm(0);
1516 .addImm(0)
1522 .addImm(0)
1529 .addImm(0);
1533 .addImm(16);
1537 .addImm(32);
1541 .addImm(48);
1544 .addImm(0)
2458 MIB.addImm(0);
2484 .addImm(0)
2485 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
2490 .addImm(0)
2491 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2495 .addImm(0)
2496 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2549 .addImm(0)
2550 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2553 .addImm(0)
2554 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2649 .addImm(-16);
2654 .addImm(16);
2765 .addImm(AArch64SysReg::NZCV)
2774 .addImm(AArch64SysReg::NZCV)
2801 .addImm(0)
2907 MI.addImm(0);
2932 .addImm(0)
3037 MI.addImm(0);
3098 .addImm(Sign * (int)ThisVal);
3100 MBI = MBI.addImm(
3115 .addImm(Imm)
3124 .addImm(Imm)
4030 .addImm(MUL->getOperand(3).getImm());
4184 .addImm(Encoding);
4275 .addImm(Encoding);
4837 .addImm(Imm)
4875 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
5547 .addImm(0);
5578 .addImm(-16);
5605 .addImm(16);
5637 .addImm(0));
5668 .addImm(0);
5672 .addImm(0);
5679 .addImm(-16);
5684 .addImm(16);
lib/Target/AArch64/AArch64InstructionSelector.cpp 727 .addImm(0)
729 .addImm(AArch64::hsub);
978 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
1099 .addImm(0)
1100 .addImm(0);
1107 .addImm(0)
1418 .addImm(/*bit offset=*/0)
1427 .addImm(1);
1431 .addImm(AArch64CC::EQ)
1619 MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
1652 MachineInstrBuilder(MF, I).addImm(Width - 1);
1664 .addImm(0)
1666 .addImm(AArch64::sub_32);
1811 .addImm(0)
1813 .addImm(AArch64::sub_32);
1924 .addImm(getInvertedCondCode(AArch64CC::HS));
2049 .addImm(0)
2051 .addImm(AArch64::sub_32);
2105 .addImm(0)
2107 .addImm(AArch64::sub_32);
2111 .addImm(0)
2112 .addImm(SrcSize - 1);
2116 .addImm(0)
2117 .addImm(SrcSize - 1);
2176 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
2182 .addImm(AArch64CC::NE);
2248 .addImm(getInvertedCondCode(CC1));
2257 .addImm(getInvertedCondCode(CC2));
2384 .addImm(0);
2691 .addImm(SubregIndex);
2754 .addImm(0)
2756 .addImm(AArch64::sub_32);
2762 .addImm(0)
2764 .addImm(AArch64::sub_32);
2770 .addImm(32)
2771 .addImm(31);
2856 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx);
3003 .addImm(AArch64::dsub);
3029 .addImm(LaneIdx);
3214 TstMI.addImm(
3324 .addImm(1) /* Lane index */
3326 .addImm(0);
3373 .addImm(InvCC);
3469 .addImm(CondCode);
3633 Dup.addImm(0);
3729 .addImm(AArch64::qsub0)
3731 .addImm(AArch64::qsub1);
3760 .addImm(LaneIdx)
3762 .addImm(0);
3765 .addImm(LaneIdx)
3949 MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(1);
3954 MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000);
4041 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
4050 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
4059 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
4068 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
4090 [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed); },
4091 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShVal); },
4267 MIB.addImm(0);
4268 MIB.addImm(1);
4306 MIB.addImm(0);
4307 MIB.addImm(0);
4373 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); },
4398 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
4414 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC >> Scale); },
4419 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC >> Scale); },
4432 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
4492 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}};
4631 MIB.addImm(getArithExtendImm(Ext, ShiftVal));
4641 MIB.addImm(CstVal.getValue());
4649 MIB.addImm(Enc);
4657 MIB.addImm(Enc);
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 767 .addImm(OffsetImm)
884 .addImm(OffsetImm)
924 .addImm(0)
925 .addImm(31);
982 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1022 .addImm(AndMaskEncoded)
1030 .addImm(Immr)
1031 .addImm(Imms)
1403 .addImm(Value / Scale)
1413 .addImm(Value / Scale)
lib/Target/AArch64/AArch64RegisterInfo.cpp 423 .addImm(Offset)
424 .addImm(Shifter);
509 .addImm(0);
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 448 .addImm(LaneNumber);
460 .addImm(LaneNumber);
573 .addImm(0);
613 .addImm(0);
618 .addImm(2);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 221 BuildMI(MBB, MBBI, DL, TII->get(AArch64::DSB)).addImm(0xf);
222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf);
235 .addImm(CondCode);
372 .addImm(0)
373 .addImm(0); // no shift
379 .addImm(AArch64CC::EQ);
395 .addImm(0)
396 .addImm(0); // no shift
402 .addImm(0);
407 .addImm(0)
408 .addImm(0); // no shift
581 .addImm(0);
596 BuildMI(MBB, MBBI, DL, TII->get(AArch64::HINT)).addImm(0x14);
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 308 .addImm(0);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 137 .addImm(0)
336 .addImm(0);
370 .addImm(0);
376 .addImm(0);
384 .addImm(AMDGPU::sub0)
386 .addImm(AMDGPU::sub1);
484 MIB.addImm(SubRegs[I]);
607 .addImm(SubReg);
765 .addImm(Tgt)
770 .addImm(VM)
771 .addImm(Compr)
772 .addImm(Enabled);
957 .addImm(Overflow);
962 .addImm(Overflow);
968 .addImm(0);
1019 .addImm(ImmOffset)
1020 .addImm(extractGLC(AuxiliaryData))
1021 .addImm(extractSLC(AuxiliaryData))
1022 .addImm(0) // tfe: FIXME: Remove from inst
1023 .addImm(extractDLC(AuxiliaryData))
1024 .addImm(extractSWZ(AuxiliaryData))
1128 .addImm(0)
1130 .addImm(0)
1253 .addImm(0)
1254 .addImm(Signed ? -1 : 1);
1265 .addImm(0) // src0_modifiers
1266 .addImm(0) // src0
1267 .addImm(0) // src1_modifiers
1268 .addImm(Signed ? -1 : 1) // src1
1285 .addImm(Mask)
1295 .addImm(0) // Offset
1296 .addImm(SrcSize); // Width
1325 .addImm(AMDGPU::sub0)
1327 .addImm(AMDGPU::sub1);
1331 .addImm(SrcSize << 16);
1341 .addImm(Mask);
1345 .addImm(SrcSize << 16);
1388 .addImm(0)
1389 .addImm(getFPTrueImmVal(DstSize, Signed));
1440 .addImm(I.getOperand(1).getImm());
1448 .addImm(Imm.trunc(32).getZExtValue());
1451 .addImm(Imm.ashr(32).getZExtValue());
1455 .addImm(AMDGPU::sub0)
1457 .addImm(AMDGPU::sub1);
1547 .addImm(-1);
1642 .addImm(Mask);
1666 .addImm(AMDGPU::sub0)
1668 .addImm(AMDGPU::sub1);
1817 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
1818 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
1819 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
1831 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
1832 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
1833 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
1841 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
1842 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
1854 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
1863 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src_mods
1864 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // clamp
1873 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods
1894 [=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
1914 [=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
1942 .addImm(GEPInfo.Imm);
1956 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // offset
1957 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // slc
1980 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset.getValue()); },
1981 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // slc
2015 .addImm(Offset & ~4095);
2033 MIB.addImm(Offset & 4095);
2087 MIB.addImm(Offset);
2131 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset
2141 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }
2158 [=](MachineInstrBuilder &MIB) { MIB.addImm(PossibleOffset); }
2173 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }
2183 MIB.addImm(CstVal.getValue());
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1165 .addImm(Encoding);
1623 MIB.addImm(0);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 1311 .addImm(ImmOffset)
1312 .addImm(extractGLC(CachePolicy))
1313 .addImm(extractSLC(CachePolicy))
1314 .addImm(0) // tfe: FIXME: Remove from inst
1315 .addImm(extractDLC(CachePolicy))
lib/Target/AMDGPU/GCNDPPCombine.cpp 197 DPPInst.addImm(Mod0->getImm());
201 DPPInst.addImm(0);
220 DPPInst.addImm(Mod1->getImm());
224 DPPInst.addImm(0);
250 DPPInst.addImm(CombBCZ ? 1 : 0);
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 202 .addImm(0);
1029 .addImm(0);
1070 .addImm(0xfffe);
1131 .addImm(0);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 354 .addImm(0) // ADDR
355 .addImm(AluInstCount - 1); // COUNT
403 .addImm(LiteralPair0)
404 .addImm(LiteralPair1);
446 MILit.addImm(Literals[i]->getImm());
453 MILit.addImm(Literals[i + 1]->getImm());
459 MILit.addImm(0);
473 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount);
485 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount);
555 .addImm(CfCount + 1)
556 .addImm(1);
573 .addImm(1);
589 .addImm(Pair.first + 1);
598 .addImm(0)
599 .addImm(0);
612 .addImm(0)
613 .addImm(0);
627 .addImm(CfCount + 1)
628 .addImm(1);
646 .addImm(0);
654 .addImm(0);
687 .addImm(Alu->getOperand(0).getImm())
688 .addImm(Alu->getOperand(1).getImm())
689 .addImm(Alu->getOperand(2).getImm())
690 .addImm(Alu->getOperand(3).getImm())
691 .addImm(Alu->getOperand(4).getImm())
692 .addImm(Alu->getOperand(5).getImm())
693 .addImm(Alu->getOperand(6).getImm())
694 .addImm(Alu->getOperand(7).getImm())
695 .addImm(Alu->getOperand(8).getImm());
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 297 .addImm(Address++) // ADDR
298 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
299 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
300 .addImm(KCacheBanks.empty()?0:2) // KM0
301 .addImm((KCacheBanks.size() < 2)?0:2) // KM1
302 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
303 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
304 .addImm(AluInstCount) // COUNT
305 .addImm(1); // Enabled
lib/Target/AMDGPU/R600ISelLowering.cpp 382 .addImm(isEOP(I)); // Set End of program bit
390 .addImm(isEOP(I)); // Set End of program bit
403 .addImm(R600::PRED_SETNE)
404 .addImm(0); // Flags
417 .addImm(R600::PRED_SETNE_INT)
418 .addImm(0); // Flags
456 .addImm(CfInst)
457 .addImm(EOP);
lib/Target/AMDGPU/R600InstrInfo.cpp 1247 MIB.addImm(0) // $update_exec_mask
1248 .addImm(0); // $update_predicate
1250 MIB.addImm(1) // $write
1251 .addImm(0) // $omod
1252 .addImm(0) // $dst_rel
1253 .addImm(0) // $dst_clamp
1255 .addImm(0) // $src0_neg
1256 .addImm(0) // $src0_rel
1257 .addImm(0) // $src0_abs
1258 .addImm(-1); // $src0_sel
1262 .addImm(0) // $src1_neg
1263 .addImm(0) // $src1_rel
1264 .addImm(0) // $src1_abs
1265 .addImm(-1); // $src1_sel
1270 MIB.addImm(1) // $last
1272 .addImm(0) // $literal
1273 .addImm(0); // $bank_swizzle
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 219 .addImm(Chan);
lib/Target/AMDGPU/SIAddIMGInit.cpp 145 .addImm(0);
156 .addImm(0);
161 .addImm(CurrIdx);
lib/Target/AMDGPU/SIFoldOperands.cpp 709 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addImm(Imm);
755 B.addImm(Defs[I].second);
lib/Target/AMDGPU/SIFrameLowering.cpp 110 .addImm(Offset)
111 .addImm(0) // glc
112 .addImm(0) // slc
113 .addImm(0) // tfe
114 .addImm(0) // dlc
115 .addImm(0) // swz
124 .addImm(Offset);
131 .addImm(0)
132 .addImm(0) // glc
133 .addImm(0) // slc
134 .addImm(0) // tfe
135 .addImm(0) // dlc
136 .addImm(0) // swz
157 .addImm(Offset)
158 .addImm(0) // glc
159 .addImm(0) // slc
160 .addImm(0) // tfe
161 .addImm(0) // dlc
162 .addImm(0) // swz
171 .addImm(Offset);
178 .addImm(0)
179 .addImm(0) // glc
180 .addImm(0) // slc
181 .addImm(0) // tfe
182 .addImm(0) // dlc
183 .addImm(0) // swz
229 .addImm(0);
232 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_LO |
236 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_HI |
246 .addImm(0);
266 .addImm(8);
527 .addImm(StackSize * ST.getWavefrontSize());
554 .addImm(MFI->getGITPtrHigh())
596 .addImm(EncodedOffset) // offset
597 .addImm(0) // glc
598 .addImm(0) // dlc
637 .addImm(0) // offset
638 .addImm(0) // glc
639 .addImm(0) // dlc
661 .addImm(Rsrc23 & 0xffffffff)
665 .addImm(Rsrc23 >> 32)
739 .addImm(-1);
771 .addImm(Spill[0].Lane)
795 .addImm((Alignment - 1) * ST.getWavefrontSize())
799 .addImm(-Alignment * ST.getWavefrontSize())
815 .addImm(RoundedSize * ST.getWavefrontSize())
850 .addImm(RoundedSize * ST.getWavefrontSize())
872 .addImm(Spill[0].Lane);
898 .addImm(-1);
1123 .addImm(Amount * ST.getWavefrontSize());
lib/Target/AMDGPU/SIISelLowering.cpp 3108 .addImm(0);
3138 .addImm(0)
3139 .addImm(EncodedReg);
3147 .addImm(EncodedReg);
3152 .addImm(0);
3226 .addImm(Offset);
3233 .addImm(IdxMode);
3243 .addImm(Offset);
3357 .addImm(IdxMode);
3364 .addImm(Offset);
3368 .addImm(IdxMode);
3382 .addImm(Offset);
3513 .addImm(SubReg);
3539 .addImm(SubReg - AMDGPU::sub0);
3572 .addImm(SubReg - AMDGPU::sub0);
3639 .addImm(AMDGPU::sub0)
3641 .addImm(AMDGPU::sub1);
3656 .addImm(MI.getOperand(0).getImm());
3664 .addImm(MI.getOperand(0).getImm());
3706 .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
3711 .addImm(0);
3714 .addImm(getSubtarget()->getWavefrontSize());
3718 .addImm(-1);
3729 .addImm(MFI->getLDSSize());
3767 .addImm(0)
3769 .addImm(0)
3773 .addImm(0)
3775 .addImm(0)
3781 .addImm(AMDGPU::sub0)
3783 .addImm(AMDGPU::sub1);
3847 I.addImm(0); // clamp bit for e64 encoding
10802 .addImm(1); // prefetch 2 lines behind PC
10806 .addImm(2); // prefetch 1 line behind PC
lib/Target/AMDGPU/SIInsertSkips.cpp 169 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
174 .addImm(1) // vm
175 .addImm(0) // compr
176 .addImm(0); // en
179 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0);
264 I.addImm(0) // src0 modifiers
266 .addImm(0) // src1 modifiers
269 I.addImm(0); // omod
289 .addImm(0);
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1154 .addImm(Enc);
1170 .addImm(Wait.VsCnt);
1599 .addImm(0);
1601 .addImm(0);
lib/Target/AMDGPU/SIInstrInfo.cpp 545 .addImm(-1)
546 .addImm(0);
558 .addImm(0)
584 .addImm(0)
605 .addImm(0);
762 .addImm(Value);
770 .addImm(Value);
776 .addImm(Value);
781 .addImm(Value);
803 Builder.addImm(IdxValue);
831 .addImm(0)
833 .addImm(0)
843 .addImm(-1)
844 .addImm(0);
846 .addImm(0)
848 .addImm(0)
857 .addImm(0)
858 .addImm(-1);
860 .addImm(0)
862 .addImm(0)
874 .addImm(0)
876 .addImm(0)
888 .addImm(0)
890 .addImm(0)
900 .addImm(0);
903 .addImm(-1)
904 .addImm(0);
906 .addImm(0)
908 .addImm(0)
918 .addImm(0);
921 .addImm(0)
922 .addImm(-1);
924 .addImm(0)
926 .addImm(0)
947 .addImm(Value)
960 .addImm(Value)
1105 .addImm(0) // offset
1223 .addImm(0) // offset
1270 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
1273 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
1292 .addImm(0); // clamp bit
1297 .addImm(-1)
1298 .addImm(0);
1302 .addImm(-1)
1308 .addImm(2)
1316 .addImm(LDSOffset)
1318 .addImm(0); // clamp bit
1335 .addImm(Arg);
1354 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1429 .addImm(Imm.getLoBits(32).getZExtValue())
1432 .addImm(Imm.getHiBits(32).getZExtValue())
1592 MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
1604 MovDPP.addImm(MI.getOperand(I).getImm());
1613 .addImm(AMDGPU::sub0)
1615 .addImm(AMDGPU::sub1);
1799 .addImm(0);
1809 .addImm(0);
2248 .addImm(SubIdx);
2667 .addImm(Imm);
2677 .addImm(Imm)
2687 .addImm(Imm)
2699 .addImm(Src0Mods ? Src0Mods->getImm() : 0)
2701 .addImm(Src1Mods ? Src1Mods->getImm() : 0)
2703 .addImm(0) // Src mods
2705 .addImm(Clamp ? Clamp->getImm() : 0)
2706 .addImm(Omod ? Omod->getImm() : 0);
4248 MIB.addImm(RI.getSubRegFromChannel(i));
4361 .addImm(AMDGPU::sub0)
4363 .addImm(AMDGPU::sub1)
4365 .addImm(AMDGPU::sub2)
4367 .addImm(AMDGPU::sub3);
4491 .addImm(0);
4495 .addImm(RsrcDataFormat & 0xFFFFFFFF);
4499 .addImm(RsrcDataFormat >> 32);
4504 .addImm(AMDGPU::sub0_sub1)
4506 .addImm(AMDGPU::sub2)
4508 .addImm(AMDGPU::sub3);
4715 .addImm(0);
4723 .addImm(0);
4728 .addImm(AMDGPU::sub0)
4730 .addImm(AMDGPU::sub1);
4768 MIB.addImm(GLC->getImm());
4772 MIB.addImm(DLC->getImm());
4775 MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc));
4779 MIB.addImm(TFE->getImm());
4782 MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::swz));
4795 .addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc))
4805 .addImm(AMDGPU::sub0)
4807 .addImm(AMDGPU::sub1);
5152 .addImm(0)
5324 .addImm(AMDGPU::sub0)
5326 .addImm(AMDGPU::sub1);
5384 .addImm(0); // clamp bit
5393 .addImm(0); // clamp bit
5397 .addImm(AMDGPU::sub0)
5399 .addImm(AMDGPU::sub1);
5463 .addImm(AMDGPU::sub0)
5465 .addImm(AMDGPU::sub1);
5544 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
5580 .addImm(0)
5581 .addImm(BitWidth);
5584 .addImm(31)
5589 .addImm(AMDGPU::sub0)
5591 .addImm(AMDGPU::sub1);
5603 .addImm(31)
5608 .addImm(AMDGPU::sub0)
5610 .addImm(AMDGPU::sub1);
5669 .addImm(0xffff);
5677 .addImm(16)
5684 .addImm(0xffff);
5695 .addImm(16)
5698 .addImm(0xffff0000);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 913 .addImm(CI.BaseOff);
921 .addImm(0); // clamp bit
928 .addImm(NewOffset0) // offset0
929 .addImm(NewOffset1) // offset1
930 .addImm(0) // gds
1006 .addImm(CI.BaseOff);
1014 .addImm(0); // clamp bit
1023 .addImm(NewOffset0) // offset0
1024 .addImm(NewOffset1) // offset1
1025 .addImm(0) // gds
1053 MIB.addImm(MergedDMask);
1113 .addImm(MergedOffset) // offset
1114 .addImm(CI.GLC0) // glc
1115 .addImm(CI.DLC0) // dlc
1172 .addImm(MergedOffset) // offset
1173 .addImm(CI.GLC0) // glc
1174 .addImm(CI.SLC0) // slc
1175 .addImm(0) // tfe
1176 .addImm(CI.DLC0) // dlc
1177 .addImm(0) // swz
1315 .addImm(SubRegIdx0)
1317 .addImm(SubRegIdx1);
1339 .addImm(std::min(CI.Offset0, CI.Offset1)) // offset
1340 .addImm(CI.GLC0) // glc
1341 .addImm(CI.SLC0) // slc
1342 .addImm(0) // tfe
1343 .addImm(CI.DLC0) // dlc
1344 .addImm(0) // swz
1364 .addImm(Val);
1401 .addImm(0); // clamp bit
1411 .addImm(0); // clamp bit
1419 .addImm(AMDGPU::sub0)
1421 .addImm(AMDGPU::sub1);
lib/Target/AMDGPU/SILowerI1Copies.cpp 526 .addImm(0)
527 .addImm(0)
528 .addImm(0)
529 .addImm(-1)
706 .addImm(0);
830 .addImm(-1);
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 841 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate);
1107 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate);
1114 .addImm(0);
lib/Target/AMDGPU/SIModeRegister.cpp 199 .addImm(Value)
200 .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) |
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1034 SDWAInst.addImm(Mod->getImm());
1036 SDWAInst.addImm(0);
1046 SDWAInst.addImm(Mod->getImm());
1048 SDWAInst.addImm(0);
1068 SDWAInst.addImm(0);
1077 SDWAInst.addImm(0);
1087 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
1097 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD);
1107 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
1117 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
1196 Copy.addImm(Op.getImm());
lib/Target/AMDGPU/SIRegisterInfo.cpp 367 .addImm(Offset);
374 .addImm(0); // clamp bit
599 .addImm(Offset)
600 .addImm(0) // glc
601 .addImm(0) // slc
602 .addImm(0) // tfe
603 .addImm(0) // dlc
604 .addImm(0) // swz
681 .addImm(Offset);
719 .addImm(Offset)
720 .addImm(0) // glc
721 .addImm(0) // slc
722 .addImm(0) // tfe
723 .addImm(0) // dlc
724 .addImm(0) // swz
741 .addImm(ScratchOffsetRegDelta);
808 .addImm(Spill.Lane)
848 .addImm(i * 4) // offset
906 .addImm(Spill.Lane);
931 .addImm(i * 4) // offset
1118 .addImm(ST.getWavefrontSizeLog2())
1127 .addImm(ST.getWavefrontSizeLog2())
1135 MIB.addImm(Offset);
1138 MIB.addImm(0); // clamp bit
1147 .addImm(Offset);
1150 MIB.addImm(0); // clamp bit
1166 .addImm(ST.getWavefrontSizeLog2());
1169 .addImm(Offset);
1177 .addImm(Offset);
1180 .addImm(ST.getWavefrontSizeLog2());
1231 .addImm(Offset);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 674 .addImm(-1);
lib/Target/ARC/ARCBranchFinalize.cpp 122 .addImm(getCCForBRcc(MI->getOperand(3).getImm()));
138 .addImm(MI->getOperand(3).getImm());
lib/Target/ARC/ARCExpandPseudos.cpp 67 .addImm(SI.getOperand(2).getImm());
72 .addImm(0);
lib/Target/ARC/ARCFrameLowering.cpp 74 .addImm(AbsAmount);
145 .addImm(VarArgsBytes);
153 .addImm(-4);
164 .addImm(4 * StackSlotsUsedByFunclet);
192 .addImm(MFI.getStackSize());
260 .addImm(StackSize);
290 .addImm(StackSize - AmountAboveFunclet);
305 .addImm(4 * (StackSlotsUsedByFunclet));
317 .addImm(4);
333 .addImm(VarArgsBytes);
466 .addImm(NumBytes);
lib/Target/ARC/ARCInstrInfo.cpp 318 .addImm(0)
345 .addImm(0)
364 .addImm(Value)
lib/Target/ARC/ARCRegisterInfo.cpp 52 .addImm(Offset)
78 .addImm(Offset);
95 .addImm(Offset)
109 .addImm(Offset)
118 .addImm(Offset);
lib/Target/ARM/A15SDOptimizer.cpp 426 .addImm(Lane)
457 .addImm(ARM::dsub_0)
459 .addImm(ARM::dsub_1);
473 .addImm(1)
488 .addImm(Lane);
lib/Target/ARM/ARMBaseInstrInfo.cpp 193 .addImm(Amt)
204 .addImm(SOOpc)
224 .addImm(Amt)
244 .addImm(0)
245 .addImm(Pred);
251 .addImm(0)
252 .addImm(Pred);
260 .addImm(0)
261 .addImm(Pred);
267 .addImm(0)
268 .addImm(Pred);
458 .addImm(Cond[0].getImm())
466 .addImm(Cond[0].getImm())
504 .addImm(Pred[0].getImm())
782 MIB.addImm(0x800);
799 MIB.addImm(0x800);
801 MIB.addImm(8);
809 MIB.addImm(ARMVCC::None);
820 MIB.addImm(Cond);
1046 .addImm(0)
1057 .addImm(0)
1064 .addImm(0)
1071 .addImm(0)
1082 .addImm(0)
1090 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1111 .addImm(16)
1127 .addImm(0)
1140 .addImm(16)
1165 .addImm(16)
1287 .addImm(0)
1297 .addImm(0)
1303 .addImm(0)
1309 .addImm(0)
1319 .addImm(0)
1329 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1352 .addImm(16)
1365 .addImm(0)
1377 .addImm(16)
1400 .addImm(16)
1712 .addImm(PCLabelId)
2267 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
2269 NewMI.addImm(CondCode);
2390 .addImm(ThisVal)
3321 .addImm(SOImmValV1)
4785 MIB.addReg(Reg, RegState::Kill).addImm(0);
4796 .addImm(0)
4982 .addImm(Lane)
5013 .addImm(Lane)
5048 .addImm(SrcLane)
5086 .addImm(1)
5104 .addImm(1)
5226 .addImm(96)
lib/Target/ARM/ARMBaseRegisterInfo.cpp 472 .addImm(0)
649 .addFrameIndex(FrameIdx).addImm(Offset);
lib/Target/ARM/ARMCallLowering.cpp 579 CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
579 CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
582 .addImm(ArgHandler.StackSize)
583 .addImm(0)
lib/Target/ARM/ARMConstantIslandPass.cpp 532 .addImm(i).addConstantPoolIndex(i).addImm(Size);
532 .addImm(i).addConstantPoolIndex(i).addImm(Size);
600 .addImm(i++)
602 .addImm(Size);
1525 .addImm(ID)
1527 .addImm(Size);
1718 .addMBB(NextBB).addImm(CC).addReg(CCReg);
2301 .addImm(CPEMI->getOperand(0).getImm());
lib/Target/ARM/ARMExpandPseudoInsts.cpp 725 MIB.addImm(Lane);
855 LO16 = LO16.addImm(SOImmValV1);
856 HI16 = HI16.addImm(SOImmValV2);
859 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
860 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
888 LO16 = LO16.addImm(Lo16);
889 HI16 = HI16.addImm(Hi16);
910 LO16.addImm(Pred).addReg(PredReg);
911 HI16.addImm(Pred).addReg(PredReg);
958 MIB.addImm(0);
971 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
982 .addImm(ARMCC::NE)
995 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
1001 .addImm(0)
1005 .addImm(ARMCC::NE)
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1103 .addImm(ARMCC::NE)
1121 .addImm(0)
1125 .addImm(ARMCC::NE)
1222 .addImm(MI.getOperand(3).getImm()) // 'pred'
1235 .addImm(MI.getOperand(3).getImm()) // 'pred'
1247 .addImm(MI.getOperand(3).getImm())
1248 .addImm(MI.getOperand(4).getImm()) // 'pred'
1261 .addImm(MI.getOperand(4).getImm())
1262 .addImm(MI.getOperand(5).getImm()) // 'pred'
1275 .addImm(MI.getOperand(2).getImm())
1276 .addImm(MI.getOperand(3).getImm()) // 'pred'
1287 .addImm(MI.getOperand(2).getImm())
1288 .addImm(MI.getOperand(3).getImm()) // 'pred'
1301 .addImm(MI.getOperand(2).getImm())
1302 .addImm(MI.getOperand(3).getImm()) // 'pred'
1325 .addImm(MI.getOperand(3).getImm())
1326 .addImm(MI.getOperand(4).getImm()) // 'pred'
1371 .addImm(MaxAlign - 1)
1387 .addImm(ARM_AM::getSORegOpc(
1400 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1424 MIB.addImm(0);
1508 MIB.addImm(0);
1516 .addImm(ARMPCLabelIndex);
1546 .addImm(LabelId);
1551 .addImm(LabelId);
1556 .addReg(DstReg).addImm(LabelId);
lib/Target/ARM/ARMFastISel.cpp 365 .addImm(Imm));
369 .addImm(Imm));
385 ResultReg).addImm(Imm));
388 .addImm(Imm));
439 TII.get(Opc), DestReg).addImm(Imm));
478 .addImm(CI->getZExtValue()));
494 .addImm(Imm));
528 .addImm(0));
597 MIB.addImm(Id);
605 .addImm(0);
615 .addImm(Id);
629 .addImm(0);
634 .addImm(0);
682 .addImm(0));
856 .addImm(0));
894 MIB.addImm(Imm);
896 MIB.addImm(Addr.Offset);
908 MIB.addImm(Imm);
910 MIB.addImm(Addr.Offset);
1069 .addReg(SrcReg).addImm(1));
1267 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1280 .addReg(OpReg).addImm(1));
1290 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1318 .addImm(1));
1328 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1457 MIB.addImm(Imm);
1492 .addReg(ZeroReg).addImm(1)
1493 .addImm(ARMPred).addReg(ARM::CPSR);
1654 .addImm(1));
1676 .addImm(ARMCC::NE)
1683 .addImm(Imm)
1684 .addImm(ARMCC::EQ)
1949 .addImm(NumBytes).addImm(0));
1949 .addImm(NumBytes).addImm(0));
2041 .addImm(NumBytes).addImm(0));
2041 .addImm(NumBytes).addImm(0));
2513 .addReg(SrcReg).addImm(0));
2727 .addImm(ImmEnc)
2807 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2810 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2974 MIB.addImm(0);
2984 .addImm(ARMPCLabelIndex);
2994 .addImm(0);
lib/Target/ARM/ARMFrameLowering.cpp 305 .addImm(~AlignMask)
310 .addImm(AlignMask)
320 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))
325 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))
335 .addImm(~AlignMask)
523 .addImm(NumWords)
528 .addImm(NumWords)
1035 .addImm(-4)
1145 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1147 MIB.addImm(4);
1211 .addImm(8 * NumAlignedDPRCS2Regs)
1246 .addImm(16)
1265 .addImm(16)
1280 .addImm(16)
1294 .addImm((NextReg - R4BaseReg) * 2)
1364 .addImm(0)
1378 .addImm(16)
1395 .addImm(16)
1408 .addImm(16)
1418 .addImm(2 * (NextReg - R4BaseReg))
2397 .addImm(AlignedStackSize)
2402 .addImm(AlignedStackSize)
2422 .addImm(0)
2428 .addImm(15)
2429 .addImm(0)
2430 .addImm(13)
2431 .addImm(0)
2432 .addImm(3)
2443 .addImm(4 * TlsOffset)
2458 .addImm(ARMCC::LO)
2471 .addImm(AlignedStackSize)
2475 .addImm(AlignedStackSize)
2484 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2488 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2541 .addImm(4)
lib/Target/ARM/ARMISelLowering.cpp 9387 .addImm(0x01)
9393 .addImm(PCLabelId);
9397 .addImm(36) // &jbuf[1] :: pc
9416 .addImm(PCLabelId);
9421 .addImm(1)
9432 .addImm(36); // &jbuf[1] :: pc
9436 .addImm(0)
9447 .addImm(0)
9453 .addImm(PCLabelId)
9458 .addImm(36) // &jbuf[1] :: pc
9575 .addImm(4)
9582 .addImm(LPadList.size())
9587 .addImm(NumLPads & 0xFFFF)
9595 .addImm(NumLPads >> 16)
9607 .addImm(ARMCC::HI)
9619 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
9631 .addImm(1)
9638 .addImm(NumLPads)
9664 .addImm(ARMCC::HI)
9671 .addImm(2)
9692 .addImm(0)
9713 .addImm(4)
9720 .addImm(NumLPads)
9725 .addImm(NumLPads & 0xFFFF)
9733 .addImm(NumLPads >> 16)
9756 .addImm(0)
9766 .addImm(ARMCC::HI)
9772 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
9786 .addImm(0)
9936 .addImm(0)
9942 .addImm(0)
9947 .addImm(LdSize)
9953 .addImm(LdSize)
9960 .addImm(LdSize)
9976 .addImm(0)
9984 .addImm(0)
9989 .addImm(StSize)
9995 .addImm(StSize)
10002 .addImm(StSize)
10135 .addImm(LoopSize & 0xFFFF)
10141 .addImm(LoopSize >> 16)
10167 .addImm(0)
10209 .addImm(UnitSize)
10216 .addImm(UnitSize)
10224 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
10350 .addImm(0)
10354 .addImm(ARMCC::EQ)
10452 .addImm(Offset) // offset (skip GPR==zero_reg)
10515 .addImm(MI.getOperand(3).getImm())
10554 .addImm(0)
10557 .addReg(LHS2).addImm(0)
10558 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10568 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10577 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
10646 .addImm(0)
10652 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
10660 .addImm(0)
lib/Target/ARM/ARMInstrInfo.cpp 133 .addImm(0)
lib/Target/ARM/ARMInstructionSelector.cpp 495 .addImm(Constant)
600 .addImm(1)
648 MIB.addImm(0);
697 .addImm(0)
778 .addImm(1)
807 MIB.addImm(ShiftOpc);
821 NewInstBuilder.addImm(FPImmEncoding);
833 NewInstBuilder.addImm(FPImmEncoding);
873 MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
887 .addImm(0)
901 MIB.addImm(0).add(predOps(ARMCC::AL));
1003 .addImm(0)
1072 MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
1108 .addImm(1)
1120 MIB.addImm(0).add(predOps(ARMCC::AL));
1143 .addImm(1)
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 553 .addImm(WordOffset * 4)
554 .addImm(Pred)
574 .addImm(WordOffset * 4)
575 .addImm(Pred)
751 .addImm(Offset / 4)
757 .addImm(Offset)
762 .addImm(Offset)
815 MIB.addImm(Pred).addReg(PredReg);
845 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
845 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1320 .addImm(Pred).addReg(PredReg);
1444 .addImm(Pred).addReg(PredReg)
1454 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg)
1454 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg)
1462 .addImm(Imm)
1471 .addImm(Offset)
1487 .addImm(Imm)
1495 .addImm(Offset)
1549 .addImm(Offset).addImm(Pred).addReg(PredReg);
1549 .addImm(Offset).addImm(Pred).addReg(PredReg);
1632 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1632 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1641 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1641 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1700 .addImm(Pred).addReg(PredReg)
1708 .addImm(Pred).addReg(PredReg)
2338 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2338 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2352 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2352 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
lib/Target/ARM/ARMLowOverheadLoops.cpp 365 MIB.addImm(0);
366 MIB.addImm(ARMCC::AL);
375 MIB.addImm(ARMCC::EQ); // condition code
400 MIB.addImm(ARMCC::AL);
423 MIB.addImm(0);
424 MIB.addImm(ARMCC::AL);
436 MIB.addImm(ARMCC::NE); // condition code
lib/Target/ARM/MLxExpansionPass.cpp 294 MIB.addImm(LaneImm);
295 MIB.addImm(Pred).addReg(PredReg);
307 MIB.addImm(Pred).addReg(PredReg);
lib/Target/ARM/MVEVPTBlockPass.cpp 237 MIBuilder.addImm(BlockMask);
244 MIBuilder.addImm(BlockMask);
lib/Target/ARM/Thumb1FrameLowering.cpp 85 .addImm(NumBytes).setMIFlags(MIFlags);
304 .addImm(FramePtrOffsetInBlock / 4)
419 .addImm(NrBitsToZero)
425 .addImm(NrBitsToZero)
724 .addImm(MBBI->getNumExplicitOperands() - 2)
lib/Target/ARM/Thumb1InstrInfo.cpp 99 .addImm(0)
127 .addImm(0)
lib/Target/ARM/Thumb2ITBlockPass.cpp 215 .addImm(CC);
269 MIB.addImm(Mask);
lib/Target/ARM/Thumb2InstrInfo.cpp 152 .addImm(0)
170 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
193 .addImm(0)
211 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
240 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
256 .addImm(NumBytes)
257 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
263 .addImm(NumBytes >> 16)
264 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
314 .addImm(ThisVal / 4)
355 .addImm(ThisVal)
lib/Target/ARM/Thumb2SizeReduction.cpp 483 .addImm(PredImm)
594 MIB.addImm(OffsetImm / Scale);
655 .addImm(Imm / 4) // The tADDrSPi has an implied scale by four.
lib/Target/ARM/ThumbRegisterInfo.cpp 77 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
151 .addImm(NumBytes)
156 .addImm(NumBytes)
164 .addImm(NumBytes).setMIFlags(MIFlags);
317 MIB.addImm(CopyImm);
333 .addImm(ExtraImm)
lib/Target/AVR/AVRExpandPseudoInsts.cpp 236 .addImm(Lo8);
246 .addImm(Hi8);
300 MIBLO.addImm(Imm & 0xff);
301 MIBHI.addImm((Imm >> 8) & 0xff);
341 .addImm(Lo8);
349 .addImm(Hi8);
521 MIBLO.addImm(Imm & 0xff);
522 MIBHI.addImm((Imm >> 8) & 0xff);
562 MIBLO.addImm(Imm);
563 MIBHI.addImm(Imm + 1);
609 .addImm(1);
716 .addImm(Imm);
726 .addImm(Imm + 1);
804 .addImm(SREG_ADDR);
807 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
813 .addImm(SREG_ADDR)
994 MIBLO.addImm(Imm);
995 MIBHI.addImm(Imm + 1);
1030 .addImm(1)
1059 .addImm(Imm);
1065 .addImm(Imm);
1093 .addImm(Imm);
1099 .addImm(Imm);
1127 .addImm(Imm)
1132 .addImm(Imm + 1)
1159 .addImm(Imm);
1163 .addImm(Imm + 1);
1189 .addImm(Imm + 1)
1193 .addImm(Imm)
1461 .addImm(0x3d)
1467 .addImm(0x3e)
1485 .addImm(SREG_ADDR)
1488 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
1491 .addImm(0x3e)
1496 .addImm(SREG_ADDR)
1501 .addImm(0x3d)
lib/Target/AVR/AVRFrameLowering.cpp 65 .addImm(0x07)
85 .addImm(0x3f)
133 .addImm(FrameSize)
172 .addImm(0x3f)
210 .addImm(FrameSize);
405 .addImm(Amount);
lib/Target/AVR/AVRISelLowering.cpp 1529 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1554 .addImm(1);
lib/Target/AVR/AVRInstrInfo.cpp 154 .addImm(0)
190 .addImm(0)
lib/Target/AVR/AVRRegisterInfo.cpp 198 .addImm(Offset);
222 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
226 .addImm(AddOffset);
231 .addImm(0x3f)
238 .addImm(Offset - 63 + 1);
lib/Target/AVR/AVRRelaxMemOperations.cpp 106 .addImm(-Imm);
lib/Target/BPF/BPFISelLowering.cpp 578 .addReg(PromotedReg0).addImm(32);
580 .addReg(PromotedReg1).addImm(32);
729 .addReg(LHS).addImm(imm32).addMBB(Copy1MBB);
lib/Target/BPF/BPFInstrInfo.cpp 80 .addImm(I * Alignment);
83 .addImm(I * Alignment);
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
137 .addImm(0);
142 .addImm(0);
157 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0);
159 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0);
lib/Target/BPF/BPFMIPeephole.cpp 171 .addImm(0).addReg(SubReg).addImm(BPF::sub_32);
171 .addImm(0).addReg(SubReg).addImm(BPF::sub_32);
lib/Target/BPF/BPFRegisterInfo.cpp 92 .addImm(Offset);
114 .addImm(Offset);
lib/Target/Hexagon/HexagonBitSimplify.cpp 1415 .addImm(int32_t(C));
1422 .addImm(C);
1431 .addImm(int32_t(Hi))
1432 .addImm(int32_t(Lo));
1437 .addImm(C);
1631 .addImm(SubLo)
1633 .addImm(SubHi);
2066 .addImm(16);
2160 MIB.addImm((1 << W) - 1);
2162 MIB.addImm(W).addImm(0);
2162 MIB.addImm(W).addImm(0);
2301 .addImm(ImmOp);
2362 .addImm(P);
2553 MIB.addImm((1u << Len) - 1);
2559 MIB.addImm(Len)
2560 .addImm(Off);
2615 .addImm(C);
2681 .addImm(KnownZ1 == (Opc == Hexagon::A4_rcmpeqi))
2682 .addImm(KnownZ2 == (Opc == Hexagon::A4_rcmpeqi));
3290 .addImm(0);
lib/Target/Hexagon/HexagonConstExtenders.cpp 1570 .addImm(Ex.S);
1600 .addImm(Hexagon::isub_hi)
1602 .addImm(Hexagon::isub_lo);
1607 .addImm(Hexagon::isub_hi)
1609 .addImm(Hexagon::isub_lo);
1683 MIB.addImm(Shift); // << Shift
1734 .addImm(D);
1809 MIB.addImm(Diff);
lib/Target/Hexagon/HexagonConstPropagation.cpp 2902 .addImm(V);
2907 .addImm(V);
2914 .addImm(Hi)
2915 .addImm(Lo);
2919 .addImm(V);
3017 .addImm(V);
lib/Target/Hexagon/HexagonCopyToCombine.cpp 660 .addImm(V);
675 .addImm(LoOperand.getImm());
680 .addImm(HiOperand.getImm())
691 .addImm(LoOperand.getImm());
696 .addImm(HiOperand.getImm())
706 .addImm(LoOperand.getImm());
711 .addImm(HiOperand.getImm())
721 .addImm(LoOperand.getImm());
726 .addImm(HiOperand.getImm())
737 .addImm(HiOperand.getImm())
738 .addImm(LoOperand.getImm());
745 .addImm(HiOperand.getImm())
746 .addImm(LoOperand.getImm());
753 .addImm(HiOperand.getImm())
754 .addImm(LoOperand.getImm());
801 .addImm(HiOperand.getImm())
851 .addImm(LoOperand.getImm());
lib/Target/Hexagon/HexagonFrameLowering.cpp 630 .addImm(-int64_t(MaxAlign));
642 .addImm(-int(NumBytes));
661 .addImm(NumBytes);
757 .addImm(0)
764 .addImm(-int(NumBytes));
769 .addImm(NumBytes)
1613 .addImm(0)
1638 .addImm(0)
1674 .addImm(0x01010101);
1709 .addImm(0x01010101);
1765 .addImm(0)
1776 .addImm(Size)
1811 .addImm(0)
1819 .addImm(Size)
1847 .addImm(0)
1875 .addImm(0)
2369 .addImm(-int64_t(A));
2373 .addImm(-int64_t(A));
2384 .addImm(CF);
lib/Target/Hexagon/HexagonGenInsert.cpp 1436 .addImm(Wdh)
1437 .addImm(Off);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 921 SubIB.addImm(EndV)
938 .addImm(-StartV);
957 .addImm(AdjV);
978 .addImm(Shift);
1262 .addImm(CountImm);
1267 .addMBB(LoopStart).addImm(CountImm);
1592 BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR).addImm(Val);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1274 .addImm(MaxA);
lib/Target/Hexagon/HexagonInstrInfo.cpp 639 addImm(Cond[2].getImm()).addMBB(TBB);
714 .addImm(TC);
746 .addImm(TripCountAdjust);
902 .addFrameIndex(FI).addImm(0)
906 .addFrameIndex(FI).addImm(0)
910 .addFrameIndex(FI).addImm(0)
914 .addFrameIndex(FI).addImm(0)
918 .addFrameIndex(FI).addImm(0)
930 .addFrameIndex(FI).addImm(0)
942 .addFrameIndex(FI).addImm(0)
967 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
970 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
973 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
976 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
979 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
990 .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
1001 .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
1058 .addImm(-MI.getOperand(1).getImm());
1100 .addImm(MI.getOperand(1).getImm())
1107 .addImm(MI.getOperand(1).getImm() + Offset)
1123 .addImm(MI.getOperand(2).getImm())
1129 .addImm(MI.getOperand(2).getImm() + Offset)
1352 .addImm(0xBADC0FEE) // Misaligned load.
1448 .addImm(0)
1460 .addImm(0)
1472 .addImm(0)
1485 .addImm(0)
1498 .addImm(0)
1511 .addImm(0)
lib/Target/Hexagon/HexagonNewValueJump.cpp 700 .addImm(cmpOp2)
lib/Target/Hexagon/HexagonRegisterInfo.cpp 224 .addImm(RealOffset);
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 83 .addImm(ImmValue);
96 .addImm(LowWord);
98 .addImm(HighWord);
lib/Target/Hexagon/HexagonSplitDouble.cpp 654 .addImm(Off);
657 .addImm(Off+4);
663 .addImm(Off)
667 .addImm(Off+4)
681 .addImm(Inc);
722 .addImm(int32_t(V & 0xFFFFFFFFULL));
724 .addImm(int32_t(V >> 32));
774 .addImm(31);
843 .addImm(S);
849 .addImm(S)
850 .addImm(32-S);
855 .addImm(S);
860 .addImm(S);
865 .addImm(S)
866 .addImm(32-S);
873 .addImm(0);
877 .addImm(31);
889 .addImm(S);
894 .addImm(31);
897 .addImm(0);
955 .addImm(S);
959 .addImm(S)
960 .addImm(32-S);
968 .addImm(S);
990 .addImm(S);
1119 .addImm(Hexagon::isub_lo)
1121 .addImm(Hexagon::isub_hi);
lib/Target/Hexagon/HexagonStoreWidening.cpp 436 .addImm(Off)
437 .addImm(Val);
446 .addImm(int(Acc));
459 .addImm(Off)
lib/Target/Hexagon/HexagonVExtract.cpp 84 .addImm(V);
92 .addImm(-4);
96 .addImm(0);
135 .addImm(0)
150 .addImm(SR == 0 ? 0 : VecSize/2);
lib/Target/Hexagon/HexagonVectorPrint.cpp 104 .addImm(ExtraInfo);
lib/Target/Lanai/LanaiFrameLowering.cpp 80 .addImm(MaxCallFrameSize);
116 .addImm(-4)
117 .addImm(LPAC::makePreOp(LPAC::ADD))
124 .addImm(8)
132 .addImm(StackSize)
188 .addImm(0);
193 .addImm(-8)
194 .addImm(LPAC::ADD);
lib/Target/Lanai/LanaiInstrInfo.cpp 46 .addImm(0);
65 .addImm(0)
66 .addImm(LPAC::ADD);
84 .addImm(0)
85 .addImm(LPAC::ADD);
524 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
526 NewMI.addImm(CondCode);
681 BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
lib/Target/Lanai/LanaiMemAluCombiner.cpp 267 InstrBuilder.addImm(AluOffset.getImm());
275 InstrBuilder.addImm(LPAC::makePreOp(AluOpcode));
277 InstrBuilder.addImm(LPAC::makePostOp(AluOpcode));
lib/Target/Lanai/LanaiRegisterInfo.cpp 189 .addImm(static_cast<uint32_t>(Offset) >> 16);
192 .addImm(Offset & 0xffffU);
196 .addImm(0)
197 .addImm(Offset);
206 .addImm(LPCC::ICC_T);
241 .addImm(-Offset);
lib/Target/MSP430/MSP430FrameLowering.cpp 99 .addReg(MSP430::SP).addImm(NumBytes);
162 .addReg(MSP430::SP).addImm(CSSize);
171 .addReg(MSP430::SP).addImm(NumBytes);
250 .addImm(Amount);
259 .addImm(Amount);
278 .addImm(CalleeAmt);
lib/Target/MSP430/MSP430ISelLowering.cpp 1451 .addReg(MSP430::SR).addImm(1);
1497 .addReg(ShiftAmtSrcReg).addImm(0);
1500 .addImm(MSP430CC::COND_E);
1515 .addReg(MSP430::SR).addImm(1);
1524 .addReg(ShiftAmtReg).addImm(1);
1527 .addImm(MSP430CC::COND_NE);
1586 .addImm(MI.getOperand(3).getImm());
lib/Target/MSP430/MSP430InstrInfo.cpp 53 .addFrameIndex(FrameIdx).addImm(0)
57 .addFrameIndex(FrameIdx).addImm(0)
81 .addImm(0).addMemOperand(MMO);
85 .addImm(0).addMemOperand(MMO);
286 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
lib/Target/MSP430/MSP430RegisterInfo.cpp 145 .addReg(DstReg).addImm(-Offset);
148 .addReg(DstReg).addImm(Offset);
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
lib/Target/Mips/Mips16ISelLowering.cpp 677 .addImm(MI.getOperand(4).getImm());
739 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
784 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
lib/Target/Mips/Mips16InstrInfo.cpp 124 addFrameIndex(FI).addImm(Offset)
142 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
230 MIB.addImm(FrameSize);
235 MIB.addImm(Base);
272 MIB.addImm(FrameSize);
292 MIB1.addImm(Amount).addImm(-1);
292 MIB1.addImm(Amount).addImm(-1);
404 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
404 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
468 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
lib/Target/Mips/MipsBranchExpansion.cpp 389 Instr.addImm(0);
458 .addImm(-8);
462 .addImm(0);
507 .addImm(0);
519 .addImm(8);
527 .addImm(8);
581 .addImm(-16);
585 .addImm(0);
593 .addImm(16);
618 .addImm(0);
626 .addImm(16);
630 .addImm(16);
685 .addImm(16);
692 .addImm(16);
lib/Target/Mips/MipsCallLowering.cpp 263 .addImm(1)
271 .addImm(0)
629 CallSeqStart.addImm(NextStackOffset).addImm(0);
629 CallSeqStart.addImm(NextStackOffset).addImm(0);
666 MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
666 MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
lib/Target/Mips/MipsConstantIslandPass.cpp 569 .addImm(i).addConstantPoolIndex(i).addImm(Size);
569 .addImm(i).addConstantPoolIndex(i).addImm(Size);
1389 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
1389 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
lib/Target/Mips/MipsExpandPseudo.cpp 145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
166 .addImm(0);
185 .addImm(ShiftImm);
188 .addImm(ShiftImm);
278 BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
288 .addReg(Scratch).addReg(Ptr).addImm(0);
404 BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
443 .addReg(StoreVal).addReg(Ptr).addImm(0);
465 .addImm(ShiftImm);
468 .addImm(ShiftImm);
592 BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
607 BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
lib/Target/Mips/MipsFastISel.cpp 221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
349 .addImm(0);
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
381 emitInst(Mips::LUi, TmpReg).addImm(Hi);
382 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
384 emitInst(Mips::LUi, ResultReg).addImm(Hi);
655 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
673 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
679 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
691 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
697 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
806 .addImm(Offset)
858 .addImm(Offset)
1152 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1152 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1282 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1282 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1618 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1619 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1621 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1629 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1640 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1641 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1642 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1645 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1646 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1648 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1846 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1847 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1893 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
2009 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
lib/Target/Mips/MipsISelLowering.cpp 1278 .addImm(7);
1562 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1563 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1671 .addReg(ABI.GetNullPtr()).addImm(-4);
1675 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1677 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1681 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1682 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1685 .addReg(Mips::ZERO).addImm(MaskImm);
1852 .addReg(ABI.GetNullPtr()).addImm(-4);
1856 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1858 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1862 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1863 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1866 .addReg(Mips::ZERO).addImm(MaskImm);
1871 .addReg(CmpVal).addImm(MaskImm);
1875 .addReg(NewVal).addImm(MaskImm);
lib/Target/Mips/MipsInstrInfo.cpp 654 MIB.addImm(0);
lib/Target/Mips/MipsInstructionSelector.cpp 135 .addImm(Imm.getLoBits(16).getLimitedValue());
141 .addImm(Imm.getHiBits(16).getLimitedValue());
147 .addImm(Imm.getLoBits(16).getLimitedValue());
153 .addImm(Imm.getHiBits(16).getLimitedValue());
155 .addImm(Imm.getLoBits(16).getLimitedValue());
301 .addImm(0);
321 .addImm(Log2_32(EntrySize));
416 .addImm(SignedOffset)
695 MIB.addImm(Instruction.RHS);
760 .addImm(1);
769 .addImm(MipsFCMPCondCode);
785 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
797 .addImm(0);
804 .addImm(0);
lib/Target/Mips/MipsSEFrameLowering.cpp 546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
600 .addImm(0)
605 .addImm(10)
606 .addImm(6)
614 .addImm(0)
625 .addImm(0)
659 .addImm(InsPosition)
660 .addImm(InsSize)
667 .addImm(1)
668 .addImm(4)
676 .addImm(29)
677 .addImm(1)
684 .addImm(0)
766 .addImm(0);
774 .addImm(0);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 148 .addImm(-8);
lib/Target/Mips/MipsSEISelLowering.cpp 3069 .addReg(Mips::ZERO).addImm(0);
3075 .addReg(Mips::ZERO).addImm(1);
3138 .addReg(Mips::ZERO).addImm(0);
3144 .addReg(Mips::ZERO).addImm(1);
3194 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3229 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3258 .addImm(0)
3260 .addImm(Mips::sub_lo);
3263 .addImm(Lane)
3265 .addImm(0);
3292 .addImm(0)
3294 .addImm(Mips::sub_64);
3297 .addImm(Lane)
3299 .addImm(0);
3377 .addImm(0)
3379 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3388 .addImm(EltLog2Size);
3404 .addImm(0)
3406 .addImm(0);
3412 .addImm(0);
3458 .addImm(Mips::sub_lo);
3459 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3489 .addImm(Mips::sub_64);
3490 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3529 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3533 .addImm(0)
3535 .addImm(Mips::sub_32);
3541 .addImm(Imm)
3689 .addImm(1);
3693 .addImm(3);
3793 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3800 .addImm(1);
3827 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3856 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
lib/Target/Mips/MipsSEInstrInfo.cpp 111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
320 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
382 .addImm(Offset)
402 .addImm(Offset)
592 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
634 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
637 .addImm(SignExtend64<16>(Inst->ImmOpnd));
642 .addImm(SignExtend64<16>(Inst->ImmOpnd));
lib/Target/Mips/MipsSERegisterInfo.cpp 231 .addImm(Offset);
lib/Target/NVPTX/NVPTXFrameLowering.cpp 62 .addImm(MF.getFunctionNumber());
lib/Target/PowerPC/PPCBranchSelector.cpp 343 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
343 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
346 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
349 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
351 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
353 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
355 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
357 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
lib/Target/PowerPC/PPCEarlyReturn.cpp 93 .addImm(J->getOperand(0).getImm())
lib/Target/PowerPC/PPCFastISel.cpp 437 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
542 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
550 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
689 .addImm(Addr.Offset)
700 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
797 .addImm(PPCSubTarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
952 .addReg(SrcReg1).addImm(Imm);
1351 .addImm(Imm);
1421 .addImm(NumBytes).addImm(0);
1421 .addImm(NumBytes).addImm(0);
1496 .addImm(NumBytes).addImm(0);
1496 .addImm(NumBytes).addImm(0);
1836 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1836 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1836 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1849 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1849 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
2032 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2044 .addImm(0)
2122 .addImm(Imm);
2128 .addImm(Hi);
2131 .addReg(TmpReg).addImm(Lo);
2136 .addImm(Hi);
2175 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2175 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2183 TmpReg3).addReg(TmpReg2).addImm(Hi);
2190 ResultReg).addReg(TmpReg3).addImm(Lo);
2226 .addImm(Imm);
2278 ResultReg).addFrameIndex(SI->second).addImm(0);
lib/Target/PowerPC/PPCFrameLowering.cpp 388 .addImm(UsedRegMask);
392 .addImm(UsedRegMask);
397 .addImm(UsedRegMask >> 16);
401 .addImm(UsedRegMask >> 16);
406 .addImm(UsedRegMask >> 16);
410 .addImm(UsedRegMask >> 16);
414 .addImm(UsedRegMask & 0xFFFF);
983 .addImm(getCRSaveOffset())
1012 .addImm(FPOffset)
1017 .addImm(PBPOffset)
1022 .addImm(BPOffset)
1029 .addImm(LROffset)
1037 .addImm(getCRSaveOffset())
1064 .addImm(0)
1065 .addImm(64 - Log2_32(MaxAlign));
1069 .addImm(0)
1070 .addImm(32 - Log2_32(MaxAlign))
1071 .addImm(31);
1075 .addImm(NegFrameSize);
1079 .addImm(NegFrameSize >> 16);
1082 .addImm(NegFrameSize & 0xFFFF);
1097 .addImm(NegFrameSize)
1102 .addImm(NegFrameSize >> 16);
1105 .addImm(NegFrameSize & 0xFFFF);
1119 .addImm(TOCSaveOffset)
1149 .addImm(FPOffset-LastOffset);
1161 .addImm(PBPOffset-LastOffset);
1172 .addImm(BPOffset-LastOffset);
1181 .addImm(-LastOffset);
1192 .addImm(FPOffset)
1197 .addImm(PBPOffset)
1202 .addImm(BPOffset)
1217 .addImm(FrameSize + FPOffset)
1222 .addImm(FrameSize + PBPOffset)
1227 .addImm(FrameSize + BPOffset)
1231 .addImm(FrameSize);
1549 .addReg(FPReg).addImm(FrameSize);
1552 .addImm(FrameSize >> 16);
1555 .addImm(FrameSize & 0xFFFF);
1565 .addImm(FrameSize);
1588 .addImm(0)
1607 .addImm(getCRSaveOffset())
1621 .addImm(LROffset+SPAdd)
1631 .addImm(getCRSaveOffset())
1640 .addImm(FPOffset)
1644 .addImm(FPOffset)
1650 .addImm(PBPOffset)
1655 .addImm(BPOffset)
1670 .addImm(SPAdd);
1681 .addImm(LROffset)
1706 .addReg(SPReg).addImm(CallerAllocatedAmt);
1709 .addImm(CallerAllocatedAmt >> 16);
1712 .addImm(CallerAllocatedAmt & 0xFFFF);
1747 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1760 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
2329 .addImm(CalleeAmt);
2333 .addImm(CalleeAmt >> 16);
2336 .addImm(CalleeAmt & 0xFFFF);
lib/Target/PowerPC/PPCISelLowering.cpp10398 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
10406 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
10514 .addImm(3)
10515 .addImm(27)
10516 .addImm(is8bit ? 28 : 27);
10520 .addImm(is8bit ? 24 : 16);
10524 .addImm(0)
10525 .addImm(61);
10529 .addImm(0)
10530 .addImm(0)
10531 .addImm(29);
10534 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
10536 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
10539 .addImm(65535);
10581 .addImm(CmpPred)
10594 .addImm(PPC::PRED_NE)
10685 .addImm(TOCOffset)
10701 .addImm(BPOffset)
10709 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
10728 .addImm(LabelOffset)
10733 .addImm(LabelOffset)
10738 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
10790 .addImm(0)
10794 .addImm(0)
10802 .addImm(LabelOffset)
10806 .addImm(LabelOffset)
10814 .addImm(SPOffset)
10818 .addImm(SPOffset)
10826 .addImm(BPOffset)
10830 .addImm(BPOffset)
10839 .addImm(TOCOffset)
10974 .addImm(SelectPred)
11028 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
11029 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
11030 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
11038 .addImm(PPC::PRED_NE)
11215 .addImm(PPC::PRED_NE)
11227 .addImm(PPC::PRED_NE)
11339 .addImm(3)
11340 .addImm(27)
11341 .addImm(is8bit ? 28 : 27);
11345 .addImm(is8bit ? 24 : 16);
11349 .addImm(0)
11350 .addImm(61);
11354 .addImm(0)
11355 .addImm(0)
11356 .addImm(29);
11364 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
11366 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
11369 .addImm(65535);
11392 .addImm(PPC::PRED_NE)
11410 .addImm(PPC::PRED_NE)
11446 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
11447 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
11453 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
11472 .addImm(1);
11487 BuildMI(*BB, MI, Dl, TII->get(PPC::TBEGIN)).addImm(Imm);
11509 .addImm(31);
11512 .addImm(30);
11555 .addImm(0)
11568 .addImm(0)
11603 .addImm(1);
11609 .addImm(0)
11610 .addImm(62);
11618 .addImm(255)
11620 .addImm(0)
11621 .addImm(0);
lib/Target/PowerPC/PPCInstrBuilder.h 35 return MIB.addImm(Offset).addFrameIndex(FI);
37 return MIB.addFrameIndex(FI).addImm(Offset);
lib/Target/PowerPC/PPCInstrInfo.cpp 431 .addImm((ME + 1) & 31)
432 .addImm((MB - 1) & 31);
730 .addImm(Cond[0].getImm())
747 .addImm(Cond[0].getImm())
941 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
942 .addImm(31)
943 .addImm(31);
1454 .addImm(Pred[0].getImm())
1486 .addImm(Pred[0].getImm())
1515 .addImm(Pred[0].getImm())
2144 .addImm(Offset)
2224 .addImm(PPC::PRED_NE_MINUS)
2226 .addImm(1);
2312 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2320 .addImm(LII.Imm);
3801 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3802 .addImm(ME);
3810 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
lib/Target/PowerPC/PPCMIPeephole.cpp 662 .addImm(PPC::sub_32);
788 .addImm(LiImm); // restore the imm of LI
lib/Target/PowerPC/PPCRegisterInfo.cpp 535 .addImm(FrameSize);
539 .addImm(FrameSize);
542 .addImm(0)
546 .addImm(0)
563 .addImm(~(MaxAlign-1));
579 .addImm(maxCallFrameSize);
588 .addImm(~(MaxAlign-1));
604 .addImm(maxCallFrameSize);
630 .addImm(maxCallFrameSize);
674 .addImm(getEncodingValue(SrcReg) * 4)
675 .addImm(0)
676 .addImm(31);
719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
720 .addImm(31);
774 .addImm(0);
778 .addImm(-32768);
799 .addImm(getEncodingValue(SrcReg))
800 .addImm(0).addImm(0);
800 .addImm(0).addImm(0);
844 .addImm(ShiftBits ? 32 - ShiftBits : 0)
845 .addImm(ShiftBits)
846 .addImm(ShiftBits);
1102 .addImm(Offset);
1105 .addImm(Offset >> 16);
1108 .addImm(Offset);
1238 .addFrameIndex(FrameIdx).addImm(Offset);
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 112 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
113 .addImm(0);
130 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
130 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
lib/Target/PowerPC/PPCVSXCopy.cpp 108 .addImm(1) // add 1, not 0, because there is no implicit clearing
111 .addImm(PPC::sub_64);
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 806 .addImm(2);
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 261 .addImm(-1);
342 .addImm(-1);
463 .addImm(0);
lib/Target/RISCV/RISCVFrameLowering.cpp 76 .addImm(Val)
215 .addImm(-(int)MaxAlignment);
222 .addImm(ShiftAmount);
225 .addImm(ShiftAmount);
lib/Target/RISCV/RISCVISelLowering.cpp 1129 .addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding)
1132 .addImm(RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding)
1135 .addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding)
1172 .addImm(0)
1176 .addImm(4)
1203 .addImm(0)
1208 .addImm(4)
lib/Target/RISCV/RISCVInstrInfo.cpp 92 .addImm(0);
134 .addImm(0);
158 BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
187 .addImm(Inst.Imm)
192 .addImm(Inst.Imm)
lib/Target/Sparc/DelaySlotFiller.cpp 156 TII->get(SP::UNIMP)).addImm(structSize);
lib/Target/Sparc/SparcFrameLowering.cpp 53 .addReg(SP::O6).addImm(NumBytes);
65 .addImm(HI22(NumBytes));
67 .addReg(SP::G1).addImm(LO10(NumBytes));
78 .addImm(HIX22(NumBytes));
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
187 .addReg(SP::O6).addImm(Bias);
194 .addReg(regUnbiased).addImm(MaxAlign - 1);
199 .addReg(regUnbiased).addImm(-Bias);
lib/Target/Sparc/SparcISelLowering.cpp 3155 .addImm(CC);
lib/Target/Sparc/SparcInstrInfo.cpp 263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
410 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
413 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
416 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
419 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
422 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
427 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
448 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
451 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
454 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
457 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
460 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
465 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
504 .addImm(Offset);
lib/Target/Sparc/SparcRegisterInfo.cpp 133 .addImm(HI22(Offset));
151 .addImm(HIX22(Offset));
153 .addReg(SP::G1).addImm(LOX10(Offset));
190 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
202 .addReg(FrameReg).addImm(0);
lib/Target/SystemZ/SystemZFrameLowering.cpp 190 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
269 MIB.addImm(StartOffset);
334 .addReg(Reg).addImm(ThisVal);
413 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
lib/Target/SystemZ/SystemZISelLowering.cpp 6514 .addImm(0)
6685 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
6685 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
6750 .addImm(Disp)
6751 .addImm(CCValid)
6752 .addImm(CCMask)
6779 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
6779 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
6790 .addImm(Disp)
6856 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
6873 .addReg(OldVal).addReg(BitShift).addImm(0);
6881 .addReg(Tmp).addImm(-1U << (32 - BitSize));
6888 .addReg(Tmp2).addImm(-1);
6900 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
6900 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
6900 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
6903 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
6908 .addImm(Disp);
6910 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
6910 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
6976 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
6990 .addReg(OldVal).addReg(BitShift).addImm(0);
6994 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
6994 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
7005 .addImm(32).addImm(31 + BitSize).addImm(0);
7005 .addImm(32).addImm(31 + BitSize).addImm(0);
7005 .addImm(32).addImm(31 + BitSize).addImm(0);
7021 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
7026 .addImm(Disp);
7028 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7028 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7088 .addImm(Disp)
7117 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
7119 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7119 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7119 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7123 .addImm(SystemZ::CCMASK_ICMP)
7124 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
7139 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7139 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7139 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7141 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
7146 .addImm(Disp);
7148 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7148 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7180 .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
7182 .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);
7210 .addImm(0);
7212 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
7216 .addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);
7297 .addImm(SystemZ::PFD_WRITE)
7298 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
7300 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
7300 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
7301 .addReg(ThisSrcReg).addImm(SrcDisp);
7304 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7304 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7322 .addReg(ThisDestReg).addImm(256).addReg(0);
7325 .addReg(ThisSrcReg).addImm(256).addReg(0);
7327 .addReg(ThisCountReg).addImm(-1);
7329 .addReg(NextCountReg).addImm(0);
7331 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7331 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7354 .addImm(DestDisp)
7363 .addImm(SrcDisp)
7370 .addImm(DestDisp)
7371 .addImm(ThisLength)
7373 .addImm(SrcDisp)
7383 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7383 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
7450 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
7450 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
lib/Target/SystemZ/SystemZInstrBuilder.h 40 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
lib/Target/SystemZ/SystemZInstrInfo.cpp 229 .addImm(32);
237 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
269 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
269 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
269 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
505 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
505 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
605 .addImm(CCValid).addImm(CCMask);
605 .addImm(CCValid).addImm(CCMask);
728 .addImm(CCValid).addImm(CCMask)
728 .addImm(CCValid).addImm(CCMask)
735 .addImm(CCValid).addImm(CCMask)
735 .addImm(CCValid).addImm(CCMask)
746 .addImm(CCValid)
747 .addImm(CCMask)
758 .addImm(CCValid).addImm(CCMask)
758 .addImm(CCValid).addImm(CCMask)
818 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
835 .addImm(3 << (SystemZ::IPM_CC - 16));
979 .addImm(Start)
980 .addImm(End + 128)
981 .addImm(0);
1023 .addImm(0)
1024 .addImm(MI.getOperand(2).getImm());
1050 .addImm(0)
1051 .addImm(MI.getOperand(2).getImm());
1065 .addImm(0)
1066 .addImm((int8_t)MI.getOperand(2).getImm());
1080 .addImm(0)
1081 .addImm((int8_t)-MI.getOperand(2).getImm());
1097 .addImm(0)
1108 .addImm(0)
1134 .addImm(0)
1135 .addImm(Size)
1137 .addImm(MI.getOperand(2).getImm())
1145 .addImm(MI.getOperand(2).getImm())
1146 .addImm(Size)
1148 .addImm(0)
1199 MIB.addFrameIndex(FrameIndex).addImm(Offset);
1748 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
lib/Target/SystemZ/SystemZLongBranch.cpp 361 .addImm(-1);
363 .addImm(SystemZ::CCMASK_ICMP)
364 .addImm(SystemZ::CCMASK_CMP_NE)
381 .addImm(SystemZ::CCMASK_ICMP)
lib/Target/SystemZ/SystemZPostRewrite.cpp 194 .addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB);
194 .addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB);
lib/Target/SystemZ/SystemZRegisterInfo.cpp 318 .addReg(BasePtr).addImm(HighOffset).addReg(0);
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 331 .addImm(int64_t(ReturnType));
410 .addImm(int64_t(WebAssembly::BlockType::Void));
579 .addImm(int64_t(WebAssembly::BlockType::Void));
1133 .addImm(int64_t(WebAssembly::BlockType::Void));
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 250 .addImm(LocalId);
261 .addImm(LocalId)
294 .addImm(LocalId)
352 .addImm(LocalId);
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 389 .addImm(0);
400 MIB.addImm(0);
405 MIB.addImm(Addr.getOffset());
465 .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));
495 .addImm(32 - MVT(From).getSizeInBits());
714 .addImm(I);
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 443 .addImm(Indices[Entry]);
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 195 .addImm(StackSize);
207 .addImm((int)~(Alignment - 1));
249 .addImm(StackSize);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 414 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute);
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 345 BuildMI(ElseMBB, DL, TII.get(WebAssembly::CONST_I32), Reg).addImm(0);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 128 .addImm(0);
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 123 .addImm(FrameOffset);
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 400 .addImm(1)
402 .addImm(LoadDisp)
420 .addImm(1)
422 .addImm(StoreDisp)
lib/Target/X86/X86CallFrameOptimization.cpp 548 .addImm(X86::sub_32bit);
lib/Target/X86/X86CallLowering.cpp 192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
440 .addImm(Handler.getNumXmmRegs());
481 CallSeqStart.addImm(Handler.getStackSize())
482 .addImm(0 /* see getFrameTotalSize */)
483 .addImm(0 /* see getFrameAdjustment */);
487 .addImm(Handler.getStackSize())
488 .addImm(0 /* NumBytesForCalleeToPop */);
lib/Target/X86/X86CmovConversion.cpp 691 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
lib/Target/X86/X86CondBrFolding.cpp 228 .addMBB(NewDest).addImm(MBBInfo->BranchCode);
255 .addMBB(MBBInfo->TBB).addImm(CC);
324 .addMBB(RootMBBInfo->FBB).addImm(NewCC);
lib/Target/X86/X86ExpandPseudo.cpp 94 .addImm(1)
113 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
255 MIB.addImm(MBBI->getOperand(2).getImm());
318 .addImm(StackAdj);
lib/Target/X86/X86FastISel.cpp 503 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
685 addFullAddress(MIB, AM).addImm(Signed ? (uint64_t) CI->getSExtValue()
1280 .addImm(X86MFInfo->getBytesToPopOnReturn());
1408 .addImm(Op1C->getSExtValue());
1450 ResultReg).addImm(1);
1492 FlagReg1).addImm(SETFOpc[0]);
1494 FlagReg2).addImm(SETFOpc[1]);
1514 ResultReg).addImm(CC);
1557 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1557 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1695 .addMBB(TrueMBB).addImm(CC);
1701 .addMBB(TrueMBB).addImm(X86::COND_P);
1726 .addReg(OpReg).addImm(1);
1735 .addMBB(TrueMBB).addImm(JmpCond);
1749 .addMBB(TrueMBB).addImm(CC);
1772 .addImm(1);
1774 .addMBB(TrueMBB).addImm(X86::COND_NE);
1969 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1969 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1995 ResultSuperReg).addReg(SourceSuperReg).addImm(8);
2071 FlagReg1).addImm(SETFOpc[0]);
2073 FlagReg2).addImm(SETFOpc[1]);
2118 .addImm(1);
2336 .addImm(1);
2794 .addImm(0)
2979 ResultReg2).addImm(CondCode);
3314 .addImm(NumBytes).addImm(0).addImm(0);
3314 .addImm(NumBytes).addImm(0).addImm(0);
3314 .addImm(NumBytes).addImm(0).addImm(0);
3468 X86::AL).addImm(NumXMMRegs);
3510 MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
3542 .addImm(NumBytes).addImm(NumBytesForCalleeToPop);
3542 .addImm(NumBytes).addImm(NumBytesForCalleeToPop);
3706 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
3706 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
lib/Target/X86/X86FixupLEAs.cpp 140 .addImm(1)
142 .addImm(0)
427 .addReg(BaseReg).addImm(Disp.getImm())
431 .addReg(BaseReg).addImm(Disp.getImm());
520 .addImm(Offset.getImm());
603 .addImm(0)
lib/Target/X86/X86FixupSetCC.cpp 152 .addImm(X86::sub_8bit);
lib/Target/X86/X86FlagsCopyLowering.cpp 745 TII->get(X86::SETCCr), Reg).addImm(Cond);
822 .addImm(Addend);
947 .addImm(0)
949 .addImm(SubRegIdx[OrigRegSize]);
lib/Target/X86/X86FrameLowering.cpp 276 .addImm(Offset)
302 .addImm(Offset)
388 .addImm(AbsOffset);
659 .addImm(X86::COND_B);
670 .addImm(1)
672 .addImm(ThreadEnvironmentStackLimit)
676 BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
682 .addImm(PageMask);
703 .addImm(1)
705 .addImm(0)
707 .addImm(0);
713 BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
868 .addImm(Val)
1130 .addImm(FramePtr)
1154 .addImm(FramePtr)
1155 .addImm(0)
1203 .addImm(Reg)
1218 .addImm(MaxAlign)
1268 .addImm(Alloc)
1272 .addImm(Alloc)
1276 .addImm(Alloc)
1283 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1309 .addImm(NumBytes)
1361 .addImm(FramePtr)
1362 .addImm(SEHFrameOffset)
1403 .addImm(Reg)
1404 .addImm(Offset)
2151 .addImm(0)
2379 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2379 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2382 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2382 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2406 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2406 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2411 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2411 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2439 .addImm(TlsOffset);
2442 .addReg(ScratchReg2).addImm(1).addReg(0)
2443 .addImm(0)
2453 BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2471 .addImm(StackSize);
2473 .addImm(X86FI->getArgumentStackSize());
2476 .addImm(X86FI->getArgumentStackSize());
2478 .addImm(StackSize);
2503 .addImm(0)
2695 BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2704 BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
2981 .addImm(EndOffset)
3224 .addImm(-2);
lib/Target/X86/X86ISelLowering.cpp29227 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), mainDstReg).addImm(-1);
29392 .addImm(MaxOffset + 8 - ArgSizeA8);
29397 .addMBB(overflowMBB).addImm(X86::COND_AE);
29417 .addImm(0)
29419 .addImm(X86::sub_32bit);
29430 .addImm(UseFPOffset ? 16 : 8);
29471 .addImm(Align-1);
29475 .addImm(~(uint64_t)(Align-1));
29486 .addImm(ArgSizeA8);
29554 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
29574 .addImm(/*Scale=*/1)
29576 .addImm(/*Disp=*/Offset)
29836 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
29840 BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
29996 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
30076 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
30076 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
30078 BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
30109 .addImm(12);
30119 .addImm(16);
30209 BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
30209 BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
30209 BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
30217 BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0);
30217 BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0);
30248 .addImm(0)
30260 .addImm(0)
30272 .addImm(0)
30545 .addImm(0)
30553 .addImm(0)
30611 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
30705 BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30735 BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
30745 .addImm(Offset);
30755 .addImm(8);
30758 BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30772 .addImm(128);
30793 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
30912 .addImm(1)
30919 .addImm(1)
31037 .addImm(LPadList.size());
31038 BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
31047 .addImm(1)
31053 .addImm(0)
31055 .addImm(X86::sub_32bit);
31062 .addImm(8)
31064 .addImm(0)
31075 .addImm(4)
31077 .addImm(0)
31096 .addImm(4)
31271 .addReg(OldCW, RegState::Kill).addImm(0xC00);
lib/Target/X86/X86InsertPrefetch.cpp 226 .addImm(
230 .addImm(Current->getOperand(MemOpOffset + X86::AddrDisp).getImm() +
lib/Target/X86/X86InstrBuilder.h 127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
187 MIB.addImm(AM.Disp);
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
lib/Target/X86/X86InstrInfo.cpp 661 .addImm(Value);
810 MIB.addReg(0).addImm(1ULL << ShAmt)
811 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
936 .addImm(1ULL << ShAmt)
938 .addImm(0)
961 .addImm(1ULL << ShAmt)
963 .addImm(0)
2463 MIB.addImm(0); // Stack offset (not used).
2593 .addImm(BranchCode);
2797 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2799 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2810 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2812 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2816 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2879 .addImm(Cond[0].getImm());
3951 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3958 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3996 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4001 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4001 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4058 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4073 MIB.addImm(ShiftAmt);
4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4169 .addReg(Reg, RegState::Undef).addImm(0xff);
4184 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4724 return MIB.addImm(0);
7778 .addImm(0)
7793 .addImm(0)
7810 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
lib/Target/X86/X86InstructionSelector.cpp 256 .addImm(0)
258 .addImm(getSubRegIndex(SrcRC));
580 MIB.addImm(0).addReg(0);
837 .addImm(0)
839 .addImm(X86::sub_32bit);
865 .addImm(0)
867 .addImm(X86::sub_8bit);
873 .addImm(1);
928 .addImm(0)
930 .addImm(getSubRegIndex(SrcRC));
978 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
1040 TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]);
1042 TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]);
1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1343 .addImm(Idx * DefSize);
1383 .addImm((Idx - 1) * SrcSize);
1413 .addImm(1);
1415 .addMBB(DestMBB).addImm(X86::COND_NE);
1670 .addImm(0)
1672 .addImm(X86::sub_32bit);
1699 .addImm(8);
1705 .addImm(0)
1707 .addImm(X86::sub_8bit);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 448 .addImm(PoisonVal);
491 .addImm(0)
493 .addImm(X86::sub_32bit);
760 .addImm(Cond);
1120 .addImm(/*Scale*/ 1)
1160 .addImm(/*Scale*/ 1)
1183 .addImm(X86::COND_NE);
1914 .addImm(47);
1939 .addImm(TRI->getRegSizeInBits(*PS->RC) - 1);
2504 .addImm(/*Scale*/ 1)
2522 .addImm(/*Scale*/ 1)
2524 .addImm(/*Displacement*/ -8) // The stack pointer has been popped, so
2546 .addImm(/*Scale*/ 1)
2564 .addImm(X86::COND_NE);
lib/Target/X86/X86WinAllocaExpander.cpp 241 .addImm(Amount);
lib/Target/XCore/XCoreFrameLowering.cpp 107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
203 .addImm(Offset)
242 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
265 MIB.addImm(Adjusted);
291 .addImm(Offset)
307 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
402 .addImm(RemainingAdj);
409 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
518 New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode)).addImm(Amount);
523 .addImm(Amount);
lib/Target/XCore/XCoreInstrInfo.cpp 341 .addImm(0);
346 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
377 .addImm(0)
398 .addImm(0)
436 .addImm(N)
441 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
lib/Target/XCore/XCoreRegisterInfo.cpp 72 .addImm(Offset)
79 .addImm(Offset)
85 .addImm(Offset);
141 .addImm(Offset)
148 .addImm(Offset)
154 .addImm(Offset);
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
tools/llvm-exegesis/lib/Assembler.cpp 108 Builder.addImm(Op.getImm());
tools/llvm-exegesis/lib/X86/Target.cpp 657 .addImm(-1);
660 .addImm(X86::COND_NE);