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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/DFAPacketizer.h 45 class MCInstrDesc;
include/llvm/CodeGen/FastISel.h 52 class MCInstrDesc;
include/llvm/CodeGen/GlobalISel/Utils.h 31 class MCInstrDesc;
include/llvm/CodeGen/MachineFunction.h 65 class MCInstrDesc;
include/llvm/CodeGen/MachineInstrBuilder.h 38 class MCInstrDesc;
include/llvm/CodeGen/ScheduleDAG.h 38 class MCInstrDesc;
lib/CodeGen/SelectionDAG/InstrEmitter.h 25 class MCInstrDesc;
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h 29 class MCInstrDesc;
lib/Target/Mips/Mips16InstrInfo.h 24 class MCInstrDesc;
References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6846 extern const MCInstrDesc AArch64Insts[] = {
18460 extern const MCInstrDesc AArch64Insts[];
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16061 extern const MCInstrDesc AMDGPUInsts[] = {
48063 extern const MCInstrDesc AMDGPUInsts[];
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 637 extern const MCInstrDesc R600Insts[] = {
1745 extern const MCInstrDesc R600Insts[];
gen/lib/Target/ARC/ARCGenInstrInfo.inc 642 extern const MCInstrDesc ARCInsts[] = {
1821 extern const MCInstrDesc ARCInsts[];
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5832 extern const MCInstrDesc ARMInsts[] = {
14489 extern const MCInstrDesc ARMInsts[];
gen/lib/Target/AVR/AVRGenInstrInfo.inc 482 extern const MCInstrDesc AVRInsts[] = {
1235 extern const MCInstrDesc AVRInsts[];
gen/lib/Target/BPF/BPFGenInstrInfo.inc 419 extern const MCInstrDesc BPFInsts[] = {
1110 extern const MCInstrDesc BPFInsts[];
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3629 extern const MCInstrDesc HexagonInsts[] = {
9987 extern const MCInstrDesc HexagonInsts[];
gen/lib/Target/Lanai/LanaiGenInstrInfo.inc 369 extern const MCInstrDesc LanaiInsts[] = {
979 extern const MCInstrDesc LanaiInsts[];
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 640 extern const MCInstrDesc MSP430Insts[] = {
1753 extern const MCInstrDesc MSP430Insts[];
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4814 extern const MCInstrDesc MipsInsts[] = {
10437 extern const MCInstrDesc MipsInsts[];
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 6630 extern const MCInstrDesc NVPTXInsts[] = {
19090 extern const MCInstrDesc NVPTXInsts[];
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2907 extern const MCInstrDesc PPCInsts[] = {
7533 extern const MCInstrDesc PPCInsts[];
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 661 extern const MCInstrDesc RISCVInsts[] = {
1741 extern const MCInstrDesc RISCVInsts[];
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 929 extern const MCInstrDesc SparcInsts[] = {
2435 extern const MCInstrDesc SparcInsts[];
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4319 extern const MCInstrDesc SystemZInsts[] = {
10475 extern const MCInstrDesc SystemZInsts[];
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 1554 extern const MCInstrDesc WebAssemblyInsts[] = {
4261 extern const MCInstrDesc WebAssemblyInsts[];
gen/lib/Target/X86/X86GenInstrInfo.inc17687 extern const MCInstrDesc X86Insts[] = {
49372 extern const MCInstrDesc X86Insts[];
gen/lib/Target/XCore/XCoreGenInstrInfo.inc 498 extern const MCInstrDesc XCoreInsts[] = {
1381 extern const MCInstrDesc XCoreInsts[];
include/llvm/CodeGen/DFAPacketizer.h 110 bool canReserveResources(const MCInstrDesc *MID);
114 void reserveResources(const MCInstrDesc *MID);
include/llvm/CodeGen/FastISel.h 476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
include/llvm/CodeGen/GlobalISel/Utils.h 80 MachineInstr &InsertPt, const MCInstrDesc &II,
include/llvm/CodeGen/MachineFunction.h 721 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL,
include/llvm/CodeGen/MachineInstr.h 112 const MCInstrDesc *MCID; // Instruction descriptor.
259 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
423 const MCInstrDesc &getDesc() const { return *MCID; }
1559 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
include/llvm/CodeGen/MachineInstrBuilder.h 317 const MCInstrDesc &MCID) {
324 const MCInstrDesc &MCID, Register DestReg) {
334 const DebugLoc &DL, const MCInstrDesc &MCID,
359 const DebugLoc &DL, const MCInstrDesc &MCID,
369 const DebugLoc &DL, const MCInstrDesc &MCID,
380 const MCInstrDesc &MCID) {
399 const MCInstrDesc &MCID) {
409 const MCInstrDesc &MCID) {
416 const MCInstrDesc &MCID) {
424 const MCInstrDesc &MCID, Register DestReg) {
433 const MCInstrDesc &MCID, bool IsIndirect,
440 const MCInstrDesc &MCID, bool IsIndirect,
449 const MCInstrDesc &MCID, bool IsIndirect,
457 const MCInstrDesc &MCID, bool IsIndirect,
include/llvm/CodeGen/MachinePipeliner.h 455 bool canReserveResources(const MCInstrDesc *MID) const;
459 void reserveResources(const MCInstrDesc *MID);
include/llvm/CodeGen/ScheduleDAG.h 581 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
614 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
include/llvm/CodeGen/TargetInstrInfo.h 89 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
include/llvm/MC/MCInstrInfo.h 24 const MCInstrDesc *Desc; // Raw array to allow static init'n
32 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND,
44 const MCInstrDesc &get(unsigned Opcode) const {
lib/CodeGen/BreakFalseDeps.cpp 198 const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/DFAPacketizer.cpp 105 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) {
113 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) {
122 const MCInstrDesc &MID = MI.getDesc();
129 const MCInstrDesc &MID = MI.getDesc();
lib/CodeGen/ExecutionDomainFix.cpp 237 const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 693 const MCInstrDesc &MCID = MII.get(Opcode);
lib/CodeGen/GlobalISel/Utils.cpp 73 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
lib/CodeGen/LiveDebugValues.cpp 284 const auto &IID = MI.getDesc();
lib/CodeGen/MIRParser/MIParser.cpp 506 const MCInstrDesc &MCID);
970 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1097 const MCInstrDesc &MCID) {
lib/CodeGen/MachineFunction.cpp 326 MachineInstr *MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
lib/CodeGen/MachineInstr.cpp 116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
1025 const MCInstrDesc &MCID = getDesc();
1409 const MCInstrDesc &MCID = getDesc();
2014 const MCInstrDesc &MCID, bool IsIndirect,
2030 const MCInstrDesc &MCID, bool IsIndirect,
lib/CodeGen/MachineLICM.cpp 1302 const MCInstrDesc &MID = TII->get(NewOpc);
lib/CodeGen/MachinePipeliner.cpp 2932 bool ResourceManager::canReserveResources(const MCInstrDesc *MID) const {
2973 void ResourceManager::reserveResources(const MCInstrDesc *MID) {
lib/CodeGen/MachineVerifier.cpp 921 const MCInstrDesc &MCID = MI->getDesc();
1481 const MCInstrDesc &MCID = MI->getDesc();
1595 const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/PeepholeOptimizer.cpp 1314 const MCInstrDesc &MCID = MI.getDesc();
1333 const MCInstrDesc &MCID = MI.getDesc();
1755 const MCInstrDesc &MIDesc = MI->getDesc();
lib/CodeGen/ReachingDefAnalysis.cpp 101 const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/RegAllocFast.cpp 1013 const MCInstrDesc &MCID = MI.getDesc();
lib/CodeGen/RegisterCoalescer.cpp 1238 const MCInstrDesc &MCID = DefMI->getDesc();
lib/CodeGen/RenameIndependentSubregs.cpp 331 const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF);
lib/CodeGen/ScheduleDAG.cpp 70 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
lib/CodeGen/ScheduleDAGInstrs.cpp 238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
264 const MCInstrDesc *UseMIDesc =
lib/CodeGen/ScoreboardHazardRecognizer.cpp 122 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
lib/CodeGen/SelectionDAG/FastISel.cpp 840 const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
1407 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
2020 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
2040 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2049 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2071 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2096 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2122 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2145 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2169 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2189 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2214 const MCInstrDesc &II = TII.get(MachineInstOpcode);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
191 const MCInstrDesc &II,
294 const MCInstrDesc *II,
303 const MCInstrDesc &MCID = MIB->getDesc();
365 const MCInstrDesc *II,
634 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
712 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
771 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
810 const MCInstrDesc &II = TII->get(Opc);
954 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
lib/CodeGen/SelectionDAG/InstrEmitter.h 47 const MCInstrDesc &II,
62 const MCInstrDesc *II,
73 const MCInstrDesc *II,
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 436 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
538 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 254 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
432 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
511 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 341 const MCInstrDesc Desc = TII->get(Opcode);
1034 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1283 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1412 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
2819 const MCInstrDesc &MCID = TII->get(Opc);
3064 const MCInstrDesc &MCID = TII->get(Opc);
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 126 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
212 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
315 const MCInstrDesc &MCID = TII->get(Opc);
449 const MCInstrDesc &MCID = TII->get(Opc);
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 642 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
1258 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
3485 const MCInstrDesc &MCID = TII->get(TargetOpc);
lib/CodeGen/SplitKit.cpp 515 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
541 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
lib/CodeGen/TailDuplicator.cpp 982 const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
lib/CodeGen/TargetInstrInfo.cpp 45 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
159 const MCInstrDesc &MCID = MI.getDesc();
291 const MCInstrDesc &MCID = MI.getDesc();
327 const MCInstrDesc &MCID = MI.getDesc();
lib/CodeGen/TwoAddressInstructionPass.cpp 1357 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1463 const MCInstrDesc &MCID = MI->getDesc();
lib/MC/MCDisassembler/Disassembler.cpp 180 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
207 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
lib/MC/MCParser/AsmParser.cpp 5809 const MCInstrDesc &Desc = MII->get(Info.Opcode);
lib/MCA/InstrBuilder.cpp 203 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc,
218 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) {
249 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
419 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
515 const MCInstrDesc &MCDesc = MCII.get(Opcode);
lib/Target/AArch64/AArch64ConditionalCompares.cpp 632 const MCInstrDesc &MCID = TII->get(Opc);
689 const MCInstrDesc &MCID = TII->get(Opc);
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 141 const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 94 const MCInstrDesc &Desc = OldMI.getDesc();
lib/Target/AArch64/AArch64FastISel.cpp 1138 const MCInstrDesc &II = MIB->getDesc();
1343 const MCInstrDesc &II = TII.get(Opc);
1388 const MCInstrDesc &II = TII.get(Opc);
1430 const MCInstrDesc &II = TII.get(Opc);
1475 const MCInstrDesc &II = TII.get(Opc);
2101 const MCInstrDesc &II = TII.get(Opc);
2170 const MCInstrDesc &II = TII.get(Opc);
2393 const MCInstrDesc &II = TII.get(Opc);
2538 const MCInstrDesc &II = TII.get(Opcode);
2557 const MCInstrDesc &II = TII.get(AArch64::BR);
2809 const MCInstrDesc &II = TII.get(AArch64::ANDSWri);
3268 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
3301 const MCInstrDesc &II = TII.get(AArch64::BLR);
5111 const MCInstrDesc &II = TII.get(Opc);
lib/Target/AArch64/AArch64InstrInfo.cpp 93 const MCInstrDesc &Desc = MI.getDesc();
1199 const MCInstrDesc &MCID = get(NewOpc);
lib/Target/AArch64/AArch64RegisterInfo.cpp 416 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
161 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
219 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) {
274 const MCInstrDesc* OriginalMCID;
275 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID;
351 const MCInstrDesc *MulMCID, *DupMCID;
417 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID;
510 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID;
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 3891 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 317 const auto &Desc = Info->get(Inst.getOpcode());
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 565 const MCInstrDesc &Desc =
2658 MCInstrDesc Desc = SII->get(Opc);
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1700 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
2718 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2742 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2812 const MCInstrDesc &Desc = MII.get(Opcode);
2891 const MCInstrDesc &Desc = MII.get(Opcode);
2929 const MCInstrDesc &Desc = MII.get(Opc);
2943 const MCInstrDesc &Desc = MII.get(Opc);
2975 const MCInstrDesc &Desc = MII.get(Opc);
3016 const MCInstrDesc &Desc = MII.get(Opc);
3036 const MCInstrDesc &Desc = MII.get(Opc);
3055 const MCInstrDesc &Desc = MII.get(Opc);
3071 const MCInstrDesc &Desc = MII.get(Opc);
3220 const MCInstrDesc &Desc = MII.get(Opcode);
3304 const MCInstrDesc &Desc = MII.get(Opcode);
3361 const MCInstrDesc &Desc = MII.get(Opcode);
5913 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6183 static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
6200 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6238 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6305 const MCInstrDesc &Desc = MII.get(Opc);
6682 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6841 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 675 const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 127 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
505 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
577 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp 105 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 286 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
381 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
475 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
490 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 250 const MCInstrDesc &getHWInstrDesc(ControlFlowInstruction CFI) const {
lib/Target/AMDGPU/SIFoldOperands.cpp 160 const MCInstrDesc &MadDesc = TII->get(Opc);
486 const MCInstrDesc &Desc = UseMI->getDesc();
820 const MCInstrDesc &UseDesc = UseMI->getDesc();
840 const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
929 const MCInstrDesc &Desc = MI.getDesc();
938 static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
lib/Target/AMDGPU/SIFrameLowering.cpp 550 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
557 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64);
585 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM);
606 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
618 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
624 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
lib/Target/AMDGPU/SIISelLowering.cpp 3533 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3566 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
lib/Target/AMDGPU/SIInstrInfo.cpp 1068 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1196 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1481 const MCInstrDesc &MovRelDesc = get(AMDGPU::V_MOVRELD_B32_e32);
1723 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
2926 const MCInstrDesc &InstDesc = MI.getDesc();
3204 const MCInstrDesc &Desc = get(Opcode);
3810 const MCInstrDesc &Desc = get(MI.getOpcode());
3953 const MCInstrDesc &InstDesc = MI.getDesc();
4015 const MCInstrDesc &InstrDesc = get(Opc);
5006 const MCInstrDesc &NewDesc = get(NewOpcode);
5298 const MCInstrDesc &InstDesc = get(Opcode);
5425 const MCInstrDesc &InstDesc = get(Opcode);
5529 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
5785 const MCInstrDesc &Desc = MI.getDesc();
5982 const MCInstrDesc &Desc = getMCOpcodeFromPseudo(Opc);
6231 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {
lib/Target/AMDGPU/SIInstrInfo.h 256 bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
929 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1001 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1020 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 899 const MCInstrDesc &Read2Desc = TII->get(Opc);
935 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
997 const MCInstrDesc &Write2Desc = TII->get(Opc);
1073 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1123 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1185 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1006 const MCInstrDesc &SDWADesc = TII->get(SDWAOpcode);
1175 const MCInstrDesc &Desc = TII->get(MI.getOpcode());
lib/Target/AMDGPU/SIRegisterInfo.cpp 629 const MCInstrDesc &Desc = TII->get(LoadStoreOp);
lib/Target/AMDGPU/SIShrinkInstructions.cpp 212 const MCInstrDesc &NewDesc = TII->get(SOPKOpc);
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1039 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1046 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1070 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1132 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 560 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
563 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
566 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
575 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
615 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
lib/Target/ARC/ARCInstrInfo.cpp 413 const MCInstrDesc &MID = MI.getDesc();
419 const MCInstrDesc &MID = MI.getDesc();
lib/Target/ARM/ARMBaseInstrInfo.cpp 169 const MCInstrDesc &MCID = MI.getDesc();
705 const MCInstrDesc &MCID = MI.getDesc();
2260 const MCInstrDesc &DefDesc = DefMI->getDesc();
2524 const MCInstrDesc &Desc = MI.getDesc();
3215 const MCInstrDesc &DefMCID = DefMI.getDesc();
3225 const MCInstrDesc &UseMCID = UseMI.getDesc();
3336 const MCInstrDesc &Desc = MI.getDesc();
3639 const MCInstrDesc &Desc = MI.getDesc();
3749 const MCInstrDesc &DefMCID,
3806 const MCInstrDesc &DefMCID,
3841 const MCInstrDesc &UseMCID,
3881 const MCInstrDesc &UseMCID,
3910 const MCInstrDesc &DefMCID,
3912 const MCInstrDesc &UseMCID,
4077 const MCInstrDesc &DefMCID, unsigned DefAlign) {
4291 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4293 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4356 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4371 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4614 const MCInstrDesc &MCID = MI.getDesc();
4645 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/ARM/ARMBaseInstrInfo.h 351 const MCInstrDesc &DefMCID,
355 const MCInstrDesc &DefMCID,
359 const MCInstrDesc &UseMCID,
363 const MCInstrDesc &UseMCID,
367 const MCInstrDesc &DefMCID,
369 const MCInstrDesc &UseMCID,
374 const MCInstrDesc &DefMCID, unsigned DefAdj,
377 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
lib/Target/ARM/ARMBaseRegisterInfo.cpp 499 const MCInstrDesc &Desc = MI->getDesc();
645 const MCInstrDesc &MCID = TII.get(ADDriOpc);
685 const MCInstrDesc &Desc = MI->getDesc();
813 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/ARM/ARMConstantIslandPass.cpp 2169 const MCInstrDesc &MCID = MI->getDesc();
2363 const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/ARMExpandPseudoInsts.cpp 94 const MCInstrDesc &Desc = OldMI.getDesc();
lib/Target/ARM/ARMFastISel.cpp 264 const MCInstrDesc &MCID = MI->getDesc();
305 const MCInstrDesc &II = TII.get(MachineInstOpcode);
328 const MCInstrDesc &II = TII.get(MachineInstOpcode);
356 const MCInstrDesc &II = TII.get(MachineInstOpcode);
381 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1444 const MCInstrDesc &II = TII.get(CmpOpc);
lib/Target/ARM/ARMFrameLowering.cpp 1532 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/ARM/ARMHazardRecognizer.cpp 21 const MCInstrDesc &MCID = MI->getDesc();
42 const MCInstrDesc &MCID = MI->getDesc();
45 const MCInstrDesc &LastMCID = LastMI->getDesc();
lib/Target/ARM/ARMISelDAGToDAG.cpp 449 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
lib/Target/ARM/ARMISelLowering.cpp 1747 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
10722 const MCInstrDesc *MCID = &MI.getDesc();
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 2322 const MCInstrDesc &MCID = TII->get(NewOpc);
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 74 extern const MCInstrDesc ARMInsts[];
2364 const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
7283 static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7291 static bool isVectorPredicable(const MCInstrDesc &MCID) {
7298 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10187 const MCInstrDesc &MCID = MII.get(Opc);
10304 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10337 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10361 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10388 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 685 extern const MCInstrDesc ARMInsts[];
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 1871 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/ARM/MLxExpansionPass.cpp 184 const MCInstrDesc &MCID = MI->getDesc();
284 const MCInstrDesc &MCID1 = TII->get(MulOpc);
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
339 const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/Thumb2ITBlockPass.cpp 171 const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/Thumb2InstrInfo.cpp 469 const MCInstrDesc &Desc = MI.getDesc();
706 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/ARM/Thumb2SizeReduction.cpp 254 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
645 const MCInstrDesc &MCID = MI->getDesc();
791 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
805 const MCInstrDesc &MCID = MI->getDesc();
865 const MCInstrDesc &MCID = MI->getDesc();
884 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
lib/Target/ARM/ThumbRegisterInfo.cpp 370 const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AVR/AVRInstrInfo.cpp 194 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
482 const MCInstrDesc &Desc = get(Opcode);
lib/Target/AVR/AVRInstrInfo.h 69 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp 285 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/Hexagon/HexagonBitSimplify.cpp 624 const MCInstrDesc &D = HII.get(Opc);
lib/Target/Hexagon/HexagonConstExtenders.cpp 873 const MCInstrDesc &D = HII->get(ExtOpc);
1066 const MCInstrDesc &D = HII->get(Opc);
1114 const MCInstrDesc &D = HII->get(IdxOpc);
lib/Target/Hexagon/HexagonConstPropagation.cpp 2871 const MCInstrDesc *NewD = (Ps & P::Zero) ?
2887 const MCInstrDesc *NewD;
3007 const MCInstrDesc &D = (V >= 0) ? HII.get(Hexagon::M2_macsip)
3151 const MCInstrDesc &JD = HII.get(Hexagon::J2_jump);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 741 const MCInstrDesc &D = HII->get(IfTrue ? Hexagon::J2_jumpt
798 const MCInstrDesc &D = HII->get(Opc);
921 const MCInstrDesc &D = HasBranch ? HII->get(Hexagon::J2_jump)
lib/Target/Hexagon/HexagonFrameLowering.cpp 892 const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
lib/Target/Hexagon/HexagonGenInsert.cpp 1415 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
lib/Target/Hexagon/HexagonGenMux.cpp 162 const MCInstrDesc &D = HII->get(Opc);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 909 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
954 MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
975 const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
1902 const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
lib/Target/Hexagon/HexagonInstrInfo.cpp 2176 const MCInstrDesc &MID = MI.getDesc();
lib/Target/Hexagon/HexagonOptAddrMode.cpp 126 const MCInstrDesc &MID = MI.getDesc();
193 const MCInstrDesc &UseMID = UseMI.getDesc();
356 const MCInstrDesc &MID = MI->getDesc();
415 const MCInstrDesc &MID = UseMI->getDesc();
443 const MCInstrDesc &MID = MI.getDesc();
624 const MCInstrDesc &UseMID = UseMI->getDesc();
671 const MCInstrDesc &MID = UseMI->getDesc();
lib/Target/Hexagon/HexagonStoreWidening.cpp 430 const MCInstrDesc &StD = TII->get(WOpc);
442 const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi);
453 const MCInstrDesc &StD = TII->get(WOpc);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 654 const MCInstrDesc& MCID = PacketMI.getDesc();
869 const MCInstrDesc& MCID = PI.getDesc();
884 const MCInstrDesc &D = HII->get(NewOpcode);
1052 const MCInstrDesc& TID = MI.getDesc();
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp 536 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 87 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
302 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
313 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
327 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
454 MCInstrDesc const &Desc =
529 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp 471 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
483 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
624 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp 223 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
820 MCInstrDesc const &Desc = getDesc(MCII, MCI);
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h 116 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
lib/Target/Hexagon/RDFGraph.cpp 627 const MCInstrDesc &D = In.getDesc();
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 229 MCInstrDesc MCID = MI->getDesc();
lib/Target/Lanai/LanaiInstrInfo.cpp 517 const MCInstrDesc &DefDesc = DefMI->getDesc();
lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp 85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/MSP430/MSP430InstrInfo.cpp 301 const MCInstrDesc &Desc = MI.getDesc();
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1712 extern const MCInstrDesc MipsInsts[];
1716 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
1784 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
2589 const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode());
3523 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3608 const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 222 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
lib/Target/Mips/MicroMipsSizeReduction.cpp 709 const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
lib/Target/Mips/Mips16InstrInfo.cpp 458 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
lib/Target/Mips/Mips16InstrInfo.h 100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
lib/Target/Mips/MipsBranchExpansion.cpp 338 const MCInstrDesc &NewDesc = TII->get(NewOpc);
lib/Target/Mips/MipsFastISel.cpp 2137 const MCInstrDesc &II = TII.get(MachineInstOpcode);
lib/Target/Mips/MipsInstrInfo.cpp 109 const MCInstrDesc &MCID = get(Opc);
686 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/Mips/MipsSEFrameLowering.cpp 213 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
lib/Target/Mips/MipsSEInstrInfo.cpp 703 const MCInstrDesc &Desc = get(Opc);
752 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
820 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 154 const MCInstrDesc &MCID = MI->getDesc();
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 81 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp 315 const MCInstrDesc &Desc = MCII.get(Opcode);
lib/Target/PowerPC/PPCFrameLowering.cpp 840 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
842 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
844 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
846 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
848 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
850 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
852 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
854 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
856 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
1408 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1410 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1412 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1414 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1416 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1418 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1420 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
lib/Target/PowerPC/PPCHazardRecognizers.cpp 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
lib/Target/PowerPC/PPCHazardRecognizers.h 32 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
lib/Target/PowerPC/PPCInstrInfo.cpp 1019 const MCInstrDesc &MCID = get(Opc);
1340 const MCInstrDesc &UseMCID = UseMI.getDesc();
1976 const MCInstrDesc &NewDesc = get(NewOpC);
lib/Target/PowerPC/PPCInstrInfo.h 467 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 178 const MCInstrDesc &MCID = TII->get(Opc);
lib/Target/PowerPC/PPCRegisterInfo.cpp 1233 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1259 const MCInstrDesc &MCID = MI.getDesc();
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp 179 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
251 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
lib/Target/RISCV/RISCVInstrInfo.cpp 494 MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
lib/Target/SystemZ/SystemZElimCompare.cpp 319 const MCInstrDesc &Desc = TII->get(Opcode);
lib/Target/SystemZ/SystemZHazardRecognizer.cpp 120 const MCInstrDesc &MID = MI->getDesc();
lib/Target/SystemZ/SystemZInstrBuilder.h 30 const MCInstrDesc &MCID = MI->getDesc();
lib/Target/SystemZ/SystemZInstrInfo.cpp 311 const MCInstrDesc &MCID = MI.getDesc();
903 const MCInstrDesc &MCID = MI->getDesc();
1186 const MCInstrDesc &MemDesc = get(MemOpcode);
1503 const MCInstrDesc &MCID = get(Opcode);
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp 54 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
227 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp 83 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 116 const MCInstrDesc &Desc = TII->get(getNonPseudoCallIndirectOpcode(MI));
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 210 const MCInstrDesc &Desc = MI->getDesc();
lib/Target/X86/AsmParser/X86AsmParser.cpp 3108 const MCInstrDesc &MCID = MII.get(Opc);
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp 86 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86BaseInfo.h 721 inline unsigned getOperandBias(const MCInstrDesc& Desc) {
lib/Target/X86/MCTargetDesc/X86InstComments.cpp 228 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp 323 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp 67 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 142 const MCInst &MI, const MCInstrDesc &Desc,
149 const MCInst &MI, const MCInstrDesc &Desc,
153 int MemOperand, const MCInstrDesc &Desc) const;
284 const MCInstrDesc &Desc = MCII.get(Opcode);
645 const MCInstrDesc &Desc,
1051 const MCInstrDesc &Desc) const {
1150 const MCInstrDesc &Desc,
1216 const MCInstrDesc &Desc = MCII.get(Opcode);
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
527 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 290 const MCInstrDesc &Descl = MI->getDesc();
lib/Target/X86/X86DomainReassignment.cpp 531 const MCInstrDesc &Desc = TII->get(MI.getOpcode());
566 const MCInstrDesc &Desc = DefMI->getDesc();
lib/Target/X86/X86EvexToVex.cpp 219 const MCInstrDesc &Desc = MI.getDesc();
lib/Target/X86/X86FastISel.cpp 639 const MCInstrDesc &Desc = TII.get(Opc);
2074 auto const &II = TII.get(SETFOpc[2]);
2788 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
3980 const MCInstrDesc &II = TII.get(MachineInstOpcode);
lib/Target/X86/X86FixupLEAs.cpp 446 const MCInstrDesc &Desc = MI.getDesc();
507 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
515 const MCInstrDesc &ADDri =
lib/Target/X86/X86InsertPrefetch.cpp 212 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
lib/Target/X86/X86InstrBuilder.h 202 const MCInstrDesc &MCID = MI->getDesc();
lib/Target/X86/X86InstrInfo.cpp 1980 const MCInstrDesc &Desc = MI.getDesc();
3198 const MCInstrDesc &Desc = MemOp.getDesc();
3878 const MCInstrDesc &Desc) {
3899 const MCInstrDesc &Desc, unsigned Reg) {
4021 const MCInstrDesc &LoadDesc,
4022 const MCInstrDesc &BroadcastDesc,
4044 const MCInstrDesc &StoreDesc,
4045 const MCInstrDesc &ExtractDesc,
4064 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
5469 const MCInstrDesc &MCID = get(Opc);
5610 const MCInstrDesc &MCID = get(Opc);
lib/Target/X86/X86OptimizeLEAs.cpp 336 const MCInstrDesc &Desc = MI.getDesc();
439 const MCInstrDesc &Desc = MI.getDesc();
505 const MCInstrDesc &Desc = MI.getDesc();
634 const MCInstrDesc &Desc = MI.getDesc();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 845 const MCInstrDesc &MCID = TII.get(UnfoldedOpc);
1701 const MCInstrDesc &Desc = MI.getDesc();
1779 const MCInstrDesc &Desc = MI.getDesc();
2177 const MCInstrDesc &Desc = UseMI.getDesc();
tools/llvm-cfi-verify/lib/FileAnalysis.cpp 170 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
175 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
192 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
207 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
286 const auto &InstrDesc = MII->get(InstrMetaPtr->Instruction.getOpcode());
338 const auto &InstrDesc = MII->get(NodeInstr.Instruction.getOpcode());
499 const auto &InstrDesc = MII->get(Instruction.getOpcode());
tools/llvm-cfi-verify/lib/GraphBuilder.cpp 234 const auto &ParentDesc =
tools/llvm-exegesis/lib/Assembler.cpp 95 const MCInstrDesc &MCID = MCII->get(Opcode);
tools/llvm-exegesis/lib/MCInstrDescView.h 136 const MCInstrDesc *Description; // Never nullptr.
tools/llvm-exegesis/llvm-exegesis.cpp 211 const MCInstrDesc &InstrDesc = *Instr.Description;
tools/llvm-mca/Views/InstructionInfoView.cpp 41 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
unittests/CodeGen/MachineInstrTest.cpp 177 MCInstrDesc MCID = {
246 MCInstrDesc MCID = {
320 MCInstrDesc MCID = {0, 1, 1, 0, 0, 0,
347 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0,
363 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0,
377 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0,
423 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0,
459 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0,
unittests/Target/ARM/MachineInstrTest.cpp 491 const MCInstrDesc &Desc = TII->get(i);